User manual

TB-7Z-020-EMC Hardware User Manual
17
Rev.1.03
7.2. Clock System
The TB-7Z-020-EMC board’s clock system diagram is showed in Figure 7-5.
PLL
5V49EE504NLGI
(U18)
OSC
33.33333MHz
CLKIN OUT0 PS_CLK_500
OUT1
XTAL_IN
OUT2
ZYNQ
XC7Z020-CLG484E
OUT3
OUT6
PS_CLK
ETH_CLK_25M
SYS_CLK4
SYS_CLK3
USB_CLK_26M
IO_L13P_T2_MRCC_33
IO_L12P_T1_MRCC_35
ETH_RXCLK
PS_MIO22_501 RX_CLK
TX_CLK
ETH_TXCLK
PS_MIO16_501
ETH_CLK_25M
Ethernet PHY
(U3)
DDR3
Component
I2C IFPS I2C IF
SEL0
SEL1
SEL2
DIPSW
(SW10)
DGND
DDR3 Memory
(U1, U2)
DDR3_CK/XCK
PS_DDR_CKP/N_502
REFCLK
USB_OTG_CLOCK
PS_MIO36_501 CLOCK
USB_CLK_26M
USB2.0 PHY(U5)
DVI_CLK
IO_L15P_T2_DQS_AD12P_35 IDCK+
DVI TX(U8)
FMC LPC CC (CN5)
FMC_CLK1P/N_M2C
CLK1_M2C_P/N
FMC_CLK0P/N_M2C
IO_L12P/N_T1_MRCC_33
IO_L12P/N_T1_MRCC_34CLK0_M2C_P/N
FMC LPC MC (CN4)
CLK1_M2C_P/N
CLK0_M2C_P/N
QSPI_CLK
PS_MIO6_500 CLK
QSPI FLASH(U13)
TRACECLK
IO_L12P_T1_MRCC_13TRACECLK
ARM TRACE PORT
(CN10)
No
Mount
CK/XCK
Figure 7-5 Clock System Diagram
Table 7-2 Clock signals pin assign
Zynq
Pin#
Zynq
Pin Name
Signal
Name
Connected component
F7
PS_CLK_500
PS_CLK)
OSC 33.33333MHz
A4
PS_MIO6_500
QSPI_CLK
QSFI FLASH (U13)
D6
PS_MIO16_501
ETH_TXCLK
Ethernet PHY (U3) TX_CLK
A14
PS_MIO22_501
ETH_RXCLK
Ethernet PHY (U3) RX_CLK
A9
PS_MIO36_501
USB_OTG_CLOCK
USB2.0 PHY (U5) Clock
N4
PS_DDR_CKP_502
DDR3_CK
DDR3 (U1, U2) Positive Clock
N5
PS_DDR_CKN_502
DDR3_XCK
DDR3 (U1, U2) Negative Clock
Y9
IO_L12P_T1_MRCC_13
TRACECLK
Mictor 38 (CN10) pin 6
W17
IO_L13P_T2_MRCC_33
SYS_CLK4
PLL (U18) Out 2
D18
IO_L12P_T1_MRCC_35
SYS_CLK3
PLL (U18) Out 3
Y18
IO_L12P_T1_MRCC_33
FMC_CLK1P_M2C
FMC(CN4, CN5) G2
AA18
IO_L12N_T1_MRCC_33
FMC_CLK1N_M2C
FMC(CN4, CN5) G3
L18
IO_L12P_T1_MRCC_34
FMC_CLK0P_M2C
FMC(CN4, CN5) H4
L19
IO_L12N_MRCC_34
FMC_CLK0N_M2C
FMC(CN4, CN5) H5