Hardware Reference Manual Contents 1 Document Details.................................................................................................................................. 7 1.1 Document History ......................................................................................................................... 7 1.2 Definition, Acronyms and Abbreviations ...................................................................................... 7 1.3 References ............................
Hardware Reference Manual 7 8 6.3.4 MIPI CSI Interface ................................................................................................................ 43 6.3.5 MIPI DSI Interface ............................................................................................................... 47 6.3.6 USB Interface ...................................................................................................................... 50 6.3.7 Gigabit Ethernet ..........................
Hardware Reference Manual List of Figures Figure 1 – ERAGON660 SBC Block Diagram ............................................................................................... 16 Figure 2 – ERAGON660 IO Card Block Diagram .......................................................................................... 17 Figure 3 – ERAGON660 Single Board Computer (SBC) Image ..................................................................... 18 Figure 4 – ERAGON660 IO Card Image................................
Hardware Reference Manual List of Tables Table 1: Document History ........................................................................................................................... 7 Table 2 : Definition, Acronyms and Abbreviations ....................................................................................... 8 Table 3 : References ......................................................................................................................................
Hardware Reference Manual 1 Document Details 1.1 Document History Author Description Of Changes Version Name Date 1.0 eInfochips 23-oct-2018 Initial release Table 1: Document History 1.
Hardware Reference Manual IC Integrated Circuit Inc.
Hardware Reference Manual 1.3 References No. Document Version 1 ERAGON660 SBC Schematic File 1.1 2. ERAGON660 IO Card Schematic File 1.1 Remarks Table 3 : References Version 1.
Hardware Reference Manual 2 License Agreement The use of this document is subject to and governed by those terms and conditions in the eInfochips Ltd. Purchase and Software License Agreement for the Qualcomm Snapdragon™ 660 based development platform, which you or the legal entity you represent, as the case may be, accepted and agreed to when purchasing ERAGON660 development platform from eInfochips Ltd. (“Agreement”).
Hardware Reference Manual 3 Preface This document provides an overview of the ERAGON660 SBC and development kit based on the Qualcomm Snapdragon™ 660. It provides step-by-step information about hardware components and associated software release Android 8.1.0 (Oreo). Intended Audience This document is intended to be used by for technically qualified personnel. It is not intended for general audiences.
Hardware Reference Manual 4 Overview The ERAGON660 SBC provides an ideal building block for simple integration with a wide range of products in target markets requiring rich multimedia functionality, powerful graphics processing and video capabilities, as well as high-processing power, in a compact, RoHS compliant, fan less, cost effective SBC with low power consumption.
Hardware Reference Manual Key Features CPU Audio PM660l(On SBC) :- Two single-ended and one differential (microphone) inputs Four outputs: EAR, HPHL + HPHR, and class-D speaker driver Supports 8, 16, 32, 44.1, 48, and 192 kHz sample rates WCD9335(On IO Card) :- IO Card has Audio codec WCD9335 along with two Audio Amplifiers WSA8810 • 3.5mm ANC Audio Jack • 2x 16 pin Audio header which supports.
Hardware Reference Manual Applications The ERAGON606 Kit is used in a wide range of products across many different target markets.
Hardware Reference Manual 5 Getting Started Prerequisites Before user power up the ERAGON660 board for the first time, will need following things: Sr No.
Hardware Reference Manual ERAGON660 6.1.1 ERAGON660 SBC (Single Board Computer) Image Figure 3 – ERAGON660 Single Board Computer (SBC) Image Version 1.
Hardware Reference Manual The ERAGON660 SBC offers a wide range of interfaces and peripherals, including several high-speed signals through its edge connectors. The major parts of ERAGON660 SBC are marked with labels in above figures and the name of it is, are listed in the below table. No. 1 No. 14 Interface Name Camera Connector (J2) 2 3 4 5 Interface Name U.FL connector for WIFI+BT External ANTENNA 1 Volume Down Switch Volume Up Switch Power on Switch USB 3.
Hardware Reference Manual 6.1.2 ERAGON660 IO Card Image Figure 4 – ERAGON660 IO Card Image Version 1.
Hardware Reference Manual The ERAGON660 IO Card offers a wide range of interfaces and peripherals, including several high-speed signals through its edge connectors. The major parts of ERAGON660 IO Card are marked with labels in above figures and the name of it is, are listed in the below table. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Interface Name EXPANSION Connector (J4) LPI EXPANSION Connector (J8) 4G LTE MODEM Connector (J11) U.
Hardware Reference Manual The Eragon660 SBC and IO Card are interfaced through three Hirose DF40C-100DP-0.4V (51) Connectors. The pin outs for these three connectors is described below, SBC Pin No. I/O Card Signal Name Pin No. Default Pin Function Voltage Level J16.1 J14.1 GND Ground - J16.2 J14.2 GND Ground - J16.3 J14.3 LPI_GPIO29_EXTR4 LPI_GPIO_29 1.8V J16.4 J14.4 LPI_I2C_3_SDA LPI_I2C_3_SDA 1.8V J16.5 J14.5 LPI_GPIO26_EXTR1 LPI_GPIO26 1.8V J16.6 J14.
Hardware Reference Manual J16.22 J14.22 VREG_L3A PM660 Linear regulator L3 output 1.0V J16.23 J14.23 HDMI_MI2S_3_D0 MI2S Data0 signal 1.8V J16.24 J14.24 BLSP_I2C_SDA_2 BLSP 2 - I2C DATA 1.8V J16.25 J14.25 HDMI_RST_N HDMI RESET 1.8V J16.26 J14.26 BLSP_I2C_SCL_2 BLSP 2 - I2C CLOCK 1.8V J16.27 J14.27 HDMI_INT_GPIO HDMI INTERRUPT 1.8V J16.28 J14.28 VREG_L1A PM660 Linear regulator L1 output 1.232V J16.29 J14.29 VCC_1V8 1.8V Switching Regulator input 1.8V J16.30 J14.
Hardware Reference Manual J16.45 J14.45 GND Ground - J16.46 J14.46 LTE_MODEM_VBUS_EN LTE Modem Disable(#2) signal/ GPIO87 1.8V J16.47 J14.47 GND Ground - J16.48 J14.48 GPIO_112 GPIO_112/LTE Modem Antenna control(no. 0) 1.8V J16.49 J14.49 BLSP_UART_RX(1) BLSP1 UART Receive/GPIO29 1.8V J16.50 J14.50 LTE_MODEM_POWER Modem Turn ON/OFF signal 1.8V J16.51 J14.51 BLSP_UART_TX(1) BLSP1 UART Transmit/GPIO28 1.8V J16.52 J14.52 GPIO_110 GPIO 110 1.8V J16.53 J14.
Hardware Reference Manual J16.68 J14.68 GND Ground - J16.69 J14.69 NC No Connection - J16.70 J14.70 GND Ground - J16.71 J14.71 NC No Connection - J16.72 J14.72 GND Ground - J16.73 J14.73 GND Ground - J16.74 J14.74 GND Ground - J16.75 J14.75 GND Ground - J16.76 J14.76 GND Ground - J16.77 J14.77 GND Ground - J16.78 J14.78 GND Ground - J16.79 J14.79 GND Ground - J16.80 J14.80 GND Ground - J16.81 J14.81 GND Ground - J16.82 J14.
Hardware Reference Manual J16.89 J14.89 VPH_PWR_CON 3.7V Supply from SBC (Battery/Input Power Supply) 3.5V-4.2V J16.90 J14.90 VPH_PWR_CON 3.7V Supply from SBC (Battery/Input Power Supply) 3.5V-4.2V J16.91 J14.91 VPH_PWR_CON 3.7V Supply from SBC (Battery/Input Power Supply) 3.5V-4.2V J16.92 J14.92 VPH_PWR_CON 3.7V Supply from SBC (Battery/Input Power Supply) 3.5V-4.2V J16.93 J14.93 VPH_PWR_CON 3.7V Supply from SBC (Battery/Input Power Supply) 3.5V-4.2V J16.94 J14.94 VPH_PWR_CON 3.
Hardware Reference Manual SBC Pin No. I/O Card Signal Name Pin No. Default Pin Function Voltage Level J18.1 J17.1 GND Ground - J18.2 J17.2 VREG_L13A PM660 Linear regulator L13 output 1.8V J18.3 J17.3 CDC_HS_DET_PMIC_CONN Headset detection - J18.4 J17.4 GND Ground - J18.5 J17.5 CDC_HPH_L_PMIC_CONN Headphone output, left channel - J18.6 J17.6 GND Ground - J18.7 J17.7 CDC_HPH_R_PMIC_CONN Headphone output, right channel - J18.8 J17.
Hardware Reference Manual J18.21 J17.21 LPI_AUD_CDC_RSTN Audio codec PDM receive 1 (DRE)/ LPI bit 24 1.8V J18.22 J17.22 LPI_AUD_CDC_INT1 Audio codec PDM receive 0 (DRE)/LPI bit 22 1.8V J18.23 J17.23 GND Ground - J18.24 J17.24 LPI_AUD_CDC_INT2 Audio codec PDM receive 1 /LPI bit 23 1.8V J18.25 J17.25 WCD_MCLK 19.2MHz clock for external audio codec. 1.8V J18.26 J17.26 GND Ground - J18.27 J17.27 GND Ground - J18.28 J17.
Hardware Reference Manual J18.40 J17.40 5V_LOAD 5V Supply from SBC 5V J18.41 J17.41 VCOIN Coin-cell battery/capacitor or backup battery charger supply and input 3V J18.42 J18.43 J17.42 J17.43 5V_LOAD VCOIN 5V Supply from SBC Coin-cell battery/capacitor or backup battery charger supply and input 5V 3V J18.44 J17.44 5V_LOAD 5V Supply from SBC 5V J18.45 J17.45 GND Ground - J18.46 J17.46 5V_LOAD 5V Supply from SBC 5V J18.47 J17.47 GND Ground - J18.48 J17.
Hardware Reference Manual J18.61 J17.61 GND Ground - J18.62 J17.62 GND Ground - J18.63 J17.63 GND Ground - J18.64 J17.64 GND Ground - J18.65 J17.65 LCD1_VDISP_M_OUT Display bias minus: negative LCD regulated output +5V J18.66 J17.66 GND Ground - J18.67 J17.67 LCD1_VDISP_P_OUT Display bias plus: boost SMPS regulated output -5V J18.68 J17.68 GND Ground - J18.69 J17.69 GND Ground - J18.70 J17.70 GND Ground - J18.71 J17.71 GND Ground - J18.72 J17.
Hardware Reference Manual J18.83 J17.83 GND Ground - J18.84 J17.84 BLSP1_SPI_CS_N_NFC BLSP1 - SPI chip select signal 1.8V J18.85 J17.85 3.7V_LOAD_REG 3.7V Supply from SBC (Battery/Input Power Supply) 3.5V-4.2V J18.86 J17.86 BLSP1_SPI_CLK_NFC BLSP1- SPI clock signal 1.8V J18.87 J17.87 3.7V_LOAD_REG 3.7V Supply from SBC (Battery/Input Power Supply) 3.5V-4.2V J18.88 J17.88 GND Ground - J18.89 J17.89 3.7V_LOAD_REG 3.7V Supply from SBC (Battery/Input Power Supply) 3.5V-4.
Hardware Reference Manual SBC Pin No. I/O Card Signal Name Pin No. Default Pin Function Voltage Level J19.1 J16.1 GND Ground - J19.2 J16.2 GND Ground - J19.3 J16.3 MIPI_CSI1_CLK_P MIPI CSI 1, differential clock – plus J19.4 J16.4 VREG_DVDD_1P2 1.2V from LDO for Digital section of camera sensor J19.5 J16.5 MIPI_CSI1_CLK_N MIPI CSI 1, differential clock – minus J19.6 J16.6 VREG_DVDD_1P2 1.2V from LDO for Digital section of camera sensor 1.2V J19.7 J16.7 GND Ground - J19.
Hardware Reference Manual J19.18 J16.18 VREG_BOB Regulated power supply from PMIC 3.3 V - 3.55V J19.19 J19.20 J16.19 J16.20 GND VREG_BOB Ground Regulated power supply from PMIC 3.3 V - 3.55V J19.21 J16.21 MIPI_CSI1_DATA3_N MIPI CSI 1, differential lane 3 – minus J19.22 J16.22 VREG_BOB Regulated BOB output of PMIC660L J19.23 J16.23 MIPI_CSI1_DATA3_P MIPI CSI 1, differential lane 3 – plus J19.24 J16.24 GND Ground - J19.25 J16.25 GND Ground - J19.26 J16.26 GND Ground - J19.
Hardware Reference Manual J19.38 J16.38 CAM2_STANDBY_N Power down signal for camera sensor 1.8V J19.39 J16.39 CCI_I2C_SCL1 Camera I2C Clock 1.8V J19.40 J16.40 CAM2_RST_N Reset signal for Camera 1.8V J19.41 J16.41 GND Ground - J19.42 J16.42 GND Ground - J19.43 J19.44 J16.43 J16.44 USB2_HS_DP GPIO103_ETHERNET_RESET USB high-speed 2 data – plus GPIO103/ Reset signal for Ethernet 1.8V J19.45 J16.45 USB2_HS_DM USB high-speed 2 data – minus J19.46 J16.
Hardware Reference Manual J19.58 J16.58 GND Ground - J19.59 J16.59 NC No Connection - J19.60 J16.60 NC No Connection - J19.61 J16.61 NC No Connection - J19.62 J16.62 NC No Connection - J19.63 J16.63 GND Ground - J19.64 J16.64 GND Ground - J19.65 J16.65 LCD1_BLSP_I2C_SCL_4 BLSP4- I2C Clock , Used for LCD 1.8V J19.66 J16.66 GND Ground - J19.67 J16.67 LCD1_BLSP_I2C_SDA_4 BLSP4- I2C DATA , Used for LCD 1.8V J19.68 J16.68 GND Ground - J19.69 J16.
Hardware Reference Manual J19.78 J16.78 GND Ground J19.79 J16.79 MIPI_DSI1_LANE2_N MIPI display serial interface 1 lane 2– negative J19.80 J16.80 GND Ground - J19.81 J16.81 GND Ground - J19.82 J16.82 GND Ground - J19.83 J16.83 MIPI_DSI1_LANE1_P MIPI display serial interface 1 lane 1– positive - J19.84 J16.84 VREG_L17A PM660 Linear regulator L17 output 1.8V J19.85 J16.85 MIPI_DSI1_LANE1_N MIPI display serial interface 1 lane 1– negative - J19.86 J16.
Hardware Reference Manual J19.97 J16.97 MIPI_DSI1_LANE0_N MIPI display serial interface 1 lane 0– negative - J19.98 J16.98 MIPI_DSI1_LANE3_N MIPI display serial interface 1 lane 3– negative J19.99 J16.99 GND Ground - J19.100 J16.100 GND Ground - Table 9 : Connector J19 pin details Version 1.
Hardware Reference Manual Major Interfaces of ERAGON660 SBC 6.2.1 Processor SDA660 - Features and interfaces The Qualcomm SDA660 includes a customized 64-bit ARM v8-compliant applications processor (Kryo 260) Quad high-performance Kryo cores targeting 2.2 GHz – Gold cluster with 1 MB L2 & Quad lowpower Kryo cores targeting 1.843 GHz – Silver cluster with 1 MB L2 It embraces Qualcomm Hexagon DSP with Hexagon Vector eXtensions (dual-HVX512) 787 MHz.
Hardware Reference Manual Wireless Connectivity With WCN3990, it supports 802.11 b/g/n/ac mode for 2.4GHz band and with MIMO configuration; it supports 802.11 a/n/ac mode for 5GHz band with MIMO configuration. WCN3990 also supports Bluetooth 5.0. With SDR660 receiver, SDA660 supports GPS location suite. Power Management 6.2.2 Combination of PM660 and PM660L interfaced through two 2-line SPMI. Dedicated clock and reset lines; plus other GPIOs as needed.
Hardware Reference Manual 6.2.6 System LEDs There are four notification LEDs provided on SBC module as described below, LED1 (Processor reset out LED): its glow indicates that processor came out of reset LED2 (Charging LED): Indicates battery charging status. D1: Indicates that 12V DC supply present. D14(RGB LED) : Multipurpose led Version 1.
Hardware Reference Manual Major Blocks of ERAGON660 6.3.1 Power Supply ERAGON660 kit can be powered through 12V@3A DC adapter or 3.8V Li battery. Switching between these supplies can be done through switch (SW2). Both power modes are described below, 6.3.1.1 DC mode In DC mode, 12VDC adapter need to plug into connector J9 of SBC with below settings, Pull switch (SW2) direction towards DC Jack (ON). From this 12V supply, remaining power supplies generated for other peripherals.
Hardware Reference Manual 6.3.2 Boot Configuration The ERAGON660 can be configured to function in different modes by selecting the switch SW3 provided on SBC.
Hardware Reference Manual Power on switch Volume Up Switch Fast Boot Switch/VOL_DOWN Switch Figure 9 – SBC General Purpose Keys (SW1,SW4 & SW5) 6.3.4 MIPI CSI Interface ERAGON660 kit supports three 4 Lane MIPI CSI ports; however only two can work concurrently. Below are its features, Three 4 Lane CSI Ports at 2.1 Gbps per lane data rate.
Hardware Reference Manual Pin description for CSI interface is as below, Camera board direct connect with SBC and connect the Camera board to IO card through FPC cable. Pin Number Net Name Pin Function J1.1 J1.2 J1.3 J1.4 J1.5 J1.6 J1.7 J1.8 J1.9 J1.10 J1.11 J1.12 J1.13 J1.14 J1.15 J1.16 J1.17 J1.18 J1.19 J1.20 J1.21 J1.22 J1.23 J1.24 J1.25 J1.26 J1.27 J1.28 J1.29 J1.
Hardware Reference Manual Pin Number Net Name Pin Function J2.1 J2.2 J2.3 J2.4 J2.5 J2.6 J2.7 J2.8 J2.9 J2.10 J2.11 J2.12 J2.13 J2.14 J2.15 J2.16 J2.17 J2.18 J2.19 J2.20 J2.21 J2.22 J2.23 J2.24 J2.25 J2.26 J2.27 J2.28 J2.29 J2.
Hardware Reference Manual Figure 11 – IO Card MIPI CSI1 connectors (J18) Pin Number J18.1 J18.2 J18.3 J18.4 J18.5 J18.6 J18.7 J18.8 J18.9 J18.10 J18.11 J18.12 J18.13 J18.14 J18.15 J18.16 J18.17 J18.18 J18.19 J18.20 J18.21 J18.22 J18.23 J18.24 J18.25 J18.26 J18.27 J18.28 J18.29 J18.30 J18.M1 J18.
Hardware Reference Manual 6.3.5 MIPI DSI Interface ERAGON660 kit supports Dual 4 Lane MIPI DSI ports, DSI0 and DSI1. SBC has DSI0 and IO card has DSI1. Display support up to 2560 × 1600, 10 bit at 60 Hz. On DSI0 Port connect LCD display with backlight bridge board and on DSI1, we can connect DSI to HDMI Bridge board to display the data on HDMI supported display screen. Connect these bridge boards to IO Card through FPC cable.
Hardware Reference Manual J14.27 J14.28 J14.29 J14.30 J14.31 J14.32 J14.33 J14.34 J14.35 J14.36 J14.37 J14.38 J14.39 J14.40 J14.41 J14.
Hardware Reference Manual J18.11 J18.12 J18.13 J18.14 J18.15 J18.16 J18.17 J18.18 J18.19 J18.20 J18.21 J18.22 J18.23 J18.24 J18.25 J18.26 J18.27 J18.28 J18.29 J18.30 J18.31 J18.32 J18.33 J18.34 J18.35 J18.36 J18.37 J18.38 J18.39 J18.40 J18.41 J18.
Hardware Reference Manual 6.3.6 USB Interface SDA660 supports one USB2.0 high speed and one USB3.1 (type C) Super speed Port with display port and USB2.0 out of them one USB2.0 comes to IO card through B2B connector. USB3.1 (Type C) use as ADB port and data port during OTG pen drive connection. Figure 14 – SBC USB 3.1 Connector (J13) Pinout Specification for the J13 are below, Pin Number Net Name J13.A1 J13.A2 J13.A3 J13.A4 J13.A5 J13.A6 J13.A7 J13.A8 J13.A9 J13.A10 J13.A11 J13.A12 J13.B1 J13.B2 J13.
Hardware Reference Manual J13.B12 11 12 13 14 15 16 17 18 GND GND_EARTH_USB GND_EARTH_USB GND_EARTH_USB GND_EARTH_USB GND_EARTH_USB GND_EARTH_USB GND_EARTH_USB GND_EARTH_USB Ground EARTH EARTH EARTH EARTH EARTH EARTH EARTH EARTH Table 16: SBC USB3.1 connector (J13) Pinout IO card has USB 2.0 hub and Hub has 4 downstream port as mentioned below. Port 1: Downstream Port 1 is directly connected to M.2 (4G LTE) connector.. Port 2: Downstream Port 2 is directly connected to Ethernet MAC.
Hardware Reference Manual USB1.S1 USB1.S2 USB1.S3 USB1.S4 USB_SHEILD_GND USB_SHEILD_GND USB_SHEILD_GND USB_SHEILD_GND Shield Ground Shield Ground Shield Ground Shield Ground Table 17: USB2.0 Host connector (J33) Pinout 6.3.7 Gigabit Ethernet Gigabit Ethernet connectivity on ERAGON660 IO card is provided in below flow, USB2.0 ->USB 2.0 HUB ->USB2.0 to Ethernet (MAC+PHY) to RJ45 connector Second downstream port of USB Hub is connected with the Ethernet MAC controller.
Hardware Reference Manual E1.12 E1.13 E1.14 E1.15 E1.16 E1.17 E1.18 E1.19 E1.20 VDD_2V5_ETHERNET GPIO4/LED4 VDD_2V5 GPIO0/LED0 VDD_2V5 ETH_SHEILD_GND ETH_SHEILD_GND ETH_SHEILD_GND ETH_SHEILD_GND 2.5V Supply GPIO -4 Pin 2.5V Supply(Yellow Led anode) GPIO -0 Pin 2.5V Supply(Orange Led anode) Shield Ground Shield Ground Shield Ground Shield Ground Table 18: IO Card Ethernet (E1) Pinout 6.3.
Hardware Reference Manual Figure 19 – IO Card Audio Headset Jack (J19) Below is the Pinout Specification of Headset Jack, Pin Number Net Name J19.1 J19.2 J19.3 J19.4 J19.5 J19.
Hardware Reference Manual Below is the Pinout Specification of J24, Pin Number J24.1 J24.2 J24.3 J24.4 J24.5 J24.6 J24.7 J24.8 J24.9 J24.10 J24.11 J24.12 J24.13 J24.14 J24.15 J24.16 J24.17 J24.18 J24.19 J24.
Hardware Reference Manual J22.15 J22.16 CDC_LINE_OUT1_P CDC_LINE_OUT2_M Line Output_2 Negative Line Output_1 Negative Table 21: IO Card Audio Header (J22) Pinout 6.3.9 Sensors ERAGON660 supports multiple sensors as below, Magnetometer, Accelerometer& Gyrometer, Pressure sensor and ALSP (Ambient Light and Proximity) sensor interfaced to SDA660 through LPI I2C and SPI. 6.3.10 Micro SD Card The ERAGON660 SBC has push-push type Micro SD card slot for external storage device (SD card).
Hardware Reference Manual Figure 22 – IO Card HDMI to CSI Audio Connector (J23) Pin specifications for J23 is mentioned below, Pin Number Net Name J23.1 J23.2 J23.3 J23.4 J23.5 J23.6 J23.7 J23.8 J23.9 J23.10 J23.11 J23.12 J23.13 J23.14 VCC_3V3_C_HDMI NC VCC_5V_C_HDMI NC HDMI_1.8V_DSI NC GND GND LNBBCLK3_HDMI HDMI_MI2S_3_SCK HDMI_HPD_N HDMI_MI2S_3_WS GPIO_110_HDMI_INT_GPIO HDMI_MI2S_3_D0 3.3V Supply Not Connected 5V Supply Not Connected 1.
Hardware Reference Manual Figure 23 – IO Card DSI to HDMI Audio Connector (J13) Pin specifications for J26 is mentioned below, Pin Number Net Name J13.1 J13.2 J13.3 J13.4 J13.5 GND GND GPIO_110_HDMI_INT_GPIO GPIO_29_HDMI_RST_N HDMI_MI2S_3_D0 Ground Ground HDMI Interrupt HDMI Reset HDMI I2S 3 Data 0 Signal J13.6 J13.7 J13.8 HDMI_MI2S_3_D1 HDMI_MI2S_3_D2 HDMI_MI2S_3_D3 HDMI I2S 3 Data 1 Signal HDMI I2S 3 Data 2 Signal HDMI I2S 3 Data 3 Signal J13.9 J13.10 J13.11 J13.12 J13.13 J13.14 J13.15 J13.
Hardware Reference Manual 6.3.14 GPS chip antenna Connect the GPS external antenna on connector (J10) Figure 25 – SBC Routing of UFL cable from SBC to IO Card (10) 6.3.15 M.2 (4G LTE) connector ERAGON660 kit supports 75-pin M.2 connector (J11) to plug 4G LTE modem on IO card. This 4G module is interfaced with first downstream port of USB Hub which it is connected to SDA660 processor, MI2S_2 interface, and few other GPIOs of SDA660 and Dual SIM card connectors (SIM1-J27, SIM2-J26). Figure 26 – IO Card M.
Hardware Reference Manual J11.9 J11.10 J11.11 J11.12 J11.13 J11.14 J11.15 J11.16 J11.17 J11.18 J11.19 J11.20 J11.21 J11.22 J11.23 J11.24 J11.25 J11.26 J11.27 J11.28 J11.29 J11.30 J11.31 J11.32 J11.33 J11.34 J11.35 J11.36 J11.37 J11.38 J11.39 J11.40 J11.41 J11.42 J11.43 J11.44 J11.45 J11.46 J11.47 J11.48 J11.49 J11.50 Version 1.
Hardware Reference Manual J11.51 J11.52 J11.53 J11.54 J11.55 J11.56 J11.57 J11.58 J11.59 J11.60 J11.61 J11.62 J11.63 J11.64 J11.65 J11.66 J11.67 J11.68 J11.69 J11.70 J11.71 J11.72 J11.73 J11.74 J11.75 GND NC NC NC NC NC GND NC GPIO_112_ANTCTL0 GPIO28_COEX3 GPIO_108/ANTCTL1 GPIO31_COEX2 ANTCTL3 GPIO30_COEX1 GPIO_89/ANTCTL4 SIM1_DETECT LTE_MODEM_RST NC TP19 3.7V_LOAD_REG GND 3.7V_LOAD_REG GND 3.
Hardware Reference Manual SIM Card_2 Connector Pin specifications are as follows, Pin Number J26.1 J26.2 J26.3 J26.4 J26.5 J26.6 J26.7 J26.8 to J26.17 Net Name Pin Function CONN_SIM2_PWR SIM2_RST SIM2_CLK GND NC SIM2_DATA SIM2_DETECT SHEILD_GND SIM2 Power Supply SIM2 Reset Signal SIM2 Clock Ground Not Connected SIM2 Data SIM2 Card Detect Shield Ground Table 26: IO Card SIM CARD_2 connector (J26) Pinout 6.3.
Hardware Reference Manual 6.3.17 FAN ERAGON660 IO card also have support to connect 5VDC Fan at connector J5. Connect +Ve terminal of Fan to J5.1 pin and GND to J5.2 pin. Figure 29 – IO Card FAN connector (J5) 6.3.18 Debug Port ERAGON660 support a debug Port to capture the system logs. SBC has on board UART to USB converter chip FT230XQ-R (U32). It converts BLSP2 UART signals from SDA660 to USB high-speed signals.
Hardware Reference Manual 6.3.19 Low Speed Expansion Connector Multiple BLSP signals brought from SDA660 to 20 pin male header (J6). User can use this signals to connect more peripherals. J6 Pin Specification are given in below table. Figure 31 – SBC Low Speed Expansion Header (J6) Pin Specification of J6 mentioned below, Pin Number Net Name J6.1 J6.2 J6.3 J6.4 J6.5 J6.6 J6.7 J6.8 J6.9 J6.10 J6.11 J6.12 J6.13 J6.14 J6.15 J6.16 J6.17 J6.18 J6.19 J6.
Hardware Reference Manual 6.3.20 Expansion Connector Different signals from SBC module are brought to IO card on 20 pin Female Headers (J4, J8). IO Card has I2C base GPIO expander chip and its signal came on connector J4. User can interface other I2S based peripherals to SBC module through connector J8. Figure 32 – IO Card Expansion Header (J4) Pinout specification of J4 is given below, Pin Number J4.1 J4.2 J4.3 J4.4 J4.5 J4.6 J4.7 J4.8 J4.9 J4.10 J4.11 J4.12 J4.13 J4.14 J4.15 J4.16 J4.17 J4.18 J4.19 J4.
Hardware Reference Manual Figure 33 – IO Card Expansion Header (J8) Pinout specification of J8 is given below, Pin Number J8.1 J8.2 J8.3 J8.4 J8.5 J8.6 J8.7 J8.8 J8.9 J8.10 J8.11 J8.12 J8.13 J8.14 J8.15 J8.16 J8.17 J8.18 J8.19 J8.20 Net Name VCC_1V8 VCC_3V3 GND GND GND GND I2C_SCL I2C_SDA LPI_I2C_3_SDA LPI_UART_2_RX LPI_I2C_3_SCL LPI_GPIO26_EXTR1 LPI_UART_2_TX HDMI_MI2S_3_SCK HDMI_MI2S_3_WS LPI_GPIO27_EXTR2 LPI_GPIO29_EXTR4 LPI_GPIO28_EXTR3 HDMI_MI2S_3_D1 HDMI_MI2S_3_D0 Pin Function 1.8V Supply 3.
Hardware Reference Manual 7 Electrical Specification Absolute Maximum Ratings Parameter Min Max Unit VBATT+ Main Battery Input Supply Voltage -0.5 6.0 V VDC 12VDC Input Supply Voltage -0.5 16 V VCOIN RTC Input Supply Voltage -0.5 3.5 V USB_VBUS USB VBUS Input Supply Voltage -0.3 16 V Table 32 : Absolute Maximum Ratings Operating Conditions s Parameter Min Typ Max Unit VBATT+ Main Battery Input Supply Voltage 2.8 3.8 4.75 V VDC 12VDC Input Supply Voltage 11.5 12 12.
Hardware Reference Manual 8 Mechanical Specification SBC Board Dimensions Figure 34 – SBC Module Dimension For more information about SBC mechanical dimension , kindly refer the Eragon660 SBC .dxf file. Version 1.
Hardware Reference Manual IO Card Dimension Figure 35 – IO Card Dimension Version 1.
Hardware Reference Manual 9 Special Care when using ERAGON660 Board Development Device Notice This device contains RF/digital hardware and software intended for engineering development, engineering evaluation, or demonstration purposes only and is intended for use in a controlled environment. This device is not being placed on the market, leased or sold for use in a residential environment or for use by the general public as an end user device.
Hardware Reference Manual 10 About eInfochips eInfochips is a partner of choice for Fortune 500 companies for product innovation and hi-tech engineering consulting. Since 1994, eInfochips has provided solutions to key verticals like Aerospace & Defense, Consumer Electronics, Energy & Utilities, Healthcare, Home, Office, and Industrial Automation, Media & Broadcast, Medical Devices, Retail & e-Commerce, Security & Surveillance, Semiconductor, Software/ISV and Storage & Compute.
Hardware Reference Manual The host product shall be properly labelled to identify the modules within the host product.
Hardware Reference Manual Regulation Information [FCC Information] This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
Hardware Reference Manual Regulation Information [IC Information] This device complies with Industry Canada license-exempt RSS standard(s). Operation in subject to The following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.
Hardware Reference Manual Information for OEM Integrator This device is intended only for OEM integrators under the following conditions: 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. [End product labelling] The label for end product must include “Contains FCC ID: 2ATUP-Q660500, Contains IC: 25301-Q660500”.