Operator's Manual

CIRCUIT DESCRIPTION
4-11
September 2001
Part No. 001-5100-001
4.4.6 UART
The UART performs parallel to serial and serial
to parallel conversion. The serial format used is a 9-bit
format with start and stop bits. The serial transmission
speed is 19200 bps. The UART appears as eight regis-
ters visible in the I/O space of the DSP starting at
every multiple of 0008h from 0000h to 07FFh. U11
performs the address decoding by selecting the UART
when both IS* and A15 are low. Crystal Y2 along with
the internal oscillator of the UART provides the clock
required to generate the correct bit rate on the serial
output of the UART.
When the UART receives a new serial word or is
ready to accept a new word to send from the DSP, it
generates an interrupt on INTRN. This pin is
connected to one of the hardware interrupt lines on the
DSP. The DSP responds by reading the status register
in the UART and by answering accordingly.
4.4.7 ADSIC
The ADSIC is a complex custom IC which
performs many analog-to-digital, digital-to-analog,
and purely digital functions as previously described.
The ADSIC has four internal registers accessible by
the DSP. They are selected through the use of address
lines A15, A14, A13, A2, A1, A0, IS* (IS* needs to be
inverted with U4 to be compatible with the logic level
required by the ADSIC), RD*, and WR*. Two of these
registers are read-only while the two others are write-
only. Therefore, they can be accessed as two locations
in the I/O spaces. Due to the decoding performed,
those locations appear at the following addresses:
Fxx0h, Fxx1h, Fxx8h, Fxx9h, Exx0h, Exx1h, Exx8h,
and Exx9h.
Crystal Y1 along with the internal oscillator in
the ADSIC provide a 20 MHz clock. This clock signal
is used internally by the ADSIC and is also multiplied
by two to provide a 40 MHz clock to the DSP. The
frequency of the clock can be electronically shifted a
small amount by controlling varicap D1 through the
OSCW pin (U3-97). This removes interference created
on some channels by the clock.
The ADSIC and DSP exchange the sampled
receive data and the sampled VCO modulation signal
through a serial port. This serial port consists of pins
SCKR*, RFS, RxD, TxD, SCKT, and TFS on the
ADSIC. U21 and U1 modify the relative phase of TxD
and TFS to be compatible with the timing required on
the serial port of the DSP.
SDO is the output of the internal speaker DAC.
MAI is the input of the internal microphone attenuator
and is followed by the microphone ADC.
The ADSIC is configured partially by the DSP
through its data and address bus (see preceding).
However, most of the configuring is provided through
an SPI compatible serial bus. This SPI serial bus
consists of pins SEL*, SPD, and SCLK. The other side
of this bus is connected to the controller on the
Keypad Board.
4.5 KEYPAD BOARD
4.5.1 INTRODUCTION
The Keypad Board contains a microcontroller,
LCD Display, Display Driver, Audio circuits, and
Power supply. The Keypad Board interfaces with the
Digital board via J4, with the Top Control rigid flex
circuit via J13, and with the side buttons, PTT switch,
and accessory connector through J5.
4.5.2 FUNCTIONAL DESCRIPTION
The microcontroller provides an interface
between the hardware and the DSP (on the Digital
Board). When the user presses or rotates a control such
as the channel selector switch, a side option or PTT
switch, or a keypad key, the microcontroller signals
the change to the DSP. Conversely, when the DSP
needs to change the display or an LED, it signals the
microcontroller which then performs the action. The
microcontroller also controls peripheral ICs such as
the synthesizer, reference oscillator, display, and
ADSIC.
The microcontroller uses a serial bus to commu-
nicate with the DSP and another RS232 bus to
communicate with the side port connector. The side
connector bus is used for external communication with
a computer running the programming or tuning soft-
ware. Finally, the microcontroller maintains certain
operating parameters in the associated EEPROM
which is controlled via a two-wire serial bus.
DIGITAL BOARD (CONT’D)

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