ȱ ȱ ȱ ȱ ȱȱ Ethernet 2 Interface R84 R222 C150 U29 C91 L4 C70 C71 C24 C66 C62 R268 L9 C106 TP45 ETHERNET 1 R270 TP61 TP46 TP43 TP42 X7 C61 R112 R113 R116 R119 R99 TP114 R103 TP113 R110 TP63 R111 TP60 TP117 TP118 TP64 R274 TP115 TP23 TP70 TP71 R85 R93 R30 R29 L8 + C113 + C109 R17 C11 C13 C10 R218 + L18 TP25 R46 R203 R204 TP29 R205 TP30 TP31 TP26 POS 2 S9 OPEN OPEN D
ȱ ȱ ȱ ȱ ȱȱ Ethernet 2, Connector J17 The table below shows the pinout of the Ethernet 2 expansion connector. ) * + ' , * - ) * + ' , * - $ % ȱ * + ' , 0 - . 2 3 ) * + ' , 0 - 2 5 $ % & % & ' , > # / $ # 3 ) # 5 . .
ȱ ȱ ȱ ȱ ȱȱ HDMI Interface HDMI Connector, J19 C176 C175 C174 C154 + R84 R222 C150 U29 L4 C70 C71 C24 C66 C62 R268 TP45 L9 C106 R270 TP61 TP46 TP43 TP42 TP114 R103 TP113 R110 TP63 R111 TP69 TP60 TP118 TP64 ETHERNET 1 C61 R112 R113 R116 R119 R99 TP117 TP66 R274 TP115 TP23 TP70 R282 R281 R284 R283 R93 R102 R30 L8 + C111 R29 + + C109 R17 C112 C11 C13 C10 R218 R207 + TP25 R4
\ ] ^ ^ _ ` a \ ] b ȱ c _ ] ȱ b d e f g h ȱ i b j l m b k ȱ _ k _ n c _ b _ ^ ` _ ȱȱ HDMI Connector, J19 The development board provides an HDMI connector, J19. The HDMI interface is connected to the Display 0 interface of the ConnectCore for i.MX53 CPU. The table below shows the pinout of the HDMI connector: + ' $ ( + & / + & 4 r p ȱ s ȱ u d t d ^ a _ b % : , * - # . - 7 . : , * - 7 2 : , * - 9 .
\ ] ^ ^ _ ` a \ ] b ȱ c _ ] ȱ b d e f g h ȱ i b j l m b k ȱ _ k c _ _ b _ ^ ` ȱȱ _ n I2C Interface 2 I C Header, P22 C176 C175 C174 C154 + Q2 o ȱ p q r p ȱ ȱ u d t d ^ a _ b ȱ u k v w ^ R84 R222 C150 U28 U29 L4 C70 C71 C24 C66 C62 R268 L9 C106 TP45 ETHERNET 1 R270 TP61 TP46 TP43 TP42 TP69 X7 R93 R30 C115 R29 L8 + + C113 C112 + R17 C109 C11 C13 C10 C65 C64 R218 R207 L18 + TP25 R46 R203 R204 TP29 TP26 R205 TP30
\ ] ^ ^ _ ` a \ ] b ȱ c _ ] ȱ b d e f g h ȱ i b j l m b k ȱ _ k _ n c _ b _ ^ ` _ ȱȱ I2C Header, P22 Pin header P22 provides access to the ConnectCore for i.MX53 I2C port 3 interface. The I2C port 3 is connected to the following headers/interfaces on the development board.
\ ] ^ ^ _ ` a \ ] b ȱ c _ ] ȱ b d e f g h ȱ i b j l m b k ȱ _ k c _ _ b _ ^ ` ȱȱ _ n JTAG Interface JTAG Connector, X13 C176 C175 C174 C154 + p q p ȱ s ȱ u d t d ^ a ] d ^ ȱ u k R84 R222 C150 v w ^ U28 U29 J20 C161 C155 C151 C164 L4 C70 C71 C24 C66 C62 R268 TP45 L9 C106 R270 TP61 TP46 TP43 TP42 TP69 ETHERNET 1 C61 R112 R113 R116 R119 R99 TP114 R103 TP113 R110 TP63 R111 TP60 TP118 TP64 TP117 TP66 R274 TP115 TP23 TP70
Å Æ Ç Ç È É Ê Å Æ Ë ȱ Ì È Æ ȱ Ë Í Î Ï Ð Ñ ȱ Ò Ë Ó Õ Ö Ë Ô ȱ È Ô È × Ì È Ë È Ç É È ȱȱ Standard JTAG ARM Connector, X13 The standard JTAG ARM connector is a 20-pin header and can be used to connect JTAG development tools.
Å Æ Ç Ç È É Ê Å Æ Ë ȱ Ì È Æ ȱ Ë Í Î Ï Ð Ñ ȱ Ò Ë Ó Õ Ö Ë Ô ȱ È Ô Ì È È Ë È Ç É ȱȱ È × LVDS LCD Interface LVDS LCD Connector, P4 C176 C175 C174 C154 Q2 C70 C71 C24 R268 C66 C62 ETHERNET 1 L9 C61 C106 R270 TP61 TP45 TP43 TP42 TP69 R93 R30 L8 + C111 R29 C13 C114 + R27 + C109 R17 C112 C11 C10 R218 TP25 R46 R203 R204 TP29 POS 2 R205 TP30 TP31 OPEN DESCRIPTION INT.
Å Æ Ç Ç È É Ê Å Æ Ë ȱ Ì È Æ ȱ Ë Í Î Ï Ð Ñ ȱ Ò Ë Ó Õ Ö Ë Ô ȱ È Ô +3.
Å Æ Ç Ç È É Ê Å Æ Ë ȱ Ì È Æ ȱ Ë Í Î Ï Ð Ñ ȱ Ò Ë Ó Õ Ö Ë Ô ȱ È Ô Ì È È Ë È Ç É ȱȱ È × MicroSD™ Card Interface C176 C175 C174 C154 + R84 R222 C150 U29 L4 C70 C71 C24 C66 C62 R268 X7 ETHERNET 1 L9 C106 R270 TP61 TP45 TP43 TP42 TP114 R103 TP113 R110 TP63 R111 TP69 TP60 TP118 TP64 TP117 R85 C61 R112 R113 R116 R119 R99 R274 TP115 TP23 TP70 TP71 R282 R281 R284 R283 TP66 TP46 TP74 TP72 TP73 TP75 TP76 C86 R20 R93 R30 C115 R29 L8 + L6
ȱ ! ȱ " # $ % & ȱ ' * ( + ȱ ) ) ! ȱȱ , MicroSD™ Connector, X14 The development board provides one MicroSD™ card connector, X14. This interface is connected to the enhanced Secured Digital Host controller 1 (eSDHC3) of the i.MX53 CPU. The MicroSD™ connector used on the development board does not provide a card detect pin (pin-9 and pin-10 are connected to chassis). Hot-plug insertion or removal is not possible with this connector.
ȱ ! ȱ " # $ % & ȱ ' * ( + ȱ ) ) ! ȱȱ , Module Connectors, J1 and J2 Module Connector, J2 + C176 C175 C174 C154 Q2 R84 R222 C150 C70 C71 C24 C66 C62 R268 L9 C61 TP45 C106 R270 TP61 TP46 TP43 TP42 TP114 R103 TP113 R110 TP63 R111 TP60 TP118 TP64 TP69 R93 R30 C115 R29 + C13 C10 C11 + TP25 R46 R203 R204 TP29 OPEN DESCRIPTION INT.
ȱ ! ȱ " # $ % & ȱ ' * ( + ȱ ) ) ! ȱȱ , Parallel LCD Interface Parallel LCD Connector, P1 C176 C175 C174 C154 + R84 R222 C150 U28 U29 C164 C91 L4 C70 C71 C24 C66 C62 R268 TP45 L9 C106 R270 TP61 TP46 TP43 TP42 TP114 R103 TP113 R110 TP63 R111 TP69 TP60 TP118 TP64 ETHERNET 1 C61 R112 R113 R116 R119 R99 TP117 TP66 R274 TP115 TP23 TP70 R282 R281 R284 R283 R93 R30 R29 + C113 + C109 R17 C112 C11 C13 + R
ȱ ! ȱ " # $ % 1 & ȱ ' * ( + ȱ ) ) ! , ȱȱ x GPIO +3.3VDC supply and a 9-30VDC supply The table below shows the pinout of the parallel LCD connector, P1: H I J K ȱ 3 2 " I L J M N V W V O X Y Z T [ \ P Q R S T U P V W V O ] Y Z O [ ^ P Q R S T U P V W V O _ Y Z \ [ ` P Q R S T U P V W V O a Y Z ^ [ P Q R S T U P V W V \ T Y Z ` [ X
u v w w x y z u v { ȱ | x v ȱ { H ȱ ȱ } } w z x { ȱ J K X O Q X ^ f b { L r U O U U R P R S t \ V Q l | x { x w y x ȱȱ O r U R R R T o Q J K I L J r M X T W X \ Q X ` R S Q O U g X X R S Q O U l X _ W ] T c ] \ d ] ` ^ \ s N g g ^ U X a P ] O f ] ^ ^ a c ^ T p ] X a c ^ T p a c ^ T p ] _ a c ^ T p _ T f ] ]
u v w w x y z u v { ȱ | x v ȱ { } ~ ȱ { { ȱ x x | x { x w y ȱȱ x Peripheral Application Header + C176 C175 C174 C154 R84 R222 C150 U29 L4 C70 C71 C24 C66 C62 R268 TP45 L9 C106 R270 TP61 TP46 TP43 TP42 TP114 R103 TP113 R110 TP63 R111 TP69 TP60 TP118 TP64 ETHERNET 1 C61 R112 R113 R116 R119 R99 TP117 TP66 R274 TP115 TP23 TP70 R282 R281 R284 R283 TP71 X7 R93 R30 R29 RESERVED CLOSE BOOT - SD CLOSE CLOSE CLOSE BOOT -
u v w w x y z u v { ȱ | x v ȱ { } ~ ȱ { { x ȱ x | x { x w y x ȱȱ Peripheral Application Header, P21 H I J K I L J M N H O d e ^ n Q l U P O n Q l U P ] n Q l U a n Q l U b P I J K I M N n Q l U P O X ] ` n Q l U P O _ O a X d P \ T _ n Q l U P \ O P \ \ O T n Q l U P \ ^ O \ n Q l U P \ ` O ` n Q l U P \ X O d e O ^ n Q l U P \ n Q l
u v w w x y z u v { ȱ | x v ȱ { } ~ ȱ { { x ȱ x | x { x w y x ȱȱ The BCLK signal corresponds to the ConnectCore for i.MX53 burst clock signal. This clock signal is not buffered, and its voltage level is +1.8V. This signal is connected to the peripheral connector through a 0R resistor. By default this resistor is not populated. The I2C interface corresponds to the ConnectCore for i.MX53 I2C port 3.
ȱ ȱ ¡ ¢ £ ¤ ȱ ¥ ¦ ¨ © § ȱ § ȱȱ ª Power-Over-Ethernet (PoE) - IEEE802.
ȱ ȱ ¡ ¢ £ ¤ ȱ ¥ ¦ ¨ © § ȱ § ª ȱȱ The PoE Module Plug in the PoE module at a right angle to the development board, as shown in the picture below. ´ The PoE module is part of the optional Digi 802.3af application kit (sold separately, Digi P/N DG-ACC-POE).
ȱ ȱ ¡ ¢ £ ¤ ȱ ¥ ¦ ¨ © § § ȱ ª ȱȱ PoE Connector (power out), P20 The table below provides the pinout of the PoE output connector: ¹ « ȱ ¬ ® ¬ ȱ ¯ ȱ ± ° º » ¼ º ½ » ¾ ¿ À Ñ À È Ò Ä Á Ó Ã È Ñ À È Ò Ä Á Ó Ã Ê Ô Õ Ö Ì Ô Õ Ö Í Á Ó Ã Ä Ô Õ Ö × Á Ó Ã Ä Ô Õ Ö § ȱ ± § ² ³ ¡ ȱȱȱ ® ¬ ¬
ȱ ȱ ¡ ¢ £ ¤ ȱ ¥ ¦ ¨ © § ȱ § ȱȱ ª PWM Interface PWM Header, P23 ® ¬ ȱ ± ° ² ³ R84 R222 C150 U29 J20 C161 C155 C159 C162 C70 C71 C24 C66 C62 R268 L9 C106 TP45 ETHERNET 1 R270 TP61 TP46 TP43 TP42 TP69 R99 R103 TP113 R110 TP63 R111 TP114 TP118 TP64 TP117 TP60 TP115 R274 TP66 TP65 TP23 TP70 R282 R281 R284 R283 TP71 TP72 X7 C61 R112 R113 R116 R119 L4 R88 R93 R3
ȱ ȱ ¡ ¢ £ ¤ ȱ ¥ ¦ ¨ © § ȱ § ª ȱȱ Power Header, P23 The development board provides access to the two PWM signals generated on the module’s DA9053 PMIC, through the PWM header P23. The PWM1 signal is also connected to the parallel LCD interface. The PWM2 signal is also connected to the LVDS LCD interface.
â ã ä ä å æ ç â ã è ȱ é å ã ȱ è ê ë ì í î ȱ ï è ð ò ó è ñ ȱ å ñ é å å è å ä æ ȱȱ å ô SATA Interface SATA Connector, P2 + C176 C175 C174 C154 ÷ ö ȱ ù ȱ û ê ú ê ç ä ã ê R84 R222 C150 ȱ û ü ý ä U29 J20 U28 C164 L4 C70 C71 C24 C66 C62 R268 TP45 L9 C106 R270 TP61 TP46 TP43 TP42 TP69 ETHERNET 1 C61 R112 R113 R116 R119 R99 TP114 R103 TP113 R110 TP63 R111 TP60 TP118 TP64 TP117 TP66 R274 TP115 TP23 TP70 TP71 R282 R281 R284 R283
â ã ä ä å æ ç â ã è ȱ é å ã ȱ è ê ë ì í î ȱ ï è ð ò ó è ñ ñ å ȱ å ô é å è å ä æ å ȱȱ SATA Connector, P2 The development board provides access to the SATA interface on the module using the SATA connector, P2.
â ã ä ä å æ ç â ã è ȱ é å ã ȱ è ê ë ì í î ȱ ï è ð ò ó è ñ å ñ ȱ é å å è å ä æ ȱȱ å ô SD Card Interface + C176 C175 C174 C154 R84 R222 C150 J20 U29 C151 C164 L4 C70 C71 C24 C66 C62 R268 L9 C106 TP45 ETHERNET 1 R270 TP61 TP46 TP43 TP42 TP69 X7 C61 R112 R113 R116 R119 R99 TP114 R103 TP113 R110 TP63 R111 TP60 TP118 TP64 TP117 TP66 R274 TP115 TP23 TP70 R282 R281 R284 R283 TP71 R93 R102 R30 + + C109 C13 C10 C11 + TP25 POS 2 R203
â ã ä ä å æ ç â ã è ȱ é å ã ȱ è ê ë ì í î ȱ ï è ð ò ó è ñ å ñ ȱ å ô é å è å ä æ å ȱȱ SD/MMC Connector, X18 The development board provides one SD/MMC card connector, X18. This interface is connected to the enhanced Secured Digital Host controller 2 (eSDHC2) of the ConnectCore for i.MX53 CPU.
â ã ä ä å æ ç â ã è ȱ é å ã ȱ è ê ë ì í î ȱ ï è ð ò ó è ñ ȱ å ñ é å å è å ä æ ȱȱ å ô SPI Interface SPI Header, P24 ö ȱ ù ȱ û ê ú ê ä å è ä ã ê R84 R222 C150 ü ý U29 J20 U28 C91 L4 C70 C71 C24 C66 C62 R268 L9 C106 TP45 TP46 R270 TP61 TP43 TP42 TP69 ETHERNET 1 C61 R112 R113 R116 R119 R99 TP114 R103 TP113 R110 TP63 R111 TP60 TP118 TP64 TP117 TP66 R274 TP115 TP23 TP70 R282 R281 R284 R283 X7 R93 ȱ û ñ R184 C161 C155 C159
' ( ) ) * + , ' ( - ȱ . * ( ȱ - / 0 1 2 3 ȱ 4 - 5 7 8 - 6 ȱ * 6 * 9 . * - * ) + * ȱȱ SPI Header, P24 The development board provides access to the SPI interface on the module using the SPI header, P24. This interface is connected to the ConnectCore for i.MX53 ECSPI1 port.
' ( ) ) * + , ' ( - ȱ . * ( ȱ - / 0 1 2 3 ȱ 4 - 5 7 8 - 6 ȱ * 6 .
' ( ) ) * + , ' ( - ȱ . * ( ȱ - / 0 1 2 3 ȱ 4 - 5 7 8 - 6 6 * ȱ * . * - * ) + ȱȱ * 9 UART 1 pins are allocated as shown: Y Z Z " # Y UART 2 (MEI), X30 UART 2 connector X30, is a DB-9 male connector. This asynchronous serial port is operating in DTE mode and requires a null-modem cable to connect to a computer serial port.
' ( ) ) * + , ' ( - ȱ . * ( ȱ - / 0 1 2 3 ȱ 4 - 5 7 8 - 6 6 * ȱ * . * - * ) 9 + * ȱȱ UART 3 (TTL Interface), X19 The UART 3 interface is a TTL interface connected to a 2x5 pin, 2.54mm pin header. The connector supports only TTL level signals. UART 3 pins are allocated as shown: a a Y Y Z Z a " a # ! UART 3 is connected to the X19 connector and XBee module socket.
' ( ) ) * + , ' ( - ȱ . * ( ȱ - / 0 1 2 3 ȱ 4 - 5 7 8 - 6 ȱ * 6 * .
' ( ) ) * + , ' ( - ȱ . * ( ȱ - / 0 1 2 3 ȱ 4 - 5 7 8 - 6 ȱ * 6 .
c d e e f g h c d i ȱ j f d ȱ i k l m n o ȱ p i q s t i r ȱ f r j f f i f e g ȱȱ f u User Interface C176 C175 C174 C154 + R84 R222 C150 U28 U29 C91 L4 C70 C71 C24 C66 C62 R268 L9 C106 TP45 ETHERNET 1 R270 TP61 TP43 TP42 TP69 X7 C61 R112 R113 R116 R119 R99 TP114 R103 TP113 R110 TP63 R111 TP60 TP118 TP64 TP117 TP23 TP70 TP71 TP115 R274 TP66 TP46 R93 R102 R30 C115 R29 + + R46 R203 R204 DESCRIPTION INT.
c d e e f g h c d i ȱ j f d ȱ i k l m n o ȱ p i q s t i r ȱ f r j f f i f e g ȱȱ f u WLAN Interface Primary Antenna Connectors, P12 & P14 C176 C175 C174 C154 + R84 R222 C150 L4 C70 C71 C24 C66 C62 R268 C86 R20 R85 X7 ETHERNET 1 L9 C61 C106 TP45 R105 R270 TP61 TP114 R103 TP113 R110 TP63 R111 TP60 TP118 TP64 TP43 TP42 R93 R30 C115 R29 L8 + + C113 + R17 C112 C11 C13 C10 R218 + TP25 POS 2 R46 R203 R204 TP29 TP26 TP27 DESCRIPTION BOOT
c d e e f g h c d i ȱ j f d ȱ i k l m n o ȱ p i q r s t i r f ȱ f j f i f u e g f ȱȱ Antenna Connectors (WLAN) The development board provides the following connectors for the WLAN interface: and P13: these two UFL connectors are used to connect the WLAN interface of the ConnectCore for i.MX53 to the development board. Two coaxial cables are used for this connection.
c d e e f g h c d i ȱ j f d ȱ i k l m n o ȱ p i q s t i r ȱ f r j f f i f e g ȱȱ f u Digi XBee Interface + C176 C175 C174 C154 R84 R222 C150 U29 J20 U28 C151 C164 L4 C70 C71 C24 C66 C62 R268 L9 C106 TP45 ETHERNET 1 R270 TP61 TP46 TP43 TP42 TP114 R103 TP113 R110 TP63 R111 TP60 TP118 TP64 TP117 X7 C61 R112 R113 R116 R119 R99 R274 TP115 TP23 TP70 R282 R281 R284 R283 TP66 TP69 R93 R30 R29 C13 C10 + TP25 POS 2 R203 R204 R46 R205 T
¢ £ ¤ ¤ ¥ ¦ § ¢ £ ¨ ȱ © ¥ £ ȱ ¨ ª « ¬ ® ȱ ¯ ¨ ° ² ³ ¨ ± ȱ ¥ ± © ¥ ¥ ¨ ¥ ¤ ¦ ȱȱ ¥ ´ Digi XBee Module Connectors, X28 and X29 The development board provides two 10-pin, 2.0mm connectors, X28 and X29, supporting a Digi XBee module. The XBee serial port is shared with UART port 3 on the development board. The table below shows the pinout of the XBee module connectors.
Module Specifications è é é ê ë ì í î è T his appendix provides ConnectCore for i.MX53 module specifications.
¢ £ ¤ ¤ ¥ ¦ § ¢ £ ¨ ȱ © ¥ £ ȱ ¨ ª « ¬ ® ȱ ¯ ¨ ° ± ² ³ ¨ ± ¥ ȱ ¥ © ¥ ¨ ¥ ¤ ¦ ¥ ´ ȱȱ Mechanical Specifications Length: 82 mm (3.228 inches) Width: 50 mm (1.968 inches) Height : – PCB: 1.60 mm (0.063 inches) – Top side part: 3.60 mm (0.142 inches) – Bottom side part: 2.20 mm (0.
¢ £ ¤ ¤ ¥ ¦ § ¢ £ ¨ ȱ © ¥ £ ȱ ¨ ª « ¬ ® ȱ ¯ ¨ ° ± ² ³ ¨ ± ¥ ȱ ¥ © ¥ ¨ ¥ ¤ ¦ ȱȱ ¥ ´ Network Interface Antenna specifications: 802.11 a/b/g antenna At t r i but e s ú û û ü ý $ * . 2 % + - & 7 4 ' $ / 3 8 ( ; .
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N L C L @ ȱ @ D @ C @ ? A ȱȱ @ O Antenna Specifications: 802.11b/g antenna At t r i but e s _ ` 4 3 ` a - .
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N L C @ L ȱ @ D @ O C @ ? A @ ȱȱ Ethernet 1 Standard: IEEE 802.3/802.3u Physical layer: 10/100Base Data rate: 10/100 Mbps Mode: Full or half duplex Ethernet 2 Standard: IEEE 802.3/802.3u Physical layer: 10/100Base Data rate: 10/100 Mbps Mode: Full or half duplex WLAN Stan dar d IEEE 802.11a/b/g/e/i/h/j standards Single-stream draft IEEE 802.
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N L C @ L ȱ @ D @ C @ ? A O @ ȱȱ W i r e le s s Me d i u m 802.11b/g: Direct Sequence-Spread Spectrum ( DSSS ) and Orthogonal Frequency Divisional Multiplexing ( OFDM ) 802.11a/n: OFDM DFS Cli ent This module supports the DFS Client only between 5.25 - 5.35GHz and 5.50 - 5.70GHz bands. It does not support being DFS Master, or can it be connected to an Ad hoc network in these bands.
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N C L ȱ @ L D @ @ C @ ? O A @ ȱȱ Ava i l a bl e T r a n s m i t Po we r Se t t i n g s ( Ty pic a l + - ( 2 dBm )@ 25 ° C) ( Maximum power settings will vary according to individual country regulations ) IEEE 802.11b ( ~12 dBm ETSI ) ( ~15.7 dBm FCC 15.247 ) @ 1, 2, 5.5 and 11 Mbps IEEE 802.11g ( ~ 10 dBm ETSI ) ( ~18.6 dBm FCC 15.247 ) @ 6, 12, 18, 24, 36 and 54Mbps IEEE 802.11n 2.
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N C L ȱ @ L D @ @ C @ ? A ȱȱ @ O Electrical Characteristics Supply Voltages f a 2 2 3 e ` ) ' ) & a + e + & ) + 9 3 / < 2 i c - ) - 2 - 2 2 g ~ b , / 2 , ) ; 2 | i h # - - - b ` Supply Current The
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G ` .
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N C L @ L ȱ D @ @ C @ ? A ȱȱ @ O C u r r e n t m e a s u r e m e n t i n Ma x i m u m c o n fi g u r a t i o n f g e & , & & a 3 g e f ; 8 .
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N C L @ L ȱ @ D @ C @ ? A ȱȱ @ O I/O DC Parameters This section includes the DC parameters of the following I/O types: General Low Purpose I/O (GPIO) Voltage I/O (LVIO) Ultra High Voltage I/O (UHVIO) LVDS WLAN VDDCORE, Ethernet Analog ADC PMIC_IO1, PMIC_IO2, PMIC_ADC, PMIC_TOUCH (ETH) RGB (AN_RGB) subsystem (ADIN) Digital and analog USB (DIG_USB, AN_USB) The I/O type associa
= > ? ? @ A B = > C ȱ D @ > ȱ C f E F ) G H a + I e ` ȱ J e 8 C K M N C L ȱ @ L D @ @ C @ a ? A ȱȱ @ O 8 8 i - ) + 2 3 + & ) + 2 ) + 2 # ) + 2 ! ! ) + 2 ! ! & 5 + ( 3 c g ~ b | i h b ` .
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N C L ȱ @ L D @ @ C @ ? A ȱȱ @ O U l t r a H i g h V o l t a g e I / O ( U H V I Ox x ) D C E l e c t r i c a l Pa r am e t e r s Z [ \ f ] a .
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N C L ȱ @ L @ D @ C @ ? A ȱȱ @ O L V D S I / O D C E l e c t r i c a l Pa r a m e t e r s The LVDS interface complies with TIA/EIA 644-A standard.
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N C L ȱ @ L D @ @ C @ ? A ȱȱ @ O P MIC _IO 2 DC E l e c t r i ca l Pa r a m e t e r s f a .
= > ? ? @ A B = > C ȱ D @ > ȱ C E F G H I ȱ J C K M N C L @ L ȱ @ D @ C @ ? A ȱȱ @ O A n a l og R G B ( R G B ) D C E l e c t r i c a l P a r a m e t e r s f a . + + e & ` - e 3 a & ' i - c 7 g ~ b 7 | 1 i h # 1 b ` - D i g i t a l U SB ( D I G _U SB ) D C E l e c t r i c a l Pa r a m e t e r s f a .
Module Dimensions ¢ £ £ ¤ ¥ ¦ § ¨ © T his appendix shows the dimensions of the ConnectCore for i.MX53 module, dimensions are in millimeters.
ª « ¬ ¬ ® ¯ ª « ° ȱ ± « ȱ ° ² ³ ´ µ ¶ ȱ · ° ¸ ¹ º » ° ¹ ȱ ¼ ± ° ¬ ® ȱȱ Top View ½ ȱ ¾ ¿ À ¾ ȱ Á ȱ Ã ² Â ² ¬ ¯ ° ¬ ¯ ¹ « ² ¬ ȱ Ã ¹ Ä Å ¬ ® ³ ȱȱȱ À ¶ Æ
ª « ¬ ¬ ® ¯ ª « ° ȱ ± « ȱ ° ² ³ ´ µ ¶ ȱ · ° ¸ ¹ º » ° ¹ ȱ ¼ ± ° ¬ ® ȱȱ Bottom View ½ ȱ ¾ ¿ À ¾ ȱ Á ȱ Ã ² Â ² ¬ ¯ ° ¬ ¯ ¹ « ² ¬ ȱ Ã ¹ Ä Å ¬ ® ³ ȱȱȱ À ¶ Ç
ª « ¬ ¬ ® ¯ ª « ° ȱ ± « ȱ ° ² ³ ´ µ ¶ ȱ · ° ¸ º » ° ¹ ȱ ¹ ± ° ¬ ® ȱȱ ¼ Side View 3.75 1.30 max 3.6mm max 2.2mm 6.00 Connectors The ConnectCore for i.MX53 module uses two Berg/FCI connectors. The following table shows the reference number of the connectors used in the module and the reference number of the connectors used in the development board. The mated height of the module and the development board is 5mm.
Certifications ø ù ù ú û ü ý þ ÿ T he ConnectCore for i.MX53 product complies with the following standards. FCC Part 15 Class B Radio Equipment - FCC Warning Statement This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
ª « ¬ ¬ ® ¯ ª « ° ȱ ± « ȱ ° ² ³ ´ µ ¶ ȱ · ° ¸ ¹ º » ° ¹ ȱ ¼ ± ° ¬ ® ȱ Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Change Log ø ù ù ú û ü ý þ ü T he following changes were made to this document in the revisions listed below. Revision A Initial release. Added Appendix C - Certifications. Revision B Renamed the Change Log appendix (previously Appendix C) to Appendix D - Change Log. Added pinout definitions to the Module Pinout section of Chapter 1. Added the Known Issue with the RTC sub-section to the RTC section of Chapter 1.
