User's Manual

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D D

C C

B B

RSSI_DETECT

RF_TX_0

RF_TX_1

RF_TX_2

RF_TX_3

RFSPI_CS

RFSPI_CLK

RFSPI_DOUT

LD_0

CLK40M

TX_I_N2

TX_Q_P2

TX_Q_N2

TX_I_P2

TX_I_N3

TX_I_P3

TX_Q_N3

TX_Q_P3

RX_I_P

RX_I_N

RX_Q_P

RX_Q_N

TX_I_N0

TX_I_P0

TX_Q_N0

TX_Q_P0

TX_I_N1

TX_I_P1

TX_Q_N1

TX_Q_P1

PA_ENABLE PA_ENABLE

WHDI_D[35..0]

WHDI_I2S_D[3..0]

WHDI_REF_CLK_OUT

WHDI_RESET_OUT

WHDI_INT_IN

WHDI_PWM0

WHDI_INT_OUT

WHDI_M_SCL

WHDI_M_SDA

WHDI_RESET_IN

SPI_SCK

SPI_SSEL_I2C_SCL

SPI_MOSI

SPI_MISO_I2C_SDA

WHDI_DCLK

WHDI_H_SYNC

WHDI_V_SYNC

WHDI_DE

WHDI_SPDIF

WHDI_SCLK

WHDI_MCLK

WHDI_LRCLK

HDMI_RESET

DDC_SW0

uC_HPD0

HDMI_INT

I2C_SDA0

I2C_SCL0

HDMI_REMOTE_CEC1

WHDI_TBD2

WHDI_TBD1

POWER_EN

DDC_SCL0

DDC_SDA0

POWER_EN_33

Title

Size Document Number Rev

Date: Sheet of

Dfine

2431.01-JD7.820.271 1.0

MAIN

Dfine

Building A2,Tianfu Software Park,Hi-tech Zone

South Extension of Tianfu Wide Road

Chengdu

China

111Tuesday, July 27, 2010

Title

Size Document Number Rev

Date: Sheet

Dfine

2431.01-JD7.820.271 1.0

MAIN

Dfine

Building A2,Tianfu Software Park,Hi-tech Zone

South Extension of Tianfu Wide Road

Chengdu

China

111Tuesday, July 27, 2010

Title

Size Document Number Rev

Date: Sheet

Dfine

2431.01-JD7.820.271 1.0

MAIN

Dfine

Building A2,Tianfu Software Park,Hi-tech Zone

South Extension of Tianfu Wide Road

Chengdu

China

111Tuesday, July 27, 2010

05 - TXIC

RF_TX_1

RF_TX_2

RF_TX_3

RF_TX_0

CLK40M

RSSI_DETECT

LD_0

RFSPI_CS

RFSPI_DOUT

RFSPI_CLK

TX_I_P0

TX_I_N0

TX_Q_N2

TX_Q_N3

TX_I_P1

TX_I_P2

TX_I_P3

TX_I_N1

TX_I_N2

TX_I_N3

TX_Q_P0

TX_Q_P1

TX_Q_P2

TX_Q_N0

TX_Q_P3

TX_Q_N1

RX_I_N

RX_I_P

RX_Q_N

RX_Q_P

04 - TX_PA

RF_TX_0

RF_TX_1

RF_TX_2

RF_TX_3

PA_ENABLE

02 - SHACHAF_TX

CLK40M

RX_I_N

RX_I_P

RX_Q_N

RX_Q_P

TX_Q_N2

TX_Q_N3

TX_I_P0

TX_I_P1

TX_I_P2

TX_I_N0

TX_I_P3

TX_I_N1

TX_I_N2

TX_I_N3

TX_Q_P0

TX_Q_P1

TX_Q_P2

TX_Q_N0

TX_Q_P3

TX_Q_N1

PA_ENABLE

RSSI_DETECT

RFSPI_CLK

RFSPI_CS

RFSPI_DOUT

LD_0

WHDI_DCLK

WHDI_H_SYNC

WHDI_REF_CLK_OUT

WHDI_LRCLK

WHDI_SCLK

WHDI_I2S_D[3..0]

SPI_MISO_I2C_SDA

WHDI_V_SYNC

WHDI_INT_IN

WHDI_D[35..0]

WHDI_MCLK

WHDI_SPDIF

WHDI_INT_OUT

WHDI_DE

WHDI_RESET_OUT

SPI_MOSI

SPI_SCK

WHDI_PWM0

SPI_SSEL_I2C_SCL

WHDI_M_SDA

WHDI_RESET_IN

WHDI_M_SCL

WHDI_TBD2

WHDI_TBD1

03 - Power

POWER_EN

POWER_EN_33

06 - HDMI

DDC_SW0

I2C_SDA0

I2C_SCL0

WHDI_TBD2

WHDI_TBD1

uC_HPD0

HDMI_INT

HDMI_RESET

WHDI_SPDIF

WHDI_SCLK

WHDI_LRCLK

WHDI_H_SYNC

WHDI_DCLK

WHDI_V_SYNC

WHDI_DE

WHDI_D[35..0]

WHDI_MCLK

WHDI_I2S_D[3..0]

WHDI_M_SCL

WHDI_M_SDA

WHDI_RESET_OUT

WHDI_INT_IN

HDMI_REMOTE_CEC1

WHDI_PWM0

DDC_SCL0

DDC_SDA0

07 - uC

DDC_SW0

WHDI_REF_CLK_OUT

SPI_MOSI

SPI_MISO_I2C_SDA

SPI_SSEL_I2C_SCL

SPI_SCK

I2C_SDA0

I2C_SCL0

HDMI_INT

HDMI_REMOTE_CEC1

uC_HPD0

POWER_EN

DDC_SCL0

POWER_EN_33

WHDI_INT_OUT

DDC_SDA0

WHDI_RESET_IN

HDMI_RESET

Summary of content (11 pages)

PAGE 1
5 4 3 06 - HDMI 2 02 - SHACHAF_TX 04 - TX_PA PA_ENABLE WHDI_DCLK WHDI_H_SYNC WHDI_V_SYNC WHDI_DE D WHDI_D[35..0] WHDI_SPDIF WHDI_SCLK WHDI_MCLK WHDI_LRCLK WHDI_I2S_D[3..0] WHDI_DCLK WHDI_H_SYNC WHDI_V_SYNC WHDI_DE WHDI_D[35..0] WHDI_SPDIF WHDI_SCLK WHDI_MCLK WHDI_LRCLK WHDI_I2S_D[3..0] WHDI_RESET_OUT WHDI_INT_IN WHDI_PWM0 WHDI_TBD1 WHDI_TBD2 WHDI_M_SCL WHDI_M_SDA WHDI_RESET_OUT WHDI_INT_IN WHDI_PWM0 WHDI_TBD1 WHDI_TBD2 POWER_EN POWER_EN_33 B WHDI_D[35..
PAGE 2
1 2 1 2 D 1 1 C? NC 10% 16 VDC C0402 2 5% R0402 1 C? NC 10% 6.
PAGE 3
U9B AMN2120_A4 BGA169_P08MM 5 4 3 N2 TP? (smp_on_rst[0]) FLASH_SPI_CLK 4 (smp_on_rst[1]) FLASH_SPI_MOSI 4 (smp_on_rst[2]) FLASH_SPI_SS 4 (smp_on_rst[3]) PA_ENABLE 2,7 (smp_on_rst[4]) RFSPI_CLK 2,8 (smp_on_rst[5]) RFSPI_CS 2,8 (smp_on_rst[6]) RFSPI_DOUT 2,8 (smp_on_rst[7]) UL_RX_ANT_SEL_N 2 (smp_on_rst[8]) UL_RX_ANT_SEL_P 2 (smp_on_rst[9]) WHDI_REF_CLK_OUT 4,11 TP_SMD_ROUND Debug test points D C WHDI_DCLK 1 Sample on reset configuration W_12_24_40 DCLK_I 2 VD_0 VD_1 VD_2 VD_3 VD_4 VD_5 VD_6 V
PAGE 4
3 2 U9C AMN2120_A4 BGA169_P08MM RESET_B_IN 2 R45 0.0ohm 5% R0402 3,11 WHDI_REF_CLK_OUT TRST TDI TMS TCK 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 1 2 RST R0402 R0402 1 1 2 0.0ohm R? 2 0.0ohm 5%R? 5% 1% R0402 1% R0402 1 1 2 NC R? 2 NC R? UART_TXD UART_RXD EJTAG_DINT TDO 1 1 1% R0402 1% R0402 9 WHDI_TBD2 9 WHDI_TBD1 2 NC R? 2 NC R? WHDI_REF_CLK_OUT B11 connector R440 10 WHDI_INT_IN I2CM_CLK I2CM_DATA WHDI_RESET_OUT WHDI_INT_OUT WHDI_PWM0 20.
PAGE 5
4 1.0V 3 2 1 3.
PAGE 6
1 R86 NC R0402 R2 2 B R4114 120Kohm 1% R0402 2 Vout=Vref*(1+R1/R2) Vout=1.1V C63 22nF 10% 16V C0402 C61 10uF C1206 10% 6.3V 2 1 220ohm 1% R0402 1 2 TP8 TP_TH TP_35_63 1 2 1 2 1 a 2 1 R? 300ohm R0402 1% D1 C190KGKT 0603_LED R463 300ohm 1% R0402 D2 C190KGKT 0603_LED ICT W_12_40_60 TP_SMD_ROUND W_12_40_60 TP_SMD_ROUND W_12_40_60 TP_SMD_ROUND TP9 TP_TH TP_35_63 TP10 TP_TH TP_35_63 TP11 TP_TH TP_35_63 V_IN 2 2 R93 3.9Kohm R0402 1% Vout=Vref*(1+R1/R2) Vout=1.
PAGE 7
5 4 3 2 1 2 3 1 2 ANT? TYPE_A_ANTENNA PIFA_001 2 2 1 FEED GND 1 L1 NC C0402 D 2 1 L3 NC C0402 1 C5 1.8pF +/-0.1pF 50V C0402 1 GND#6 GND#5 GND#4 2 RFTX0 6 3 2 OUT 5 IN GND OUT 1 GND#3 6 2 GND#3NC#6 GND#7 IN 7 2 17 6.8pF C909 +/-0.25pF NC 50V C0402 C0402 C907 0.5pF +/-0.
PAGE 8
1 2 TX3RF_N 37 TX3RF_P 2 34 VCC_LO 33 LD_0 LD_0 32 0.5% 2 TP? 2 2 W_12_24_40CS R? 49.9ohm R0402 0.5% TX_Q_N1 TX_Q_N1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 1 R? 49.9ohm 1 C? 4.7nF 15% 50V C0402 4 2 49.9ohm 0.5% R0402 1 BALN TX0RF_N 3 TX0RF_P 1 2 Y? 40MHZ TXC_3_2X2_5 2 1 4 2 BALP NC GND#5 UNBAL GND C? NC C0402 C? NC ?.25pF 50V C0402 J? UFL-R-SMT UFL-R-SMT Note: For test only 1 6 1 1 1 C? 1.8pF +/-0.
PAGE 9
4 3 2 VCC5_CBL_0 TP_SMD_ROUND W_12_24_40 RV441 AVR-M1608C120MT2AB AVRM1608 2 1 D 10 10 R0X2+ R0X2- 10 10 R0X1+ R0X1- 10 10 R0X0+ R0X0- 10 10 R0XC+ R0XC- 6 7 8 9 10 R0X2+ R0X2R0X1+ R0X1- Line4 NC3 GND Line2 NC1 R0XC+ R0XC- FOR DEBUG 3.3V_HDMI R427 R0402 300ohm 1% 1 2 R2781 R2791 NC NC 11 DDC_SCL0 11 DDC_SDA0 D447 C190KGKT a 0603_LED 4 L4433 R0X1+ R0X1- 2 5% R0402 2 5% R0402 DSCL0 DSDA0 c HPD_CONN0 C 1 3 R473 3.
PAGE 10
HDMI_AVCC_1V8 3 102 101 100 2 3.9Kohm 2 3.9Kohm 92 143 131 119 107 91 80 25 24 12 1 XTALVCC XTALIN XTALOUT 2 2 HDMI_DVCC_1V8 C494 100nF 10% 10V C0402 1 C495 10uF 10% 6.
PAGE 11
3 2 I2C / SPI SELECTION GND APP_TRST APP_TDI A 1 5 R214 3.9Kohm GND 1% R0402 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 2 1 VBUS DM DP 6 5 4 IO_1 VBUS IO_2 1 2 R681 NC R0402 50V 15% 4.7nF C677 C0402 3.