DFZM-E72xx Data sheet DFZM-E72xx An IEEE 802.15.
DFZM-E72xx Contents 1. 2. 3. 4. 5. 6. 7. 8. Features ............................................................................................................................................... 4 ZigBee Model No. Definition ............................................................................................................. 6 Architecture......................................................................................................................................... 7 3-1.
DFZM-E72xx Revision History Version Date 0.1 2013/9/5 0.2 1. Change the DFZM-E722x module size, and modify all 2013/9/16 mechine drawing 2. Add package information 0.3 1. Add RF exposure warning statement including FCC 2014/2/15 statement. 2. Modify 5.6 Radio Parameter for DFZM-E721x .
DFZM-E72xx DFZM-E72xx IEEE802.15.4 System-On-Chip ZigBee Module describes the DFZM-E72xx ZigBee module hardware specification. The EM357 based modules provide cost effective, low power, and flexible platform to add ZigBee connectivity for embedded devices for a variety of applications, such as wireless sensors and energy monitoring.
DFZM-E72xx ► Interfaces: • Internal antenna or external antenna options. • Flexible ADC, UART/SPI/TWI serial communications, and general purpose timers. • Up to 22 configurable general purpose I/Os. • Single voltage operation: 2.1~3.6V ► Embedded RTC (Real Time Clock) can run directly from battery.
DFZM-E72xx 2. ZigBee Model No. Definition D F Z M - E 7 2 2 0 Data Sheet - DT 0 R Sheet 6 of 40 Free-lead E=Pb free R=RoHS N=NG L=Process with Lead Serial no. 0~9 then A~Z Customer code DT= Delta Define Antenna Version 0= External Antenna 1= Onboard Chip Antenna Power Version 1= High Power 2= Low Power Frequency 2= 2.
DFZM-E72xx 3. Architecture 3-1.
DFZM-E72xx 3-2.Block Diagram Description 3-2-1.Overview DFZM-E72xx module is a highly integrated ZigBee system-on-chip (SOC) that contains the following: • The module includes Silicon Labs EM357 SoC, which contains CPU- and memory-related, peripherals-related, clocks and power management-related in a single package. • The module features an IEEE802.15.4-compliant radio transceiver with onboard 24 MHz crystal circuitries, RF, and certified antenna or external antenna options.
DFZM-E72xx developer to assist in tracking down and fixing issues. Figure 3.3 shows the EM357 ARM® Cortex-M3 memory map.
DFZM-E72xx 3-2-3.Clocks and Power Management The DFZM-E72xx integrates four oscillators: 12 MHz RC oscillator 24 MHz crystal oscillator 10 kHz RC oscillator Figure 3-4 shows a block diagram of the clocks in the DFZM-E72xx.
DFZM-E72xx The DFZM-E72xx’s power management system is designed to achieve the lowest deep sleep current consumption possible while still providing flexible wakeup sources, timer activity, and debugger operation. The DFZM-E72xx has four main sleep modes: Idle Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All power domains remain fully powered and nothing is reset. Deep Sleep 1: The primary deep sleep state.
DFZM-E72xx 3-2-4.Peripherals The DFZM-E72xx has 22 multipurpose GPIO pins, which may be individually configured as: General purpose output General purpose open-drain output Alternate output controlled by a peripheral device Alternate open-drain output controlled by a peripheral device Analog General purpose input General purpose input with pull-up or pull-down resistor The GPIO signal assignments are shown in Table 3-1.
DFZM-E72xx PC1 ADC3 PC2 TRACEDATA0, SWO Standard 6 JTDO , SWO Standard PC3 JTDI PC4 SWDIO7 PC5 TX_ACTIVE 5 Standard SWDIO7, JTMS7 Standard Standard Notes: 1.Default signal assignment (not remapped). 2. Overrides during reset as an input with pull up. 3. Overrides after reset as an open-drain output. 4. Alternate signal assignment (remapped). 5. Overrides in JTAG mode as a input with pull up. 6. Overrides in JTAG mode as a push-pull output. 7.
DFZM-E72xx PB1 PB2 PB4 SC1SCLK Alternate SC1MOSI Alternate SPI-Master PB3 (not used) SC1MISO Input Output (push-pull) Output (push-pull) SC1MISO Alternate SPI-Slave TWI-Master SC1MOSI Input SC1SDA Alternate SC1SCL Alternate Output (open-drain) Output (open-drain) TXD Alternate Output UART SC1SCLK Input SC1nSSEL Input (not used) (not used) Output (push-pull) RXD Input nCTS Input1 (push-pull) nRTS Alternate Output (push-pull)* *Note: used if RTS/CTS hardware flow control is enabled.
DFZM-E72xx 4. Pin-out and Signal Description 4-1.
DFZM-E72xx 4-2.
DFZM-E72xx Either disable timer output in TIM2_CCER,or disable remap with TIM2_OR[7] Enable with SC1_UARTCFG[5], Select UART with SC1_MODE Select alternate output function with GPIO_PBCFGH[3:0] SPI slave select of Serial Controller 1 SC1nSSEL I Enable slave with SC1_SPICFG[4], Select SPI with SC1_MODE PA0 I/O Digital I/O Timer 2 channel 1 output, Disable remap with TIM2_OR[4] TIM2C1 O Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[3:0] TIM2C1 I 7 Timer 2 channe
DFZM-E72xx Disable remap with TIM2_OR[7], Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[11:8] TIM2C4 I Timer 2 channel 4 input, Disable remap with TIM2_OR[7] TWI clock of Serial Controller 2, Either disable timer output in TIM2_CCER, SC2SCL I/O or enable remap with TIM2_OR[7], Select TWI with SC2_MODE Select alternate open-drain output function with GPIO_PACFGL[11:8] SPI master clock of Serial Controller 2 Either disable timer output in TIM2_CCER, or enable remap wi
DFZM-E72xx PA5 I/O ADC5 Analog Digital I/O ADC Input 5, Select analog function with GPIO_PACFGH[7:4] Data signal of Packet Trace Interface (PTI) PTI_DATA O Disable trace interface in ARM core, Enable PTI in Ember software Select alternate output function with GPIO_PACFGH[7:4] 12 Activate FIB monitor instead of main program or bootloader when coming out of reset. nBOOTMODE I Signal is active during and immediately after a reset on nRESET.
DFZM-E72xx Select UART with SC1_MODE Select alternate output function with GPIO_PBCFGL[7:4] Timer 2 channel 1 output TIM2C1 O Enable remap with TIM2_OR[4], Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[7:4] TIM2C1 PB2 I I/O Timer 2 channel 1 input, Disable remap with TIM2_OR[4] Digital I/O SPI master data in of Serial Controller 1 SC1MISO I Select SPI with SC1_MODE, Select master with SC1_SPICR SPI slave data in of Serial Controller 1 SC1MOSI I Select SPI with S
DFZM-E72xx Digital I/O, Either Enable with GPIO_DBGCFG[5] PC3 I/O or enable Serial Wire mode (see JTMS description) 20 JTAG data in from debugger JTDI I Selected when in JTAG mode (default mode, see JTMS description, Pin 21) Internal pull-up is enabled PC4 I/O Digital I/O, Enable with GPIO_DBGCFG[5] JTAG mode select from debugger, Selected when in JTAG mode (default mode) JTAG mode is enabled after power-up or by forcing nRESET low JTMS I Select Serial Wire mode using the ARM-defined protocol thro
DFZM-E72xx Select alternate output function with GPIO_PCCFGL[7:4] Digital I/O, High current, Either enable with GPIO_DBGCFG[5] PC0 I/O or enable Serial Wire mode (see JTMS description, Pin 21) and disable TRACEDATA1 JTAG reset input from debugger JRST I Selected when in JTAG mode (default mode, see JTMS description) and TRACEDATA1 is disabled, Internal pull-up is enabled 24 IRQD I Default external interrupt source D Synchronous CPU trace data bit 1 Select 2- or 4-wire synchronous trace interface in A
DFZM-E72xx 5. Electrical Characteristics 5-1.Absolute Maximum Rating Conditions beyond those cited in Table 5-1 may cause permanent damage to the DFZM-E72xx, and must be avoided. Parameter Minimum Maximum Unit Supply voltage(VCC) -0.3 3.6 V Storage temperature range -40 125 ºC Voltage on any digitai I/O -0.3 VCC+0.3 V Table 5-1: Absolute Maximum Ratings 5-2.Recommended Operating Conditions Parameter Minimum Maximum Unit Operating supply voltage(VCC) 2.1 3.
DFZM-E72xx oscillator Simulated deep sleep (debug mode) current With no debugger activity 300 uA Reset Current Quiescent current, nRESET asserted 1.2 2.0 mA 7.5 9.
DFZM-E72xx 5-4.Digital I/O and nRESET Pin Specifications Test Conditions: TA=25 ºC, VCC=3.0V Parameter Low Schmitt switching threshold High Schmitt switching threshold Test conditions Min Typ Max VSWIL, Schmitt input threshold going from high to 0.42 x 0.5 x low VCC VCC VSWIH, Schmitt input threshold going from low to 0.62 x 0.80 x high VCC VCC Unit V V Input current for logic 0 IIL -1.0 uA Input current for logic 1 IIH +1.
DFZM-E72xx Table 5-4: Digital I/O Specifications Parameter Low Schmitt switching threshold High Schmitt switching threshold Test conditions Min Typ Max VSWIL, Schmitt input threshold going from high to 0.42 x 0.5 x low VCC VCC VSWIH, Schmitt input threshold going from low to 0.62 x 0.80 x high VCC VCC Unit V V Input current for logic 0 IIL -1.0 uA Input current for logic 1 IIH +1.
DFZM-E72xx 5-6.Radio Parameters Test Conditions: TA=25 ºC, VCC=3.
DFZM-E72xx 5-7.ADC Parameters Test Conditions: TA=25 ºC, VCC=3.0V Parameter Min Typ Max Unit 1.17 1.2 1.23 V VREF output current 1 mA VREF load capacitance 10 nF 1.3 V VREF External VREF voltage range 1.1 1.
DFZM-E72xx 6. Package and Layout Guidelines 6-1.
DFZM-E72xx Figure 6-2: DFZM-E72xx Module Dimensions (in mm) Data Sheet Sheet 30 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change
DFZM-E72xx 6-2.Layout Guidelines Keep out area for onboard antenna. All layers on the PCB must be clear. (i.e. No GND, Power trace/plane, traces.) Note: If guidelines are not followed, DFZM-E72xx range with onboard antenna will be compromised. Figure 6-3: DFZM-E72xx module onboard antenna keep-out layout guidelines (in mm) Notes: 1. All Dimensions are in mm. Tolerances shall be ±0.10 mm. 2. Absolutely no metal trace or ground layer underneath this area. 3.
DFZM-E72xx Do not use a metallic or metalized plastic for the end product enclosure. Recommendation is to keep plastic enclosure clearance of 1cm from top and bottom of the DFZM-E72xx onboard antenna keep-out area, if possible. 5-mm (0.2 in) clearance shall be the minimum as shown in Figure 6-4. Figure 6-4 Recommended clearance above and below the PCB trace antenna 6-2-1.Surface Mount Assembly The reflow profile is shown in Figure 6-5.
DFZM-E72xx Note: 1. Perform adequate test in advance as the reflow temperature profile will vary accordingly to the conditions of the parts and boards, and the specifications of the reflow furnace. 2. Be careful about rapid temperature rise in preheat zone as it may cause excessive slumping of the solder paste. 3. If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will generate in clusters at a time. 4.
DFZM-E72xx 6-3.Recommended Stencil Aperture Note: The thickness of the stencil should be 0.15mm over this area.
DFZM-E72xx 7. Ordering Information DEVICE DESCRIPTION ORDERING NUMBER Extended range module using external antenna DFZM-E7210-DT0R Extended range module using onboard antenna DFZM-E7211-DT0R Low power module using external antenna DFZM-E7220-DT0R Low power module using onboard antenna DFZM-E7221-DT0R 8. Package 8-1.
DFZM-E72xx 6 :20 ZL Unreeling direction 06 20 .
DFZM-E72xx 8-2.Reel dimension W1 ZL:200620003605.7 W0 規 格 品 名 瑋鋒編號 W0 W1 13" 100*44mm旋轉式圓盤 RUR-26-3-XL 45.0±0.5 50.0±1.
DFZM-E72xx 8-3.
DFZM-E72xx 8-4. RF exposure warning statement FCC Label Statement This device complies with part 15 of the FCC rules. Operation is subject to the following two conditions: 1. This device may not cause harmful interference, and 2. This device must accept any interference received, including interference that may cause undesired operation. Federal Communications Commission (FCC) Statement 15.
DFZM-E72xx be co-located or operating in conjunction with any other antenna or transmitter.
