DFCM-NNN50-DT0R Data sheet DFCM-NNN50-DT0R A IEEE 802.11b/g/n Wireless LAN Plus Bluetooth Low Energy System On Chip Combo Module.
DFCM-NNN50-DT0R Contents 1. Features ........................................................................................................................................... 5 1-1. General......................................................................................................................................... 5 1-2. WLAN ......................................................................................................................................... 5 1-3. Bluetooth ...............
DFCM-NNN50-DT0R 10-9. BLE Serial Peripheral Interface (SPIS/SPI) ............................................................................ 24 10-9.1.SPI Slave Specifications and Parameters ...................................................................... 25 10-9.2.SPI Master Specifications and Parameters .................................................................... 26 10-10. Two-wire interface (TWI) ..............................................................................................
DFCM-NNN50-DT0R Revision History Version Date S0.1 2016/8/15 Reason of change Initial release Maker Josh Modify S0.2 2016/11/23 1. RF TX output power and RX sensitivity spec 2. VBAT input voltage range 3. Delta logo, mechanical information and reflow Josh profile 4. Add reference schematic S0.3 2016/12/07 Modify 5.2 Recommended Operating Conditions Josh S0.4 2016/12/29 Add current consumption data Modify 11-1、11-2 reference circuit Josh S0.5 2017/02/22 S0.
DFCM-NNN50-DT0R DFCM-NNN5-DT0R Wireless LAN/BLE SoC Combo Module T his document describes the DFCM-NNN50-DT0R wireless LAN/BLE SoC combo module hardware specification. The modules provide cost effective, low power, and flexible platform to add Wi-Fi® connectivity and BLE for embedded devices for a variety of applications, such as wireless sensors and thermostats. It uses the wireless LAN chip and BLE SoC, which integrating the 2.
DFCM-NNN50-DT0R Supports IEEE 802.11 WEP, WPA, WPA2 Security SSL Security On-Chip network stack offload MCU - Integrated Network IP stack to minimize high speed mode host CPU requirements (4KB flash less than 1KB RAM, for Wi-Fi drivers) Network features TCP, UDP, DHCP, ARP, HTTP, SSL, and DNS Support SPI host interface 1-3. Bluetooth Bluetooth 4.
DFCM-NNN50-DT0R 2. Model No. Definition D F C M - N N N 5 0 - DT 0 R Lead Free Preliminary Data Sheet E=Pb free R=RoHS N=NG L=Process with Lead Serial no. 0= Consumer Application Customer code DT= Delta Define Version 0= WLAN + Bluetooth Dimension 5= 12.4x10.9 mm Bluetooth Chip N=Delta Define WLAN Specification N= IEEE 802.
DFCM-NNN50-DT0R 3.
DFCM-NNN50-DT0R 4. General Specification Standard WLAN: IEEE 802.11 b/g/n Bluetooth: V4.1 Frequency 2.412 ~ 2.484 GHz for WLAN 2.402 ~ 2.48 GHz for BT Modulation 64QAM, 16QAM, QPSK, BPSK, CCK, DQPSK, DBPSK for WLAN GFSK for Bluetooth Data Rate 802.11b: 1, 2, 5.5, 11 Mbps 802.11g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps 802.11n: 6.5, 13, 19.5, 26, 39, 52, 58.5, 65 Mbps BLE: 0.25, 1, 2 Mbps Operating Temperature -25~+85 ℃ Storage Temperature -40~+85 ℃ Antenna Impedance 50 ohm Package Size 12.4 X 10.
DFCM-NNN50-DT0R 5. Electrical Characteristics 5-1. Absolute Maximum Rating Symbol Min. Max. Units VBAT -0.3 5.0 V VDDIO -0.3 3.9 V VGPIO -0.3 2.1 V ESD-HBM 1 KV ESD-CDM 500 V Table 5-1 Absolute Maximum Rating 5-2. Recommended Operating Conditions 5-2.1. Operating Conditions Symbol Parameter Min. Typ. Max. Unit VBAT Supply voltage 3.0 3.3 4.2 V VDDIO Supply voltage 2.7 3.3 3.6 V Table 5-2 Operating Conditions 5-2.2. Power Consumption Condition: VBAT=3.3V, VDDIO=3.
DFCM-NNN50-DT0R 6. RF Characteristics 6-1. WLAN RF Characteristics Condition: VBAT=3.3V, VDDIO=3.3V, T=25℃ Item Condition Min. Typ. Max. Unit 8 12* 16 dBm -25 0 +25 ppm Fc-22MHzFc+22MHz -50 dBr 11 35 % -84 -76 dBm -10 dBm 802.11b Transmit Transmit power level 11Mbps Transmit center frequency tolerance Transmit spectral mask Transmit modulation accuracy 802.
DFCM-NNN50-DT0R 802.11g Receiver Receiver minimum input level sensitivity (PER<10%) 54Mbps -70 Receiver maximum input level (PER<10%) -65 dBm -20 dBm Table 6-2 WLAN 802.11g RF Characteristics Condition: VBAT=3.3V, VDDIO=3.3 V, T=25℃ Item Condition Min. Typ. Max. Unit 5 9* 13 dBm +25 ppm 802.
DFCM-NNN50-DT0R 6-2. Bluetooth Low Energy RF characteristics Condition: VDDIO=3.3V, T=25℃ Item Condition Min. Typ. Max. Unit Output Power -20 2.5 8 dBm Initial Frequency Offset -75 0 75 KHz F1 Average 225 250 275 KHz F2 Maximum 185 217 F2 / F1 Ratio 0.8 0.91 RF Characteristics Modulation Characteristics Sensitivity (PER<30.8%) 250Kbps Maximum Input Level (PER<30.
DFCM-NNN50-DT0R 7. Pin Description Pin Definition Function 1 BT_P0.23 Digital I/O Bluetooth General purpose I/O pin 2 BT_P0.03 Digital I/O Bluetooth General purpose I/O pin 3 GND Gnd Ground 4 ANT RF WLAN/Bluetooth RF input/output 5 GND Gnd Ground 6 BT_P0.25 Digital I/O Bluetooth general purpose I/O pin 7 BT_P0.13 Digital I/O Bluetooth general purpose I/O pin 8 BT_P0.20 Digital I/O Bluetooth general purpose I/O pin 9 BT_P0.
DFCM-NNN50-DT0R 24 BT_P0.04 Analog input ADC input 5 25 BT_P0.31 Digital I/O 26 GND Gnd 27 VBAT Power 28 GND Gnd 29 BT_P0.30 Digital I/O Bluetooth general purpose I/O pin 30 BT_P0.00 Digital I/O General purpose I/O. 31 SPI_MISO Digital I/O SPI_MISO 32 SPI_SCK Digital I/O SPI_SCK 33 SPI_SSN Digital I/O SPI_SSN Bluetooth general purpose I/O pin Ground VBAT power supply input Ground Analog input ADC Reference voltage. Bluetooth general purpose I/O pin 34 BT_P0.
DFCM-NNN50-DT0R 8. Slow Clock Requirement 8-1. External 32.768KHz crystal oscillator The 32.768 kHz crystal oscillator is designed for use with a quartz crystal in parallel resonant mode. To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet. Table 8-1 shows the specification of 32.768 kHz crystal oscillator. Table 8-1 32.768 kHz crystal oscillator specification 8-2. 32.768KHz RC oscillator The 32.
DFCM-NNN50-DT0R Table 8-2 32.768 kHz RC oscillator specification 8-3. 32.768KHz synthesized oscillator The low frequency clock can be synthesized from the high frequency clock. This saves the cost of a crystal but increases average power consumption as the high frequency clock source will have to be active. Table 8-3 32.
DFCM-NNN50-DT0R 9. Power-Up Sequence Power-Up Sequence The power-up sequence for DFCM-NNN50-DT0R is shown in Figure 9.1 The timing parameters are provided in Table 9.1 t VBAT tB VDDIO tR Figure 9.
DFCM-NNN50-DT0R 10. Peripheral Peripheral blocks which have a register interface and/or interrupt vector assigned are instantiated, one or more times, in the device address space. The instances, associated ID (for those with interrupt vectors), and base address of features are found in Table 10-1.
DFCM-NNN50-DT0R 10-1. Timer/Counters (TIMER) The timer/counter runs on the high-frequency clock source (HFCLK) and includes a 4 bit (1/2X) prescaler that can divide the HFCLK. The task/event and interrupt features make it possible to use the PPI system for timing and counting tasks between any system peripheral including any GPIO of the device. The PPI system also enables the TIMER task/event features to generate periodic output and PWM signals to any GPIO.
DFCM-NNN50-DT0R Table 10-5 RTC specification 10-3. AES Electronic Codebook Mode Encryption (ECB) The ECB encryption block supports 128 bit AES block encryption. It can be used for a range of cryptographic functions like hash generation, digital signatures, and keystream generation for data encryption/decryption. ECB encryption uses EasyDMA to access system RAM for in-place operations on cleartext and ciphertext during encryption. Table 10-6 ECB specification 10-4.
DFCM-NNN50-DT0R Table 10-7 CCM specification 10-5. Accelerated Address Resolver (AAR) Accelerated Address Resolver is a cryptographic support function to implement the "Resolvable Private Address Resolution Procedure" described in the Bluetooth Core Specification v4.0. "Resolvable Private Address Generation" should be achieved using ECB and is not supported by AAR. The procedure allows two devices that share a secret key to generate and resolve a hash based on their device address.
DFCM-NNN50-DT0R Table 10-10 Random Number Generator (RNG) specifications 10-7. Watchdog Timer (WDT) A countdown watchdog timer using the low-frequency clock source (LFCLK) offers configurable and robust protection against application lock-up. The watchdog can be paused during long CPU sleep periods for low power applications and when the debugger has halted the CPU. Table 10-11 Watchdog Timer specifications 10-8.
DFCM-NNN50-DT0R Table 10-12 Temperature sensor 10-9. BLE Serial Peripheral Interface (SPIS/SPI) The SPI interfaces enable full duplex synchronous communication between devices. They support a threewire (SCK, MISO, MOSI) bi-directional bus with fast data transfers. The SPI Master can communicate with multiple slaves using individual chip select signals for each of the slave devices attached to a bus. Control of chip select signals is left to the application through use of GPIO signals.
DFCM-NNN50-DT0R 10-9.1.SPI Slave Specifications and Parameters Table 10-14.
DFCM-NNN50-DT0R Table 10-15 SPIS timing parameters 10-9.2.
DFCM-NNN50-DT0R Table 10-17 SPI timing parameters 10-10. Two-wire interface (TWI) The two-wire interface can communicate with a bi-directional wired-AND bus with two lines (SCL, SDA). The protocol makes it possible to interconnect up to 127 individually addressable devices. The interface is capable of clock stretching, supporting data rates of 100 kbps and 400 kbps. The GPIOs used for each two-wire interface line can be chosen from any GPIO on the device and are independently configurable.
DFCM-NNN50-DT0R Table 10-19 TWI specification Figure 10-3 SCL/SDA timing Table 10-20 TWI timing parameters Preliminary Data Sheet Sheet 28 of 41 Proprietary Information and Specifications are Subject to Change Jun 27 2017
DFCM-NNN50-DT0R 10-11. Universal Asynchronous Receiver/Transmitter (UART) The Universal Asynchronous Receiver/Transmitter offers fast, full-duplex, asynchronous serial communication with built-in flow control (CTS, RTS) support in hardware up to 1 Mbps baud. Parity checking is supported. The GPIOs used for each UART interface line can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of board space and signal routing.
DFCM-NNN50-DT0R 10-13. Analog to Digital Converter (ADC) The 10 bit incremental Analog to Digital Converter (ADC) enables sampling of up to 5 external signals through a front-end multiplexer. The ADC has configurable input and reference prescaling, and sample resolution (8, 9, and 10 bit). Note: The ADC module uses the same analog inputs as the LPCOMP module (AIN0, AIN1, AIN5, AIN6, AIN07, and AREF1). Only one of the modules can be enabled at the same time.
DFCM-NNN50-DT0R 10-14. GPIO Task Event block (GPIOTE) A GPIOTE block enables GPIOs on Port 0 to generate events on pin state change which can be used to carry out tasks through the PPI system. A GPIO can also be driven to change state on system events using the PPI system. Low power detection of pin state changes on Port 0 is possible when in System ON or System OFF.
DFCM-NNN50-DT0R Table 10-26 Low power comparator specifications 10-16. GPIO The general purpose I/O is organized as one port with up to 14 I/Os enabling.
DFCM-NNN50-DT0R 10-17. Debugger support The two pin Serial Wire Debug (SWD) interface provided as a part of the Debug Access Port (DAP) in conjunction with the Nordic Trace Buffer (NTB) offers a flexible and powerful mechanism for non-intrusive debugging of program code. Breakpoints, single stepping, and instruction trace capture of code execution flow are part of this support. 10-18. WLAN SPI Slave Interface WLAN provides a Serial Peripheral Interface (SPI) that operates as a SPI slave.
DFCM-NNN50-DT0R Table 10-29 SPI Slave Interface Pin Mapping Figure 10-4 SPI Slave Clock Polarity and Clock Phase Timing Preliminary Data Sheet Sheet 34 of 41 Proprietary Information and Specifications are Subject to Change Jun 27 2017
DFCM-NNN50-DT0R Figure 10-5 SPI Slave Timing Diagram Table 10-30 SPI Slave Timing Parameters Preliminary Data Sheet Sheet 35 of 41 Proprietary Information and Specifications are Subject to Change Jun 27 2017
DFCM-NNN50-DT0R 11. Reference Circuit 11-1.
DFCM-NNN50-DT0R 11-2.
DFCM-NNN50-DT0R 12.
DFCM-NNN50-DT0R 13.
DFCM-NNN50-DT0R 14. Important Notice 14.1 Federal Communications Commission (FCC) Notice You are cautioned that changes or modifications not expressly approved by the part responsible for compliance could void the user’s authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
DFCM-NNN50-DT0R Required end product labeling: Any device incorporating this module must include an external, visible, permanent marking or label which states: “Contains FCC ID: H79DFCM-NNN50.” Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module.
