Reference Guide

Statement of Volatility – Dell EMC PowerEdge C6525
The Dell EMC PowerEdge C6525 contains both volatile and non-volatile (NV) components. Volatile components lose their data
immediately upon removal of power from the component. Non-volatile components continue to retain their data even after the power has
been removed from the component.
Components chosen as user-definable configuration options (those not soldered to the motherboard) are not included in the Statement
of Volatility. Configuration option information (pertinent to options such as microprocessors, remote access controllers, and storage
controllers) is available by component separately.
The following Volatile / Non-Volatile components are present in the PowerEdge C6525 sled:
Item
Non-Volatile or Volatile
Quantity
Reference Designator
Size
Planar
CPU Internal CMOS RAM
Volatile
1
CPU0
256 MB
BIOS SPI Flash
Non-Volatile
1
U4
32 MB
DATA ROM
Non-Volatile
1
U31
4MB
iDRAC SPI Flash
Non-Volatile
1
U_BMC_SPI1
4 MB
BMC EMMC
Non-Volatile
1
U_EMMC
8 GB
System CPLD RAM
Volatile/ Non-Volatile
1
U_CPLD
54 Kb /240 Kb
System Memory
Volatile
1
CPU1:
CPU1_CH0_D0-
CPU1_CH7_D0
Up to 64GB per DIMM
(RDIMM)
CPU2:
CPU2_CH0_D0-
CPU2_CH7_D0
Up to 128GB per DIMM
(LRDIMM)
CPU Vcore and VDDCR SOC
FW
Non-Volatile
1
Vcore/VDDCR SOC
CPU1: PU62/ PU63
CPU2: PU64/ PU65
MEM_VDDQ FW
Non-Volatile
1
CPU1: PU66
CPU2
: PU67
LOM NVRAM
Non-Volatile
1
U7
8Mb
Risers 1A
MCU
Non-Volatile
1
U6
8KB
SD SPI ROM
Non-Volatile
1
U4
64KB
RSPI ROM
Non-Volatile
1
U5
4MB
Risers 1B
MCU
Non-Volatile
1
U6
8KB
RSPI ROM
Non-Volatile
1
U5
4MB
Risers 2A
MCU
Non-Volatile
1
U801
8KB
Item
How is data input to this memory?
How is this memory write protected?
Planar
CPU Internal CMOS RAM
BIOS
N/A – BIOS code control only
BIOS SPI Flash
SPI interface via iDRAC
No HW write protection
DATA ROM
SPI interface via host
Software write by host
iDRAC SPI Flash
SPI interface via iDRAC
Software write protected by iDRAC
BMC EMMC
NAND Flash interface via iDRAC
No HW write protection.
Memory VDDQ, CPU Vcore and
By fixture via I2C.
No HW write protection.
System CPLD RAM
By fixture via Jtag.
No HW write protection.
System Memory
System OS RAM
System OS
System Memory
System OS
OS Control
Riser 1A
MCU
C2 bus via iDRAC
No HW write protection
SD SPI ROM
Software utility
No HW write protection
RSPI ROM
SPI interface via iDRAC
No HW write protection
Riser 1B
MCU
C2 bus via iDRAC
No HW write protection
RSPI ROM
SPI interface via iDRAC
No HW write protection
Riser 2A
MCU
C2 bus via iDRAC
No HW write protection