Reference Guide

Direct from Development
Server and Infrastructure Engineering
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24 NVMe Drive R7525:
Designed for Maximum Storage Bandwidth
Introduction
NVMe drives are designed for high speed, low latency access to
storage. The NVMe protocol is a lightweight protocol that is built on
top of the PCIe bus. Most NVMe devices use x4 PCIe lanes,
allowing maximum bandwidth to the device. Since PCIe is the
default interface between the CPU and peripherals, NVMe drives
can be connected directly to the CPU.
The number of available PCIe lanes usually dictates the number of
NVMe devices that can be directly connected to the CPU. In case
a system does not have enough free PCIe lanes, one or more PCIe
switches can be used to connect more NVMe devices to the CPU.
This results in a design that is considered as oversubscribed. For
example, if 24 x4 NVMe devices are connected to the CPUs using
32 PCIe lanes, this would be considered as a 3:1 oversubscription.
2nd Gen AMD EPYC 7002 series and PCIe
The 2U 2-socket Dell PowerEdge R7525 featuring 2nd Gen AMD
EPYC 7002 series processors has plenty of available PCIe lanes.
Each 2nd Gen AMD EPYC processor has 128 available PCIe lanes
for use. In the standard 2-socket configuration, 128 PCIe lanes are
available for peripherals, with the rest being used for inter-socket
communication. However, some of the inter-socket xGMI2 lanes
can also be repurposed to add PCIe lanes. In this way, some
configurations have an additional 32 lanes giving a total of 160
PCIe lanes for peripherals.
Figure 1 - Diagram showing PCIe lanes in a 2-socket configuration
Tech Note by
Mohan Rokkam
Summary
The PowerEdge R7525
featuring 2nd Gen AMD
EPYC 7002 series
processors with 24 NVMe
drives provides a unique
combination non-
oversubscribed NVMe
storage along with plenty of
peripheral options to
support applications that
require maximum
performance.