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18 Mbit QDR

II SRAM Two Word Burst

Architecture

CY7C1312BV18

CY7C1314BV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05619 Rev. *G Revised August 25, 2009

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 250 MHz clock for high bandwidth

■ 2-word burst on all accesses

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 500 MHz) at 250 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self timed writes

■ Available in x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V

= 1.8V (±0.1V); IO V

DDQ

= 1.4V to V

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1312BV18 – 1M x 18

CY7C1314BV18 – 512K x 36

Functional Description

The CY7C1312BV18, and CY7C1314BV18 are 1.8V

Synchronous Pipelined SRAMs, equipped with QDR

II archi-

tecture. QDR II architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. QDR II

architecture has separate data inputs and data outputs to

completely eliminate the need to “turn around” the data bus

required with common IO devices. Access to each port is accom-

plished through a common address bus. The read address is

latched on the rising edge of the K clock and the write address

is latched on the rising edge of the K

clock. Accesses to the QDR

II read and write ports are completely independent of one

another. To maximize data throughput, both read and write ports

are provided with DDR interfaces. Each address location is

associated with two 18 bit words (CY7C1312BV18), or 36 bit

words (CY7C1314BV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K

and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus “turn arounds”.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self timed write circuitry.

Selection Guide

Description 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 250 200 167 MHz

Maximum Operating Current x18 800 675 600 mA

x36 900 750 650

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Summary of content (27 pages)

PAGE 1
CY7C1312BV18 CY7C1314BV18 18 Mbit QDR® II SRAM Two Word Burst Architecture Features Functional Description ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minim
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CY7C1312BV18 CY7C1314BV18 Logic Block Diagram (CY7C1312BV18) K CLK Gen. DOFF 19 Address Register Read Add. Decode K Write Reg 512K x 18 Array Address Register Write Reg 512K x 18 Array A(18:0) 19 18 Write Add. Decode D[17:0] A(18:0) RPS Control Logic C Read Data Reg. C CQ 36 VREF WPS 18 Control Logic 18 BWS[1:0] Reg. Reg. 18 Reg. 18 CQ 18 Q[17:0] Logic Block Diagram (CY7C1314BV18) K CLK Gen. DOFF 18 Address Register Read Add.
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CY7C1312BV18 CY7C1314BV18 Pin Configuration The pin configuration for CY7C1312BV18, and CY7C1314BV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Table 1.
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CY7C1312BV18 CY7C1314BV18 Pin Definitions Pin Name IO Pin Description D[x:0] InputSynchronous Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1312BV18 - D[17:0] CY7C1314BV18 - D[35:0] WPS InputSynchronous Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
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CY7C1312BV18 CY7C1314BV18 Pin Definitions Pin Name (continued) IO Pin Description TDO Output TDO for JTAG. TCK Input TCK Pin for JTAG. TDI Input TDI Pin for JTAG. TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/36M N/A Not Connected to the Die. Can be tied to any voltage level. NC/72M N/A Not Connected to the Die. Can be tied to any voltage level. NC/144M N/A Not Connected to the Die. Can be tied to any voltage level.
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CY7C1312BV18 CY7C1314BV18 Functional Overview The CY7C1312BV18, and CY7C1314BV18 are synchronous pipelined Burst SRAMs equipped with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required.
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CY7C1312BV18 CY7C1314BV18 Echo Clocks DLL Echo clocks are provided on the QDR II to simplify data capture on high speed systems. Two echo clocks are generated by the QDR II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock (C/C) of the QDR II. In single clock mode, CQ is generated with respect to K and CQ is generated with respect to K.
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CY7C1312BV18 CY7C1314BV18 Truth Table The truth table for CY7C1312BV18, and CY7C1314BV18 follows. [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write Cycle: Load address on the rising edge of K; input write data on K and K rising edges. L-H X L D(A + 0) at K(t) ↑ Read Cycle: Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges.
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CY7C1312BV18 CY7C1314BV18 Write Cycle Descriptions The write cycle description table for CY7C1314BV18 follows. [2, 8] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – Document #: 38-05619 Rev.
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CY7C1312BV18 CY7C1314BV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Instruction Register These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 1.8V IO logic levels. Three bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in on page 13.
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CY7C1312BV18 CY7C1314BV18 between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state. SAMPLE Z BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins.
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CY7C1312BV18 CY7C1314BV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 0 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 0 0 1 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05619 Rev.
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CY7C1312BV18 CY7C1314BV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 106 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [10, 11, 12] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V VOH2 Output HIGH Voltage IOH = −100 μA 1.
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CY7C1312BV18 CY7C1314BV18 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency 50 ns tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns Setup Times Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Ho
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CY7C1312BV18 CY7C1314BV18 Identification Register Definitions Value Instruction Field Description CY7C1312BV18 CY7C1314BV18 000 000 Cypress Device ID (28:12) 11010011010010101 11010011010100101 Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicates the presence of an ID register. Revision Number (31:29) Version number. Defines the type of SRAM.
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CY7C1312BV18 CY7C1314BV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D
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CY7C1312BV18 CY7C1314BV18 Power Up Sequence in QDR II SRAM QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (all other inputs can be HIGH or LOW). ❐ Apply VDD before VDDQ. ❐ Apply VDDQ before VREF or at the same time as VREF. ❐ Drive DOFF HIGH. ■ Provide stable DOFF (HIGH), power and clock (K, K) for 1024 cycles to lock the DLL.
PAGE 18
CY7C1312BV18 CY7C1314BV18 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Neutron Soft Error Immunity Parameter Description Ambient Temperature with Power Applied.. –55°C to +125°C Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V DC Input Voltage [11] Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch up Current........................
PAGE 19
CY7C1312BV18 CY7C1314BV18 Electrical Characteristics (continued) DC Electrical Characteristics Over the Operating Range [12] Parameter Description Test Conditions Min Typ Max Unit 250 MHz (x18) 400 mA Notes 15. Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 16. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms. 17. Output are impedance controlled.
PAGE 20
CY7C1312BV18 CY7C1314BV18 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V Unit CIN Input Capacitance 5 pF CCLK Clock Input Capacitance 6 pF CO Output Capacitance 7 pF 165 FBGA Package Unit 18.7 °C/W 4.5 °C/W Thermal Resistance Tested initially and after any design or process change that may affect these parameters.
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CY7C1312BV18 CY7C1314BV18 Switching Characteristics Over the Operating Range [20, 21] Cypress Consortium Parameter Parameter 250 MHz Description 167 MHz Min Max Min Max Min Max VDD(Typical) to the First Access [22] tPOWER 200 MHz 1 1 1 Unit ms tCYC tKHKH K Clock and C Clock Cycle Time 4.0 8.4 5.0 8.4 6.0 8.4 ns tKH tKHKL Input Clock (K/K and C/C) HIGH 1.6 – 2.0 – 2.4 – ns tKL tKLKH Input Clock (K/K and C/C) LOW 1.6 – 2.0 – 2.
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CY7C1312BV18 CY7C1314BV18 Switching Characteristics Over the Operating Range [20, 21] (continued) Cypress Consortium Parameter Parameter 250 MHz Description 167 MHz Min Max Min Max Min Max VDD(Typical) to the First Access [22] tPOWER 200 MHz 1 1 1 Unit ms tCYC tKHKH K Clock and C Clock Cycle Time 4.0 8.4 5.0 8.4 6.0 8.4 ns tKH tKHKL Input Clock (K/K and C/C) HIGH 1.6 – 2.0 – 2.4 – ns tKL tKLKH Input Clock (K/K and C/C) LOW 1.6 – 2.0 – 2.
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CY7C1312BV18 CY7C1314BV18 Switching Waveforms Figure 5.
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CY7C1312BV18 CY7C1314BV18 Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors.
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CY7C1312BV18 CY7C1314BV18 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm) 51-85180 *B Document #: 38-05619 Rev.
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CY7C1312BV18 CY7C1314BV18 Document History Page Document Title: CY7C1312BV18/CY7C1314BV18, 18 Mbit QDR® II SRAM Two Word Burst Architecture Document Number: 38-05619 Orig.
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CY7C1312BV18 CY7C1314BV18 Document History Page Document Title: CY7C1312BV18/CY7C1314BV18, 18 Mbit QDR® II SRAM Two Word Burst Architecture Document Number: 38-05619 *E 1274723 VKN See ECN Corrected typo in the JTAG ID code for CY7C1910BV18 *F 2511674 VKN/ PYRS 06/03/08 Updated Logic Block diagrams Updated IDD/ISB specs Added footnote# 19 related to IDD Updated power up sequence waveform and its description Changed DLL minimum operating frequency from 80 MHz to 120 MHz Changed ΘJA spec from 28.