MPR603HSU-03 (IBM Order Number) MPC603EC/D (Motorola Order Number) 5/95 REV 2 ™ Advance Information PowerPC 603 ™ RISC Microprocessor Hardware Specifications The PowerPC 603 microprocessor is an implementation of the PowerPC™ family of reduced instruction set computer (RISC) microprocessors. This document contains pertinent physical characteristics of the 603. For functional characteristics of the processor, refer to the PowerPC 603 RISC Microprocessor User’s Manual.
1.1 Overview The 603 is the first low-power implementation of the PowerPC microprocessor family of RISC microprocessors. The 603 implements the 32-bit portion of the PowerPC Architecture™ specification, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits.
• Five independent execution units and two register files — BPU featuring static branch prediction — A 32-bit IU — Fully IEEE 754-compliant FPU for both single- and double-precision operations — LSU for data transfer between data cache and GPRs and FPRs — SRU that executes condition register (CR) and special-purpose register (SPR) instructions — Thirty-two GPRs for integer operands — Thirty-two FPRs for single- or double-precision operands • High instruction and data throughput — Zero-cycle branch capabi
1.2 General Parameters The following list provides a summary of the general parameters of the 603. Technology Die size Transistor count Logic design Max. internal frequency Max. bus frequency Package Power supply 0.5 µ CMOS (four-layer metal) 11.5 mm x 7.4 mm 1.6 million Fully-static 80 MHz 66.67 MHz Surface mount, 240-pin CQFP 3.3 ± 5% V dc For ordering information, refer to Section 1.8, “Ordering Information.” 1.
Table 3 provides the DC electrical characteristics for the 603. Table 3. DC Electrical Specifications Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C Characteristic Symbol Min Max Unit Input high voltage (all inputs except SYSCLK) VIH 2.2 5.5 V Input low voltage (all inputs except SYSCLK) VIL GND 0.8 V SYSCLK input high voltage CVIH 2.4 5.5 V CVIL GND 0.4 V Iin — 10 µA Iin — TBD µA ITSI — 10 µA ITSI — TBD µA Output high voltage, IOH = –9 mA VOH 2.
Table 4. Power Dissipation (Continued) Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C CPU Clock: SYSCLK Bus Frequency (SYSCLK) Unit 25 MHz 33 MHz 40 MHz 50 MHz 66 MHz Nap Mode1 1:1 Typical 2:1 Typical 160 140 mW 160 mW Sleep Mode1 1:1 Typical 2:1 Typical 125 110 mW 130 mW Sleep Mode—PLL Disabled1 1:1 Typical 2:1 Typical 70 30 Sleep Mode—PLL and SYSCLK 1:1 Typical 2:1 Typical mW 40 mW Disabled1 2.0 2.0 mW 2.0 mW Note: 1.
Table 5. Clock AC Timing Specifications (Continued) Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ TJ ≤ 105 °C 25 MHz Num 33.33 MHz 40 MHz 50 MHz 66.67 Characteristic Min Max Min Max Min Max Min Max Min Unit Notes Max 8 SYSCLK short- and long-term jitter — ±150 — ±150 — ±150 — ±150 — ±150 ps 2 9 603 internal PLL relock time — 100 — 100 — 100 — 100 — 100 µs 3,4 Notes: 1. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V. 2.
Table 6. Input AC Timing Specifications Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ TJ ≤ 105 °C 25 MHz Num 33.33 MHz 40 MHz 50 MHz 66.67 MHz Characteristic Min Max Min Max Min Max Min Max Min Max Unit Notes 10a Address/data/transfer attribute inputs valid to SYSCLK (input setup) 4.5 — 4.0 — 3.5 — 3.0 — 2.5 — ns 2 10b All other inputs valid to SYSCLK (input setup) 6.5 — 6.0 — 5.5 — 5.0 — 4.
SYSCLK VM 10a 10b 11a 11b ALL INPUTS VM = Midpoint Voltage (1.4V) Figure 2. Input Timing Diagram VM HRESET 10c 11c MODE PINS VM = Midpoint Voltage (1.4 V) Figure 3. Mode Select Input Timing Diagram 1.3.2.3 Output AC Specifications Table 7 provides the output AC timing specifications for the 603 (shown in Figure 4). These specifications are for 25, 33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies. Table 7. Output AC Timing Specifications Vdd = 3.
Table 7. Output AC Timing Specifications (Continued) Vdd = 3.3 ± 5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ TJ ≤ 105 °C 25 Num 33.33 40 50 66.67 Characteristic Unit Min Max Min Max Min Max Min Max Min Max Notes 14a SYSCLK to output valid (5.5 V to 0.8 V— all except TS, ABB, ARTRY, DBB ) — 16.0 — 15.0 — 14.0 — 13.0 — 12.0 ns 4 14b SYSCLK to output valid (all except TS, ABB, ARTRY, DBB) — 14.0 — 13.0 — 12.0 — 11.0 — 10.
VM VM VM SYSCLK 14 15 16 12 ALL OUTPUTS (Except TS, ABB DBB, ARTRY) 13 15 16 13 TS 17 ABB, DBB 21 20 19 18 ARTRY VM = Midpoint Voltage (1.4 V) Figure 4.
1.3.3 JTAG AC Timing Specifications Table 8 provides the JTAG AC timing specifications. Table 8. JTAG AC Timing Specifications (Independent of SYSCLK) Vdd = 3.3 ± 5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ TJ ≤ 105 °C Num Characteristic Min Max Unit Notes TCK frequency of operation 0 16 MHz 1 TCK cycle time 62.5 — ns 2 TCK clock pulse width measured at 1.
Figure 6 provides the TRST timing diagram. TCK 4 TRST 5 Figure 6. TRST Timing Diagram Figure 7 provides the boundary-scan timing diagram. TCK 6 Data Inputs 7 Input Data Valid 8 Data Outputs Output Data Valid 9 Data Outputs 8 Data Outputs Output Data Valid Figure 7. Boundary-Scan Timing Diagram Figure 8 provides the test access port timing diagram. TCK 10 TDI, TMS 11 Input Data Valid 12 TDO Output Data Valid 13 TDO 12 TDO Output Data Valid Figure 8.
1.
1.5 Pinout Listing Table 9 provides the pinout listing for the 603. Table 9.
Table 9.
Table 9. PowerPC 603 Microprocessor Pinout Listing (Continued) Signal Name Pin Number Active I/O TS 149 Low I/O TT0–TT4 191, 190, 185, 184, 180 High I/O VDD 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, 207 High Input WT 236 Low Output XATS 150 Low I/O Notes: 1. These are test signals for factory use only and must be pulled up to VDD for normal machine operation. 2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core.
1.6.1.2 Mechanical Dimensions of the Motorola Wire-Bond CQFP Package Figure 10 shows the mechanical dimensions for the wire-bond CQFP package. AB θI R –H– θ2 R G H AA F C A J B *Reduced pin count shown for clarity. 60 pins per side A B C D E F G H J AA AB θ1 θ2 R Pin 240 Pin 1 Min. Max. 30.86 31.75 34.6 BSC 3.75 4.15 0.5 BSC 0.18 0.30 3.10 3.90 0.13 0.175 0.45 0.55 0.25 – 1.80 REF 0.95 REF 2° 6° 1° 7° 0.15 REF Notes: 1. BSC—Between Standard Centers. 2. All measurements in mm.
1.6.2 IBM C4-CQFP Package Description The following sections provide the package parameters and mechanical dimensions for the IBM C4-CQFP package. 1.6.2.1 Package Parameters The package parameters are as provided in the following list. The package type is 32 mm x 32 mm, 240-pin ceramic quad flat pack. Package outline 32 mm x 32 mm Interconnects 240 Pitch 0.5 mm Lead plating Ni Au Solder joint Sn/PB (10/90) Lead encapsulation Epoxy Solder-bump encapsulation Epoxy Maximum module height 3.
1.6.2.2 Mechanical Dimensions of the IBM C4-CQFP Package Figure 11 shows the mechanical dimensions for the C4-CQFP package. Epoxy Dam Solder-Bump Encapsulant Chip F Rad Ang G Urethane Clip Leadframe Jmin H Tape Cast Ceramic Cmax 0.08 CA 0.13 TOTAL s A-B *Reduced pin count shown for clarity. 60 pins per side E -B- Min. 31.8 34.4 3.05 0.45 0.18 A B C D E Max. 32.2 34.8 3.15 0.55 0.28 D 0.08 TOTAL M A-B Pin 240 Pin 1 -AB 0.13 TOTAL s A-B * Not to scale All measurements in mm Figure 11.
1.7 System Design Information This section provides electrical and thermal design recommendations for successful application of the 603. 1.7.1 PLL Configuration A 603 part number corresponds to a particular combination of internal (CPU core) and SYSCLK (external bus) frequency ranges which the device has been tested to. The PLL is configured by the PLL_CFG0–PLL_CFG3 pins. For a given SYSCLK (bus) frequency, the PLL configuration pins set the internal CPU frequency of operation. Table 10.
1.7.2 PLL Power Supply Filtering The AVdd power signal is provided on the 603 to provide power to the clock generation phase-lock loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using a circuit similar to the one shown in Figure 12. The circuit should be placed as close as possible to the AVdd pin to ensure it filters out as much noise as possible. 10 Ohms Vdd AVdd 0.1 uF 10 uF GND Figure 12. PLL Power Supply Filter Circuit 1.7.
Figure 13 provides a thermal management example for the Motorola wire-bond CQFP package. Junction-to-Ambient Thermal Resistance (°C/watt) 35 30 Motorola Wire-Bond CQFP 25 20 15 With Heat Sink 10 5 0 0 1 2 3 4 5 Forced Convection (m/sec) Figure 13.
Notes: 1. Junction-to-ambient thermal resistance is based on measurements on single-sided printed circuit boards per SEMI (Semiconductor Equipment and Materials International) G38-87 in natural convection. 2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88 with the exception that the cold plate temperature is used for the case temperature. The vendors who supply heat sinks are Aavid Engineering, IERC, Thermalloy, and Wakefield Engineering.
Figure 14 provides a thermal management example for the IBM C4-CQFP package. 40 Junction-to-Ambient Thermal Resistance (°C/W) 35 IBM C4-CQFP Exposed Die 30 25 Aluminum Plate 20 15 10 Pinfin 5 0 0 0.25 0.5 1 2 Forced Convection (m/sec) Figure 14. IBM C4-CQFP Thermal Management Example For a power dissipation of 2.
1.8 Ordering Information This section provides the ordering information for the 603. Note that the individual part numbers correspond to a specific combination of 603 internal/bus frequencies, which must be observed to ensure proper operation of the device. For other frequency combinations, temperature ranges, power-supply tolerances package types, etc., contact your local Motorola or IBM sales office. Table 11.
Appendix A General Handling Recommendations for the IBM Package The following list provides a few guidelines for package handling: • Handle the electrostatic discharge sensitive (ESD) package with care before, during, and after processing. • Do not apply any load to exceed 3 Kg after assembly. • Components should not be hot dip tinned • The package encapsulation is an acrylated urethane. Use adequate ventilation (local exhaust) for all elevated temperature processes.
A.2 Card Assembly Recommendations This section provides recommendations for card assembly process. Follow these guidelines for card assembly. • This component is supported for aqueous, IR, convection reflow, and vapor phase card assembly processes. • The temperature of packages should not exceed 220 °C for longer than 5 minutes. • The package entering a cleaning cycle must not be exposed to temperature greater than that occurring during solder reflow or hot air exposure.
Clean after reflow De-ionized (D.I.) water if water-soluble paste is used •Cleaner requirements—conveyorized, in-line •Minimum of four washing chambers —Pre-clean chamber: top and bottom sprays, minimum top-side pressure of 25 psig, water temperature of 70 °C minimum, dwell time of 24 seconds minimum, water is not re-used, water flow rate of 30 liters/minute. —Wash chamber #1: top and bottom sprays, minimum top-side pressure of 48 psig, minimum bottom-side pressure of 44 psig, water temperature of 62.
Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or fabricate circuits based on the information in this document. The PowerPC 603 microprocessor embodies the intellectual property of Motorola and of IBM.
