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Cinterion

PLSx3

Hardware Interface Description

Version: 01.002d

DocId: PLSx3_HID_v01.002d

Summary of content (130 pages)

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Cinterion® PLSx3 Hardware Interface Description Version: DocId: 01.002d PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 2 of 129 2 Document Name: Cinterion® PLSx3 Hardware Interface Description Version: 01.002d Date: 2021-08-24 DocId: PLSx3_HID_v01.002d Status Public / Released GENERAL NOTE THIS DOCUMENT CONTAINS INFORMATION ON THALES DIS AIS DEUTSCHLAND GMBH (“THALES”) PRODUCTS. THALES RESERVES THE RIGHT TO MAKE CHANGES TO THE PRODUCTS DESCRIBED HEREIN. THE SPECIFICATIONS IN THIS DOCUMENT ARE SUBJECT TO CHANGE AT THE DISCRETION OF THALES.
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Cinterion® PLSx3 Hardware Interface Description Page 3 of 129 Contents 129 Contents 1 Introduction ................................................................................................................. 9 1.1 Product Variants ................................................................................................ 9 1.2 Key Features at a Glance .................................................................................. 9 1.2.1 Supported Frequency Bands ...........................
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Cinterion® PLSx3 Hardware Interface Description Page 4 of 129 Contents 129 3.2 3.3 3.4 3.5 3.6 3.7 4 Power Up/Power Down Scenarios ................................................................... 68 3.2.1 Turn on PLSx3 .................................................................................... 68 3.2.2 Restart PLSx3..................................................................................... 68 3.2.2.1 Restart PLSx3 Using Restart Command............................. 68 3.2.2.
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Cinterion® PLSx3 Hardware Interface Description Page 5 of 129 Contents 129 4.3.2 Shipping Materials ............................................................................ 102 4.3.2.1 Moisture Barrier Bag ......................................................... 102 4.3.2.2 Transportation Box ............................................................ 105 5 Regulatory and Type Approval Information ......................................................... 106 5.1 Directives and Standards.........
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Cinterion® PLSx3 Hardware Interface Description Page 6 of 129 Tables Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: t Supported frequency bands for each PLS
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Cinterion® PLSx3 Hardware Interface Description Page 7 of 129 Figures Figures Figure 1: Figure 2: Figure 3: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: F
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Cinterion® PLSx3 Hardware Interface Description Page 8 of 129 Figures Figure 50: Figure 51: Figure 52: t JATE/TELEC mark for -J.............................................................................. 117 JATE/TELEC mark for -W ............................................................................ 117 PLSx3 Label................................................................................................. 128 PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 9 of 129 1 Introduction 17 1 Introduction This document1 describes the hardware of the Cinterion® PLSx3 module. It helps you quickly retrieve interface specifications, electrical and mechanical details and information on the requirements to be considered for integrating further components. Note: This Hardware Interface Description is a preliminary version and as such subject to change depending on further implementation and measurements. 1.
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Cinterion® PLSx3 Hardware Interface Description Page 10 of 129 1.
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Cinterion® PLSx3 Hardware Interface Description Page 11 of 129 1.2 Key Features at a Glance 17 Feature Implementation 3GPP Release 7 UE CAT. 8, 6 for PLS63 HSDPA – DL 7.2Mbps HSUPA – UL 5.7Mbps UE CAT. 14, 6 for PLS83 HSPA+ – DL 21Mbps HSUPA – UL 5.7Mbps Compressed mode (CM) supported according to 3GPP TS25.
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Cinterion® PLSx3 Hardware Interface Description Page 12 of 129 1.2 Key Features at a Glance 17 Feature Implementation Interfaces Module interface Surface mount device with solderable connection pads (SMT application interface). Land grid array (LGA) technology ensures high solder joint reliability and allows the use of an optional module mounting socket. For more information on how to integrate SMT modules see also [4].
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Cinterion® PLSx3 Hardware Interface Description Page 13 of 129 1.2 Key Features at a Glance 17 Feature Implementation DSB-mini DSB-mini Development Support Board designed to test and type approve. It is the cost optimized development board alternative to DSB75. DSB75 DSB75 Development Support Board designed to test and type approve Thales modules and provide a sample configuration for application engineering. A special adapter is required to connect the PLSx3 evaluation module to the DSB75.
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Cinterion® PLSx3 Hardware Interface Description Page 14 of 129 1.2 Key Features at a Glance 17 1.2.1 Supported Frequency Bands The following table lists the supported frequency bands for each of the PLSx3 product variants mentioned in Section 1.1. Table 1: Supported frequency bands for each PLSx3 variant Band PLSx3-W PLSx3-X PLSx3-EP PLSx3-LA PLSx3-J PLSx3-X2 PLSx3-X3 PLSx3-X4 PLSx3-I GSM/GPRS/EDGE 850MHz x x x 900MHz x x x x 1800MHz x x x x 1900MHz x x x Bd.
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Cinterion® PLSx3 Hardware Interface Description Page 15 of 129 1.2 Key Features at a Glance 17 Table 1: Supported frequency bands for each PLSx3 variant Band PLSx3-W PLSx3-X PLSx3-EP PLSx3-LA Bd.7 (2600MHz) x x x Bd.8 (900MHz) x x x Bd.12 (700MHz) Bd.13 (700MHz) 1 PLSx3-J PLSx3-X2 PLSx3-X3 x x x x x x x x x x x Bd.17 (700 MHz) PLSx3-I x x Bd.14(700MHz) PLSx3-X4 x x x x Bd.18 (850MHz) x x Bd.19 (850MHz) x x Bd.20 (800MHz) x Bd.25(1900MHz) x x Bd.
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Cinterion® PLSx3 Hardware Interface Description Page 16 of 129 1.3 PLSx3 System Overview 17 1.
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Cinterion® PLSx3 Hardware Interface Description Page 17 of 129 1.4 Circuit Concept 17 1.4 Circuit Concept Figure 2 shows block diagrams of the PLSx3 module and illustrate the major functional components: BATT+BB EMERG_RST VGNSS IGT V180 PMU ADC_IN XTAL Power Power Control STATUS MCLK BUS SIM_SWITCH Memory FAST_SHDN Control USB ASC0 ASC1 GPIO SOC ANT PWR_IND RF I2S/PCM UIM1 UIM2 Figure 2: PLSx3 block diagram t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 18 of 129 2 Interface Characteristics 66 2 Interface Characteristics PLSx3 is equipped with an SMT application interface that connects to the external application. The SMT application interface incorporates the various application interfaces as well as the RF antenna interface. 2.1 Application Interface 2.1.
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Cinterion® PLSx3 Hardware Interface Description Page 19 of 129 2.1 Application Interface 66 Table 2: Overview: Pad assignments Pad No. Signal Name Pad No. Signal Name Pad No.
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Cinterion® PLSx3 Hardware Interface Description Page 20 of 129 2.
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Cinterion® PLSx3 Hardware Interface Description Page 21 of 129 2.
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Cinterion® PLSx3 Hardware Interface Description Page 22 of 129 2.1 Application Interface 66 2.1.2 Signal Properties Table 3: Signal properties (Sheet 1 of 5) Function Signal name IO Signal form and level Comment Power supply BATT+BB BATT+RF I GSM activated: VImax = 4.5V VInorm = 3.8V VImin = 3.0V Imax= see Table 19 Lines of BATT+ and GND must be connected in parallel for supply purposes because higher peak currents may occur. ___|¯¯|____________|¯¯|___ n Tx = n x 577µs peak current every 4.
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Cinterion® PLSx3 Hardware Interface Description Page 23 of 129 2.1 Application Interface 66 Table 3: Signal properties (Sheet 2 of 5) Function Signal name IO Signal form and level Comment Ignition IGT I Do not add any voltage on it. There is a built-in pull up resister, you can test about 0.8V voltage on it. This signal switches the module on. The IGT signal characteristic is: Power on triggered and low level triggered. Fall time should be <1ms.
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Cinterion® PLSx3 Hardware Interface Description Page 24 of 129 2.1 Application Interface 66 Table 3: Signal properties (Sheet 3 of 5) Function Signal name IO Signal form and level Comment Serial Interface ASC0 RXD0 O VOLmax = 0.45V VOHmin = 1.35V If unused keep lines open. CTS0 DSR0 DCD0 Test points recommended for RXD0, TXD0, RTS0, and CTS0. RING0 TXD0 I VILmax = 0.63V VIHmin = 1.17V RTS0 I VILmax = 0.63V VIHmin = 1.17V DTR0 I VILmax = 0.63V VIHmin = 1.17V O VOLmax = 0.
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Cinterion® PLSx3 Hardware Interface Description Page 25 of 129 2.1 Application Interface 66 Table 3: Signal properties (Sheet 4 of 5) Function Signal name 1.8V SIM CCRST1 Card Inter- CCRST2 face CCIO1 CCIO2 IO Signal form and level Comment O VOLmax = 0.4V VOHmin = 1.36V VOHmax = 1.93V Maximum cable length or copper track to SIM card holder should not exceed 100mm. I/O VILmax = 0.334V VIHmin = 1.351V VIHmax = 1.97V CCIO2 should add 10k pull-up to CCVCC2 VOLmax = 0.4V VOHmin = 1.336V VOHmax = 1.
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Cinterion® PLSx3 Hardware Interface Description Page 26 of 129 2.1 Application Interface 66 Table 3: Signal properties (Sheet 5 of 5) Function Signal name IO Signal form and level Comment Power indicator PWR_IND O VIHmax = 5.5V VOLmax = 0.4V at Imax = 2mA PWR_IND (Power Indicator) notifies the module’s on/off state (see Section 2.1.10). PWR_IND is an open collector that needs to be connected to an external pullup resistor. Low state of the open collector indicates that the module is on.
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Cinterion® PLSx3 Hardware Interface Description Page 27 of 129 2.1 Application Interface 66 2.1.2.1 Absolute Maximum Ratings The absolute maximum ratings stated in Table 4 are stress ratings under any conditions. Stresses beyond any of these limits will cause permanent damage to PLSx3. Table 4: Absolute maximum ratings Parameter Min Max Unit Supply voltage BATT+ (no service) -0.3 +5.5 V Voltage at all digital pins in POWER DOWN mode -0.3 +0.3 V Voltage at digital pins 1.
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Cinterion® PLSx3 Hardware Interface Description Page 28 of 129 2.1 Application Interface 66 2.1.3 USB Interface PLSx3 supports a USB 2.0 High Speed (480Mbit/s) device interface that is Full Speed (12Mbit/ s) compliant. The impedances, serial and pull up resistors are implemented according to “Universal Serial Bus Specification Revision 2.0”1, No further additional components are required. The external application is responsible for supplying the VUSB_IN line. This line is used for cable detection only.
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Cinterion® PLSx3 Hardware Interface Description Page 29 of 129 2.1 Application Interface 66 2.1.3.1 Reducing Power Consumption While a USB connection is active, the module will never switch into SLEEP mode. Only if the USB interface is in Suspended state or Detached (i.e., VUSB_IN = 0) is the module able to switch into SLEEP mode thereby saving power.
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Cinterion® PLSx3 Hardware Interface Description Page 30 of 129 2.1 Application Interface 66 2.1.4 Serial Interface ASC0 PLSx3 offers an 8-wire unbalanced, asynchronous modem interface ASC0 conforming to ITUT V.24 protocol DCE signaling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state). For electrical characteristics please refer to Table 3. PLSx3 is designed for use as a DCE.
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Cinterion® PLSx3 Hardware Interface Description Page 31 of 129 2.1 Application Interface 66 Notes: No data must be sent over the ASC0 interface before the interface is active and ready to receive data (see Section 3.2.1). The following figure shows the startup behavior of the asynchronous serial interface ASC0.
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Cinterion® PLSx3 Hardware Interface Description Page 32 of 129 2.1 Application Interface 66 2.1.5 Serial Interface ASC1 Four PLSx3 GPIO lines can be configured as ASC1 interface signals to provide a 4-wire unbalanced, asynchronous modem interface ASC1 conforming to ITU-T V.24 protocol DCE signalling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state).
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Cinterion® PLSx3 Hardware Interface Description Page 33 of 129 2.1 Application Interface 66 The following figure shows the startup behavior of the asynchronous serial interface ASC1. Power supply active Start up Reset state Firmware initialization Command interface initialization Interface active IGT VCORE V180 EMERG_RST Internal RST TXD1 PD RXD1 PD RTS1 PD CTS1 OH For pull-down values see Table 16. Figure 8: ASC1 startup behavior t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 34 of 129 2.1 Application Interface 66 2.1.6 UICC/SIM/USIM Interface PLSx3 has two UICC/SIM/USIM interfaces (includes eSIM interface) compatible with the 3GPP 31.102 and ETSI 102 221. These are wired to the host interface in order to be connected to an external SIM card holder. Five pads on the SMT application interface are reserved for each of the two SIM interfaces. The UICC/SIM/USIM interface supports 3V and 1.8V SIM cards.
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Cinterion® PLSx3 Hardware Interface Description Page 35 of 129 2.1 Application Interface 66 Module 1st SIM interface SIM1 2nd SIM interface SIM2 Figure 9: Module’s two UICC/SIM/USIM interfaces . Figure 10: UICC/SIM/USIM interfaces connected The total cable length between the SMT application interface pads on PLSx3 and the pads of the external SIM card holder must not exceed 100mm in order to meet the specifications of 3GPP TS 51.010-1 and to satisfy the requirements of EMC compliance.
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Cinterion® PLSx3 Hardware Interface Description Page 36 of 129 2.1 Application Interface 66 2.1.6.1 Enhanced ESD Protection for SIM Interface To optimize ESD protection for the SIM interface it is possible to add ESD diodes (eg. NUP4114) to the SIM interface lines as shown in the example given in Figure 11. Please place the ESD protection close to the SIM connector. It is suggested that the cload of diode be less than 3pF.
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Cinterion® PLSx3 Hardware Interface Description Page 37 of 129 2.1 Application Interface 66 2.1.6.2 SIM_SWITCH Line As an alternative to connecting the module’s two SIM interfaces and switching between these interfaces by means of AT command, it is possible to connect the first of the module’s SIM interfaces via an external SIM switch that in turn provides access to a further SIM interface.
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Cinterion® PLSx3 Hardware Interface Description Page 38 of 129 2.1 Application Interface 66 2.1.7 GPIO Interface PLSx3 offers a GPIO interface with 22 GPIO lines. The GPIO lines are shared with other interfaces or functions: Fast shutdown (see Section 2.1.10.3), Status LED (see Section 2.1.10.1), ASC0 (see Section 2.1.4), ASC1 (see Section 2.1.5) and SIM Switch (see Section 2.1.6.2) The following table shows the configuration variants for the GPIO pads. All variants are mutually exclusive, i.e.
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Cinterion® PLSx3 Hardware Interface Description Page 39 of 129 2.1 Application Interface 66 The following figure shows the startup behavior of the GPIO interface.
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Cinterion® PLSx3 Hardware Interface Description Page 40 of 129 2.1 Application Interface 66 2.1.8 Digital Audio Interface PLSx3 supports the digital audio interface that can be deployed as PCM or Inter_IC Sound (I2S). 2.1.8.1 Pulse Code Modulation Interface PLSx3’s PCM interface can be used to connect audio devices capable of pulse code modulation. The PCM functionality is limited to the use of wideband codec with 16kHz sample rate only. The PCM interface runs at 16 kHz sample rate (62.
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Cinterion® PLSx3 Hardware Interface Description Page 41 of 129 2.1 Application Interface 66 The following figure shows an example of short frame PCM timing at 8kHz sample rate and 2048kHz PCM_CLK in the master mode: 125 µs PCMx_CLK PCMx_SYNC PCMx_OUT MSB 14 13 12 2 1 LSB MSB PCMx_IN MSB 14 13 12 2 1 LSB MSB Figure 15: PCM timing short frame 2.1.8.
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Cinterion® PLSx3 Hardware Interface Description Page 42 of 129 2.1 Application Interface 66 2.1.9 Analog-to-Digital Converter (ADC) PLSx3 provides three unbalanced ADC input line: ADC[1...3]_IN. They can be used to measure three independent, externally connected DC voltages in the range of 0.1V to 1.7V. They can be used especially for antenna diagnosing. The AT^SRADC command can be employed to select the ADC line, set the measurement mode and read out the measurement results. 2.1.
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Cinterion® PLSx3 Hardware Interface Description Page 43 of 129 2.1 Application Interface 66 2.1.10.2 Power Indication The power indication signal PWR_IND notifies the on/off state of the module. High state of PWR_IND indicates that the module is switched off. The state of PWR_IND immediately changes to low when IGT is pulled low. For state detection an external pull-up resistor is required. Module Power supply On/Off (open drain driver) SMT interface e.g.
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Cinterion® PLSx3 Hardware Interface Description Page 44 of 129 2.1 Application Interface 66 2.1.10.3 Fast Shutdown The GPIO4 interface line can be configured as fast shutdown signal line FST_SHDN. The configured FST_SHDN line is an active low control signal and must be applied for at least 1 milliseconds. If unused this line can be left open because of a configured internal pull-up resistor. Before setting the FST_SHDN line to low, the IGT signal should be set to high (see Figure 18).
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Cinterion® PLSx3 Hardware Interface Description Page 45 of 129 2.1 Application Interface 66 2.1.10.4 Remote Wakeup If no call, data or message transfer is in progress, the external host application may shut down its own module interfaces or other components in order to save power. If a call, data, or other request (URC) arrives, the external application can be notified of this event and be woken up again by a state transition of a configurable remote wakeup line.
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Cinterion® PLSx3 Hardware Interface Description Page 46 of 129 2.2 RF Antenna Interface 66 2.2 RF Antenna Interface The PLSx3 GSM/UMTS/LTE antenna interface comprises a GSM/UMTS/LTE main antenna as well as a UMTS/LTE Rx diversity antenna to improve signal reliability and quality1. The RF interface has an impedance of 50Ω. PLSx3 is capable of sustaining a total mismatch at the antenna line without any damage, even when transmitting at maximum RF power.
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Cinterion® PLSx3 Hardware Interface Description Page 47 of 129 2.2 RF Antenna Interface 66 2.2.1 Antenna Interface Specifications Table 11: RF Antenna interface GSM/UMTS/LTE Parameter Conditions LTE connectivity Band 1,2,3,4,5,7,8,12,13,14,17,18,19,20,25,26,28,38,40,41,66,71 Receiver Input Sensitivity @ARP, Combined Antenna, Channel BW at 5 MHz @25°C, 3.8V LTE FDD 2100 Band 1 -100.0 -104.3 dBm LTE FDD 1900 Band 2 -98.0 -104.7 dBm LTE FDD 1800 Band 3 -97.0 -104.
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Cinterion® PLSx3 Hardware Interface Description Page 48 of 129 2.2 RF Antenna Interface 66 Table 11: RF Antenna interface GSM/UMTS/LTE Parameter Conditions Min. Typical Max. Unit RF Power @ARP with 50Ω Load (Board temperature<85°C, 5 MHz BW, 1RB Position Low) LTE FDD 2100 Band 1 +21 +23.0 dBm LTE FDD 1900 Band 2 +21 +23.0 dBm LTE FDD 1800 Band 3 +21 +23.0 dBm LTE FDD 2100 Band 4 +21 +23.0 dBm LTE FDD 850 Band 5 +21 +23.0 dBm LTE FDD 2600 Band 7 +21 +22.
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Cinterion® PLSx3 Hardware Interface Description Page 49 of 129 2.2 RF Antenna Interface 66 Table 11: RF Antenna interface GSM/UMTS/LTE Parameter Conditions UMTS connectivity Band I,II,III, IV,V,VI,VIII,XIX Receiver Input Main Sensitivity @ ARP @25°C, 3.8V Receiver Input Diversity Sensitivity @ ARP @25°C, 3.8V RF Power @ ARP with 50Ohm Load Board temperature < 85°C Min. Typical Max. Unit UMTS 2100 Band I -106.7 -110.2 dBm UMTS 1900 Band II -104.7 -111.3 dBm UMTS 1800 Band III -103.
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Cinterion® PLSx3 Hardware Interface Description Page 50 of 129 2.2 RF Antenna Interface 66 Table 11: RF Antenna interface GSM/UMTS/LTE Parameter Conditions GPRS, 1 TX RF Power @ ARP with 50Ohm Load, (ROPR = 4, i.e. no reduction) EDGE, 1 TX GPRS, 2 TX EDGE, 2 TX GPRS, 3 TX EDGE, 3 TX GPRS, 4 TX EDGE, 4 TX t Min. Typical Max.
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Cinterion® PLSx3 Hardware Interface Description Page 51 of 129 2.2 RF Antenna Interface 66 Table 11: RF Antenna interface GSM/UMTS/LTE Parameter Conditions GPRS, 1 TX RF Power @ ARP with 50Ohm Load, (ROPR =5, i.e. partial reduction) EDGE, 1 TX GPRS, 2 TX EDGE, 2 TX GPRS, 3 TX EDGE, 3 TX GPRS, 4 TX EDGE, 4 TX t Min. Typical Max.
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Cinterion® PLSx3 Hardware Interface Description Page 52 of 129 2.2 RF Antenna Interface 66 Table 11: RF Antenna interface GSM/UMTS/LTE Parameter Conditions GPRS, 1 TX RF Power @ ARP with 50Ohm Load, (ROPR = 6, i.e. partial reduction) EDGE, 1 TX GPRS, 2 TX EDGE, 2 TX GPRS, 3 TX EDGE, 3 TX GPRS, 4 TX EDGE, 4 TX t Min. Typical Max.
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Cinterion® PLSx3 Hardware Interface Description Page 53 of 129 2.2 RF Antenna Interface 66 Table 11: RF Antenna interface GSM/UMTS/LTE Parameter Conditions GPRS, 1 TX RF Power @ ARP with 50Ohm Load, (ROPR = 7, i.e. partial reduction) EDGE, 1 TX GPRS, 2 TX EDGE, 2 TX GPRS, 3 TX EDGE, 3 TX GPRS, 4 TX EDGE, 4 TX t Min. Typical Max.
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Cinterion® PLSx3 Hardware Interface Description Page 54 of 129 2.2 RF Antenna Interface 66 Table 11: RF Antenna interface GSM/UMTS/LTE Parameter Conditions RF Power @ ARP with 50Ohm Load, (ROPR = 8, i.e. max reduction) GPRS, 1 TX EDGE, 1 TX GPRS, 2 TX EDGE, 2 TX GPRS, 3 TX EDGE, 3 TX GPRS, 4 TX EDGE, 4 TX t Min. Typical Max.
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Cinterion® PLSx3 Hardware Interface Description Page 55 of 129 2.2 RF Antenna Interface 66 Table 12: RF Antenna interface LTE for -J variant (at operating temperature range) Parameter Condition LTE connectivity Band 1,3,8,18,19,26 Receiver Input Sensitivity @ARP, Combined Antenna, Channel BW at 10MHz @25°C, 3.8V t Min. Typical Max. Unit LTE FDD 2100 Band 1 -102.2 dBm LTE FDD 1800 Band 3 -102.2 dBm LTE FDD 900 Band 8 -101.9 dBm LTE FDD 850 Band 18 -101 dBm LTE FDD 850 Band 19 -100.
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Cinterion® PLSx3 Hardware Interface Description Page 56 of 129 2.2 RF Antenna Interface 66 2.2.2 Antenna Installation The antenna is connected by soldering the antenna pads (ANT_MAIN, ANT_DRX and ANT_GNSS) and their neighboring ground pads directly to the application’s PCB.
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Cinterion® PLSx3 Hardware Interface Description Page 57 of 129 2.2 RF Antenna Interface 66 2.2.3 RF Line Routing Design 2.2.3.1 Line Arrangement Examples Several dedicated tools are available to calculate line arrangements for specific applications and PCB materials - for example from http://www.polarinstruments.com/ (commercial software) or from http:www.awr.com/awr-software/options/tx-line/ (free software).
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Cinterion® PLSx3 Hardware Interface Description Page 58 of 129 2.2 RF Antenna Interface 66 Micro-Stripline This section gives two line arrangement examples for micro-stripline. Figure 21: Micro-Stripline arrangement example t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 59 of 129 2.2 RF Antenna Interface 66 2.2.3.2 Routing Example Interface to RF Connector Figure 22 and Figure show a sample connection of a module‘s antenna pad at the bottom layer of the module PCB with an application PCB‘s coaxial antenna connector. Line impedance depends on line width, but also on other PCB characteristics like dielectric, height and layer gap. The sample stripline width of 0.33mm/0.8mm and the space of 0.625mm/0.
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Cinterion® PLSx3 Hardware Interface Description Page 60 of 129 2.2 RF Antenna Interface 66 Figure 23: Routing Detail t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 61 of 129 2.3 GNSS Antenna Interface 66 2.3 GNSS Antenna Interface 2.3.1 GNSS Receiver PLSx3 integrates a GNSS receiver that offers the full performance of GPS/GLONASS/BeiDou/ Galileo technology. The GNSS receiver is able to continuously track all satellites in view, thus providing accurate satellite position data. The integrated GNSS receiver supports the NMEA protocol.
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Cinterion® PLSx3 Hardware Interface Description Page 62 of 129 2.3 GNSS Antenna Interface 66 PLSx3 provides the signal VGNSS to enable an active GNSS antenna power supply. Figure 24 shows the flexibility in realizing the power supply for an active GNSS antenna by giving a sample circuit realizing the supply voltage for an active GNSS antenna. Application: Module RF DC DC GNSS Receiver Antenna Matching ANT_GNSS LNA Active GNSS Antenna ANT_GNSS_DC BATT+ VGNSS (3.
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Cinterion® PLSx3 Hardware Interface Description Page 63 of 129 2.3 GNSS Antenna Interface 66 Figure 25 shows a sample circuit realizing ESD protection for a passive GNSS antenna. Connecting the input ANT_GNSS_DC to GND prevents ESD from coupling into the module. Module SMT interface VGNSS 100nF Not used 22pF ANT_GNSS_DC Passive GNSS antenna (Optional) 0R ESD protection 12nH ANT_GNSS To GNSS receiver Figure 25: ESD protection for passive GNSS antenna 2.3.
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Cinterion® PLSx3 Hardware Interface Description Page 64 of 129 2.3 GNSS Antenna Interface 66 2.3.4 GNSS Antenna Interface Characteristics Table 14: GNSS properties Parameter Conditions Min. Typical Max. Unit Frequency GPS 1574.4 1575.42 1576.4 MHz GLONASS 1597.5 1602 1605.
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Cinterion® PLSx3 Hardware Interface Description Page 65 of 129 2.4 Sample Application 66 2.4 Sample Application Figure 26 shows a typical example of how to integrate a PLSx3 module with an application. Usage of the various host interfaces depends on the desired features of the application. Because of the very low power consumption design, current flowing from any other source into the module circuit must be avoided, for example reverse current from high state external control lines.
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Cinterion® PLSx3 Hardware Interface Description Page 66 of 129 2.4 Sample Application 66 BATT+_DSB PLSx3 0R 2 Main antenna BATT+BB GND 100nF ANT_MAIN 2 'HFRXSOLQJ FDSDFLWRUV H J ȝ) 0/&& ; 5 GND BATT+RF 'HFRXSOLQJ FDSDFLWRUV H J ȝ) 0/&& ; 5 Diversity antenna GND 33pF ANT_DRX V180 V180 GND GNSS antenna EMERG_RST 47k GND %& ANT_GNSS GND GND IGT 47k ANT_GNSS_DC %& ANT_GNSS_DC *For more details see Section 5.2 GNSS Antenna Interface GND E.g., VBATT USB E.g.
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Cinterion® PLSx3 Hardware Interface Description Page 67 of 129 3 Operating Characteristics 89 3 Operating Characteristics 3.1 Operating Modes The table below briefly summarizes the various operating modes referred to throughout the document.
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Cinterion® PLSx3 Hardware Interface Description Page 68 of 129 3.2 Power Up/Power Down Scenarios 89 3.2 Power Up/Power Down Scenarios In general, be sure not to turn on PLSx3 while it is beyond the safety limits of voltage and temperature stated in Section 2.1.2.1. PLSx3 immediately switches off after having started and detected these inappropriate conditions. In extreme cases this can cause permanent damage to the module. 3.2.
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Cinterion® PLSx3 Hardware Interface Description Page 69 of 129 3.2 Power Up/Power Down Scenarios 89 3.2.2.2 Restart PLSx3 Using EMERG_RST The EMERG_RST signal is internally connected to the baseband processor. A low level >2 00ms sets the processor and all signals to the reset states, and thus restart the module. Please note that if the EMERG_RST signal is not released, i.e., changed from low to high, after a restart, the module will be repeatedly restarted.
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Cinterion® PLSx3 Hardware Interface Description Page 70 of 129 3.2 Power Up/Power Down Scenarios 89 3.2.3 Signal States after Startup Table 16 lists the states each interface signal passes through during reset phase and the first firmware initialization. For further firmware startup initializations the values may differ because of different GPIO line configurations. After the reset state has been reached the firmware initialization state begins.
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Cinterion® PLSx3 Hardware Interface Description Page 71 of 129 3.2 Power Up/Power Down Scenarios 89 3.2.4 Turn off PLSx3 To switch the module off the following procedures may be used: • Software controlled shutdown procedure: Software controlled by sending an AT command over the serial application interface. See Section 3.2.4.1 • Hardware controlled shutdown procedure: Hardware controlled by setting the FST_SHDN line to low. See Section 2.1.10.
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Cinterion® PLSx3 Hardware Interface Description Page 72 of 129 3.2 Power Up/Power Down Scenarios 89 factory setting AT^SCTM=0 was never changed. The maximum temperature ratings are stated in Section 3.6. Refer to Table 17 for the associated URCs. Table 17: Temperature associated URCs Sending temperature alert (2min after PLSx3 start-up, otherwise only if URC presentation enabled) ^SCTM_B: 1 Board close to overtemperature limit. ^SCTM_B: -1 Board close to undertemperature limit.
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Cinterion® PLSx3 Hardware Interface Description Page 73 of 129 3.2 Power Up/Power Down Scenarios 89 3.2.5.2 Undervoltage Shutdown The undervoltage shutdown threshold is the specified minimum supply voltage VBATT+ given in Table 3. When the average supply voltage measured by PLSx3 approaches the undervoltage shutdown threshold (i.e., 0.
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Cinterion® PLSx3 Hardware Interface Description Page 74 of 129 3.3 Power Saving 89 3.2.5.4 Deferred Shutdown at Extreme Temperature Condition In the following cases, automatic shutdown will be deferred if a critical temperature limit is exceeded: • While an emergency call is in progress. • During a two minute guard period after power-up. This guard period has been introduced in order to allow for the user to make an emergency call.
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Cinterion® PLSx3 Hardware Interface Description Page 75 of 129 3.3 Power Saving 89 Now, a paging timing cycle consists of the actual fixed length paging plus a variable length pause before the next paging. In the pauses between listening to paging messages, the module resumes power saving, as shown in Figure 28. Figure 28: Power saving and paging in GSM networks The varying pauses explain the different potential for power saving. The longer the pause the less power is consumed.
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Cinterion® PLSx3 Hardware Interface Description Page 76 of 129 3.3 Power Saving 89 Generally, power saving depends on the module’s application scenario and may differ from the above mentioned normal operation. The power saving interval may be shorter than 0.64 seconds or longer than 5.12 seconds. 3.3.3 Power Saving while Attached to LTE Networks The power saving possibilities while attached to an LTE network depend on the paging timing cycle of the base station. During normal LTE operation, i.e.
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Cinterion® PLSx3 Hardware Interface Description Page 77 of 129 3.3 Power Saving 89 3.3.4 Wake-up via RTS0 RTS0 can be used to wake up PLSx3 from SLEEP mode configured with AT^SPOW. Assertion of RTS0 (i.e., toggle from inactive high to active low) serves as wake up event, thus allowing an external application to almost immediately terminate power saving. After RTS0 assertion, the CTS0 line signals module wake up, i.e., readiness of the AT command interface.
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Cinterion® PLSx3 Hardware Interface Description Page 78 of 129 3.4 Power Supply 89 3.4 Power Supply PLSx3 needs to be connected to a power supply at the SMT application interface - 4 lines BATT+, and GND. There are two separate voltage domains for BATT+: • BATT+BB with two lines for the general power management. • BATT+RF with two lines for the RF. Please note that throughout the document BATT+ refers to both voltage domains and power supply lines - BATT+BB and BATT+RF.
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Cinterion® PLSx3 Hardware Interface Description Page 79 of 129 3.4 Power Supply 89 3.4.1 Power Supply Ratings The tables in this section assemble various voltage supply and current consumption ratings of the module. Table 18: Supply Ratings BATT+ Description Conditions Supply voltage 3.0 Normal Range (Directly measured at Module. Voltage must stay within the min/max values, including voltage drop, ripple, spikes.) The module shall work with supply voltages between 3.0 and 4.
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Cinterion® PLSx3 Hardware Interface Description Page 80 of 129 3.4 Power Supply 89 Table 19: Current Consumption Ratings -GSM1 IBATT+2 (i.e., sum of BATT+BB and BATT+RF) Description Conditions GSM SLEEP State supply current SLEEP3 @ DRX=9 (no communication via UART) USB disconnected 2.365 mA USB suspended 2.690 mA SLEEP3 @ DRX=5 (no communication via UART) USB disconnected 2.534 mA USB suspended 2.839 mA SLEEP3 @ DRX=2 (no communication via UART) USB disconnected 2.
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Cinterion® PLSx3 Hardware Interface Description Page 81 of 129 3.4 Power Supply 89 Table 19: Current Consumption Ratings -GSM1 IBATT+2 (i.e., sum of BATT+BB and BATT+RF) Description Conditions Average GSM900 supply current5 GPRS Data transfer GSM900; PCL=5; 1Tx/4Rx ROPR=8 (max. reduction) 307 mA ROPR=4 (no reduction) 307 mA GPRS Data transfer GSM900; PCL=5; 2Tx/3Rx ROPR=8 (max. reduction) 446 mA ROPR=4 (no reduction) 554 mA GPRS Data transfer GSM900; PCL=5; 4Tx/1Rx ROPR=8 (max.
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Cinterion® PLSx3 Hardware Interface Description Page 82 of 129 3.4 Power Supply 89 Table 19: Current Consumption Ratings -GSM1 IBATT+2 (i.e., sum of BATT+BB and BATT+RF) Description Conditions Average GSM1800 supply current5 GPRS Data transfer GSM1800; PCL=0; 1Tx/4Rx ROPR=8 (max. reduction) 209 mA ROPR=4 (no reduction) 209 mA GPRS Data transfer GSM1800; PCL=0; 2Tx/3Rx ROPR=8 (max. reduction) 295 mA ROPR=4 (no reduction) 359 mA GPRS Data transfer GSM1800; PCL=0; 4Tx/1Rx ROPR=8 (max.
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Cinterion® PLSx3 Hardware Interface Description Page 83 of 129 3.4 Power Supply 89 Table 19: Current Consumption Ratings -GSM1 IBATT+2 (i.e., sum of BATT+BB and BATT+RF) Description Conditions Average GSM1900 supply current5 GPRS Data transfer GSM1900; PCL=0; 1Tx/4Rx ROPR=8 (max. reduction) 210 mA ROPR=4 (no reduction) 208 mA GPRS Data transfer GSM1900; PCL=0; 2Tx/3Rx ROPR=8 (max. reduction) 295 mA ROPR=4 (no reduction) 358 mA GPRS Data transfer GSM1900; PCL=0; 4Tx/1Rx ROPR=8 (max.
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Cinterion® PLSx3 Hardware Interface Description Page 84 of 129 3.4 Power Supply 89 3. Measurements start 6 minutes after switching ON the module, averaging times: SLEEP mode – 3 minutes, transfer modes – 1.5 minutes Communication tester settings:no neighbor cells, no cell reselection etc., RMC (Reference Measurement Channel) SLEEP mode is enabled via AT command AT^SPOW=2, 1000, 3 4. The power save mode is disabled via AT command AT^SPOW=1,0,0 5.
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Cinterion® PLSx3 Hardware Interface Description Page 85 of 129 3.4 Power Supply 89 Table 20: Current Consumption Ratings - UMTS1 Description IBATT+2 (i.e., sum of BATT+BB and BATT+RF) Conditions Typical rating (W,EP,L A,J,I) Typical rating (X, X2, X3, X4) Unit UMTS SLEEP State SLEEP3 @ DRX=9 supply current (no communication via UART) USB disconnected 2.336 mA USB suspended 2.698 mA SLEEP3 @ DRX=8 (no communication via UART) USB disconnected 2.431 mA USB suspended 2.
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Cinterion® PLSx3 Hardware Interface Description Page 86 of 129 3.4 Power Supply 89 Table 21: Current Consumption Ratings - LTE1 IBATT+2 (i.e., sum of BATT+ BB and BATT+ RF) Description Conditions Typical rating (W,EP, LA,J,I) LTE SLEEP State supply current SLEEP3 @ “Paging Cycles = USB disconnected 256” (no communication via UART) USB suspended 2.496 mA 2.793 mA SLEEP3 @ “Paging Cycles = USB disconnected 128” (no communication via UART) USB suspended 2.740 mA 3.
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Cinterion® PLSx3 Hardware Interface Description Page 87 of 129 3.4 Power Supply 89 1. Note: Current consumption ratings are based on measurements done in a laboratory test environment, and deviations may occur from the given typical ratings. Under real life conditions however, with e.g., varying network quality, location changes, or changing supply currents, the deviations from these typical ratings may be even bigger, and will have to be taken into account for actual power supply solutions.
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Cinterion® PLSx3 Hardware Interface Description Page 88 of 129 3.5 Operating Temperatures 89 3.5 Operating Temperatures Table 22: Board Temperature Parameter Min Operating temperature range 1 Restricted temperature range Typ Max Unit -30 +85 °C -40 +95 °C +95 °C Automatic shutdown2 <-40 Temperature measured on PLSx3 board 1. Restricted operation allows normal mode data transmissions for limited time until automatic thermal shutdown takes effect.
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Cinterion® PLSx3 Hardware Interface Description Page 89 of 129 3.7 Reliability Characteristics 89 3.7 Reliability Characteristics The test conditions stated below are an extract of the complete test specifications.
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Cinterion® PLSx3 Hardware Interface Description Page 90 of 129 4 Mechanical Dimensions, Mounting and Packaging 105 4 Mechanical Dimensions, Mounting and Packaging 4.1 Mechanical Dimensions of PLSx3 Figure 34 shows the top and bottom view of PLSx3 and provides an overview of the board's mechanical dimensions. For further details see Figure 35. Top view Bottom View Figure 34: PLSx3– top and bottom view t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 91 of 129 4.1 Mechanical Dimensions of PLSx3 105 Top view Figure 35: Dimensions of PLSx3 (all dimensions in mm) t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 92 of 129 4.1 Mechanical Dimensions of PLSx3 105 Figure 36: Dimensions of PLSx3 (keepout area recommended) t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 93 of 129 4.2 Mounting PLSx3 onto the Application Platform 105 4.2 Mounting PLSx3 onto the Application Platform This section describes how to mount PLSx3 onto the PCBs, including land pattern and stencil design, board-level characterization, soldering conditions, durability and mechanical handling.
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Cinterion® PLSx3 Hardware Interface Description Page 94 of 129 4.2 Mounting PLSx3 onto the Application Platform 105 Figure 38: Recommended design for 110 micron thick stencil (top view) Figure 39: Recommended design for 150 micron thick stencil (top view) t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 95 of 129 4.2 Mounting PLSx3 onto the Application Platform 105 4.2.1.2 Board Level Characterization Board level characterization issues should also be taken into account if devising an SMT process. Characterization tests should attempt to optimize the SMT process with regard to board level reliability.
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Cinterion® PLSx3 Hardware Interface Description Page 96 of 129 4.2 Mounting PLSx3 onto the Application Platform 105 4.2.3 Soldering Conditions and Temperature 4.2.3.
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Cinterion® PLSx3 Hardware Interface Description Page 97 of 129 4.2 Mounting PLSx3 onto the Application Platform 105 2. Temperatures measured on shielding at each corner. See also [3]. 1 Module 3 2 4 Temperature sensors (1-4) 4.2.3.2 Maximum Temperature and Duration The following limits are recommended for the SMT board-level soldering process to attach the module: • A maximum module temperature of 245°C. This specifies the temperature as measured at the module’s top side.
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Cinterion® PLSx3 Hardware Interface Description Page 98 of 129 4.2 Mounting PLSx3 onto the Application Platform 105 4.2.4 Durability and Mechanical Handling 4.2.4.1 Storage Conditions PLSx3 modules, as delivered in tape and reel carriers, must be stored in sealed, moisture barrier anti-static bags. The conditions stated below are only valid for modules in their original packed state in weather protected, non-temperature-controlled storage locations.
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Cinterion® PLSx3 Hardware Interface Description Page 99 of 129 4.2 Mounting PLSx3 onto the Application Platform 105 4.2.4.2 Processing Life PLSx3 must be soldered to an application within 72 hours after opening the moisture barrier bag (MBB) it was stored in. As specified in the IPC/JEDEC J-STD-033 Standard, the manufacturing site processing the modules should have ambient temperatures below 30°C and a relative humidity below 60%. 4.2.4.
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Cinterion® PLSx3 Hardware Interface Description Page 100 of 129 4.3 Packaging 105 4.3 Packaging 4.3.1 Tape and Reel The single-feed tape carrier for PLSx3 is illustrated in Figure 41. The figure also shows the proper part orientation. The tape width is 44mm and the PLSx3 modules are placed on the tape with a 40mm pitch. The reels are 330mm in diameter with 100mm hubs. Each reel contains 400 modules. 4.3.1.1 Orientation Figure 41: Carrier tape Figure 42: Reel direction t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 101 of 129 4.3 Packaging 105 4.3.1.2 Barcode Label A barcode label provides detailed information on the tape and its contents. It is attached to the reel. Barcode label Figure 43: Barcode label on tape reel Figure 44: Barcode label on tape reel - layout Variables on the label are explained in Table 27. t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 102 of 129 4.3 Packaging 105 4.3.2 Shipping Materials PLSx3 is distributed in tape and reel carriers. The tape and reel carriers used to distribute PLSx3 are packed as described below, including the following required shipping materials: • Moisture barrier bag, including desiccant and humidity indicator card • Transportation box 4.3.2.
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Cinterion® PLSx3 Hardware Interface Description Page 103 of 129 4.3 Packaging 105 Figure 46: Moisture Sensitivity Label t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 104 of 129 4.3 Packaging 105 MBBs contain one or more desiccant pouches to absorb moisture that may be in the bag. The humidity indicator card described below should be used to determine whether the enclosed components have absorbed an excessive amount of moisture. The desiccant pouches should not be baked or reused once removed from the MBB.
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Cinterion® PLSx3 Hardware Interface Description Page 105 of 129 4.3 Packaging 105 4.3.2.2 Transportation Box Tape and reel carriers are distributed in a box, marked with a barcode label for identification purposes. A box contains two reels with 400 (TBD for -X variant) modules each. 1 2 3 4 5 8 6 9 7 10 11 12 14 13 Figure 48: Sample of VP box label Table 27: VP Box label information No.
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Cinterion® PLSx3 Hardware Interface Description Page 106 of 129 5 Regulatory and Type Approval Information 117 5 Regulatory and Type Approval Information 5.1 Directives and Standards PLSx3 is designed to comply with the directives and standards listed below.
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Cinterion® PLSx3 Hardware Interface Description Page 107 of 129 5.1 Directives and Standards 117 Table 30: Standards of European type approval 3GPP TS 51.010-1 Digital cellular telecommunications system (Release 7); Mobile Station (MS) conformance specification; GCF-CC V3.79 Global Certification Forum - Certification Criteria ETSI EN 301 511 V12.5.1 Global System for Mobile communications (GSM); Mobile Stations (MS) equipment; Harmonized Standard covering the essential requirements of article 3.
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Cinterion® PLSx3 Hardware Interface Description Page 108 of 129 5.1 Directives and Standards 117 Table 32: Standards of the Ministry of Information Industry of the People’s Republic of China SJ/T 11364-2006 “Marking for Control of Pollution Caused by Electronic Information Products” (2006-06). According to the “Chinese Administration on the Control of Pollution caused by Electronic Information Products” (ACPEIP) the EPUP, i.e.
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Cinterion® PLSx3 Hardware Interface Description Page 109 of 129 5.1 Directives and Standards 117 5.1.1 IEC 62368-1 Classification With respect to the safety requirements for audio/video, information and communication technology equipment defined by the hazard based product safety standard for ICT and AV equipment - i.e., IEC-62368-1 (EN 62368-1, UL 62368-1) - Cinterion® modules are classified as shown below: Standalone operation of the modules is not possible.
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Cinterion® PLSx3 Hardware Interface Description Page 110 of 129 5.1 Directives and Standards 117 Table 34: IEC 62368-1 Classification Source of Energy Class Limits Hazardous Substances, Chemical reaction - Under regular conditions, the Cinterion® modules does not contain any chemically reactive substances, and no chemical energy source, especially no battery. Module is compliant with RoHS and REACH. In very rare cases however - under abnormal conditions 9i.e.
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Cinterion® PLSx3 Hardware Interface Description Page 111 of 129 5.2 SAR requirements specific to portable mobiles 117 5.2 SAR requirements specific to portable mobiles Mobile phones, PDAs or other portable transmitters and receivers incorporating a GSM/UMTS module must be in accordance with the guidelines for human exposure to radio frequency energy.
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Cinterion® PLSx3 Hardware Interface Description Page 112 of 129 5.3 Reference Equipment for Type Approval 117 5.
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Cinterion® PLSx3 Hardware Interface Description Page 113 of 129 5.4 Compliance with FCC and ISED Rules and Regulations 117 5.4 Compliance with FCC and ISED Rules and Regulations The Equipment Authorization Certification for the Thales reference application described in Section 5.
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Cinterion® PLSx3 Hardware Interface Description Page 114 of 129 5.4 Compliance with FCC and ISED Rules and Regulations 117 tains FCC ID: QIPPLS63-X4”, "Contains FCC ID: QIPPLS83-X4”, and accordingly “Contains IC: 7830A-PLS63W“, “Contains IC: 7830A-PLS83W“, “Contains IC: 7830A-PLS63X“, “Contains IC: 7830A-PLS83X“, “Contains IC: 7830A-PLS63X2“, “Contains IC: 7830A-PLS83X2“, “Contains IC: 7830A-PLS63X3“, “Contains IC: 7830A-PLS83X3“, “Contains IC: 7830A-PLS63X4“, “Contains IC: 7830A-PLS83X4“.
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Cinterion® PLSx3 Hardware Interface Description Page 115 of 129 5.4 Compliance with FCC and ISED Rules and Regulations 117 Table 36: Antenna gain limits for FCC and ISED (for X, X2, X3, X4 variants) Operation band FCC limit ISED limit Unit Maximum gain in LTE Band 25 8.01 8.01 dBi Maximum gain in LTE Band 26 9.30 6.10 dBi Maximum gain in LTE Band 66 5.00 5.00 dBi Maximum gain in LTE Band 71 8.48 5.
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Cinterion® PLSx3 Hardware Interface Description Page 116 of 129 5.4 Compliance with FCC and ISED Rules and Regulations 117 Notes (ISED): (EN) This Class B digital apparatus complies with Canadian ICES-003 and RSS-210. Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.
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Cinterion® PLSx3 Hardware Interface Description Page 117 of 129 5.5 Compliance with Japanese Rules and Regulations 117 5.5 Compliance with Japanese Rules and Regulations The PLSx3 reference application described in Section 5.
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Cinterion® PLSx3 Hardware Interface Description Page 118 of 129 6 Document Information 125 6 Document Information 6.1 Revision History Proceeding document: "Cinterion® PLSx3-W Hardware Interface Description" Version 01.002c New document: "Cinterion® PLSx3 Hardware Interface Description" Version 01.002d Chapter What is new 2.1.2 Updated CCIN to CCIN1 and CCIN2. 2.4 Updated Figure 26. 3.4 Updated Figure 32. 5.4 Added LET Band8 in Table 35.
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Cinterion® PLSx3 Hardware Interface Description Page 119 of 129 6.1 Revision History 125 Proceeding document: "Cinterion® PLSx3-W Hardware Interface Description" Version 01.002 New document: "Cinterion® PLSx3 Hardware Interface Description" Version 01.002a Chapter What is new 1.2.1 Added a note to Table 1. 2.2 Updated Table 12. 2.2.3.2 Updated Figure 23. 2.1.2 3.2.2.2 Updated the low level impulse. 3.2.3 Updated Table 16 and added a note. 5.1 Added 1907/2006/EC (REACH) in Table 28. 5.1.
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Cinterion® PLSx3 Hardware Interface Description Page 120 of 129 6.1 Revision History 125 3.6 Added Electrostatic Discharge section. 4.3.1.2 Added Figure 44. 4.3.2.2 Added Figure 48 and Table 27. 5 Added chapter 6 Regulatory and Type Approval Information. 7.2 Added Module Label Information section. 3.2.1 Updated Figure 27 and the description of IGT signal. 2.1.2 Updated Ignition signal description in Table 3. Proceeding document: "Cinterion® PLSx3-W Hardware Interface Description" Version 00.
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Cinterion® PLSx3 Hardware Interface Description Page 121 of 129 6.1 Revision History 125 New document: "Cinterion® PLSx3-W Hardware Interface Description" Version 00.001 Chapter What is new -- Initial document setup. t PLSx3_HID_v01.
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Cinterion® PLSx3 Hardware Interface Description Page 122 of 129 6.2 Related Documents 125 6.2 [1] [2] [3] [4] [5] Related Documents PLSx3 AT Command Set PLSx3 Release Note Universal Serial Bus Specification Revision 2.0, April 27, 2000 Application Note 48: SMT Module Integration Differences between Selected Cinterion® Modules, Hardware Migration Guide 6.
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Cinterion® PLSx3 Hardware Interface Description Page 123 of 129 6.3 Terms and Abbreviations 125 Abbreviation Description EIRP Equivalent Isotropic Radiated Power EMC Electromagnetic Compatibility ERP Effective Radiated Power ESD Electrostatic Discharge ETS European Telecommunication Standard ETSI European Telecommunication Standards Institute FCC Federal Communications Commission (U.S.
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Cinterion® PLSx3 Hardware Interface Description Page 124 of 129 6.
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Cinterion® PLSx3 Hardware Interface Description Page 125 of 129 6.4 Safety Precaution Notes 125 6.4 Safety Precaution Notes The following safety precautions must be observed during all phases of the operation, usage, service or repair of any cellular terminal or mobile incorporating PLSx3. Manufacturers of the cellular terminal are advised to convey the following safety information to users and operating personnel and to incorporate these guidelines into all manuals supplied with the product.
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Cinterion® PLSx3 Hardware Interface Description Page 125 of 129 7 Appendix 7 Appendix 7.
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Cinterion® PLSx3 Hardware Interface Description Page 126 of 129 7.
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Cinterion® PLSx3 Hardware Interface Description Page 127 of 129 7.
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Cinterion® PLSx3 Hardware Interface Description Page 128 of 129 7.2 Module Label Information 7.2 Module Label Information The label engraved on the top of PLSx3 comprises the following information. 1 5 4 2 3 6 8 7 Figure 52: PLSx3 Label Table 39: PLSx3 label information No. 1 Cinterion logo 2 Manufacturing country (e.g., “Made in China”) 3 Factory Code 4 Product name/variant (e.g.
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