Cinterion® PLS62-W Hardware Interface Overview Version: DocId: 02.010a PLS62-W_hio_v02.
Cinterion® PLS62-W Hardware Interface Overview Page 2 of 50 2 Document Name: Cinterion® PLS62-W Hardware Interface Overview Version: 02.010a Date: 2020-08-18 DocId: PLS62-W_hio_v02.010a Status Public / Released GENERAL NOTE THIS DOCUMENT CONTAINS INFORMATION ON THALES PRODUCTS. THALES RESERVES THE RIGHT TO MAKE CHANGES TO THE PRODUCTS DESCRIBED HEREIN. THE SPECIFICATIONS IN THIS DOCUMENT ARE SUBJECT TO CHANGE AT THE DISCRETION OF THALES.
Cinterion® PLS62-W Hardware Interface Overview Page 3 of 50 Contents 50 Contents 1 Introduction ................................................................................................................. 7 1.1 Key Features at a Glance .................................................................................. 7 1.2 PLS62-W System Overview............................................................................. 11 2 Interface Characteristics ............................................
Cinterion® PLS62-W Hardware Interface Overview Page 4 of 50 Contents 50 6 Document Information.............................................................................................. 43 6.1 Revision History ............................................................................................... 43 6.2 Related Documents ......................................................................................... 43 6.3 Terms and Abbreviations .....................................................
Cinterion® PLS62-W Hardware Interface Overview Page 5 of 50 Tables 50 Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: t Signals of the SIM interface (SMT application interface) ............................... GPIO lines and possible alternative assignment............................................ Return loss in the active band........................................................................ Directives .............
Cinterion® PLS62-W Hardware Interface Overview Page 6 of 50 Figures 50 Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: t PLS62-W system overview ............................................................................ USB circuit ..................................................................................................... Serial interface ASC0.
Cinterion® PLS62-W Hardware Interface Overview Page 7 of 50 1 Introduction 11 1 Introduction This document1 describes the hardware of the Cinterion® PLS62-W module. It helps you quickly retrieve interface specifications, electrical and mechanical details and information on the requirements to be considered for integrating further components. 1.
Cinterion® PLS62-W Hardware Interface Overview Page 8 of 50 1.1 Key Features at a Glance 11 Feature Implementation Operating temperature (board temperature) Normal operation: -30°C to +85°C Extended operation: -40°C to +90°C Physical Dimensions: 33mm x 29mm x 3.06mm Weight: approx. 5g RoHS All hardware components fully compliant with EU RoHS Directive LTE features 3GPP Release 9 UE CAT 1 supported DL 10.2Mbps, UL 5.2Mbps HSPA features 3GPP Release 8 DL 7.2Mbps, UL 5.7Mbps HSDPA Cat.
Cinterion® PLS62-W Hardware Interface Overview Page 9 of 50 1.1 Key Features at a Glance 11 Feature Implementation Java™ Open Platform Java™ Open Platform with • Java™ profile IMP-NG & CLDC 1.
Cinterion® PLS62-W Hardware Interface Overview Page 10 of 50 1.
Cinterion® PLS62-W Hardware Interface Overview Page 11 of 50 1.2 PLS62-W System Overview 11 1.
Cinterion® PLS62-W Hardware Interface Overview Page 12 of 50 2 Interface Characteristics 29 2 Interface Characteristics PLS62-W is equipped with an SMT application interface that connects to the external application. The SMT application interface incorporates the various application interfaces as well as the RF antenna interface. 2.1 Application Interface 2.1.1 USB Interface PLS62-W supports a USB 2.0 High Speed (480Mbit/s) device interface that is Full Speed (12Mbit/s) compliant.
Cinterion® PLS62-W Hardware Interface Overview Page 13 of 50 2.1 Application Interface 29 2.1.2 Serial Interface ASC0 PLS62-W offers an 8-wire unbalanced, asynchronous modem interface ASC0 conforming to ITU-T V.24 protocol DCE signalling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state). PLS62-W is designed for use as a DCE.
Cinterion® PLS62-W Hardware Interface Overview Page 14 of 50 2.1 Application Interface 29 2.1.3 Serial Interface ASC1 Four PLS62-W GPIO lines can be configured as ASC1 interface signals to provide a 4-wire unbalanced, asynchronous modem interface ASC1 conforming to ITU-T V.24 protocol DCE signalling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state).
Cinterion® PLS62-W Hardware Interface Overview Page 15 of 50 2.1 Application Interface 29 2.1.4 UICC/SIM/USIM Interface PLS62-W has two UICC/SIM/USIM interfaces compatible with the 3GPP 31.102 and ETSI 102 221. These are wired to the host interface in order to be connected to an external SIM card holder. Five pads on the SMT application interface are reserved for each of the two SIM interfaces. The UICC/SIM/USIM interface supports 3V and 1.8V SIM cards.
Cinterion® PLS62-W Hardware Interface Overview Page 16 of 50 2.
Cinterion® PLS62-W Hardware Interface Overview Page 17 of 50 2.1 Application Interface 29 2.1.4.1 SIM_SWITCH Line As an alternative to connecting the module’s two SIM interfaces and switching between these interfaces by means of AT command, it is possible to connect the first of the module’s SIM interfaces via an external SIM switch that in turn provides access to a further SIM interface.
Cinterion® PLS62-W Hardware Interface Overview Page 18 of 50 2.1 Application Interface 29 2.1.5 GPIO Interface PLS62-W offers a GPIO interface with 24 GPIO lines. The GPIO lines are shared with other interfaces or functions: Fast shutdown (see Section 2.1.11), status LED (see Section 2.1.10), the PWM functionality (see Section 2.1.8), an pulse counter (see Section 2.1.9), ASC0 (see Section 2.1.2), ASC1 (see Section 2.1.3), an SPI interface (see Section 2.1.7).
Cinterion® PLS62-W Hardware Interface Overview Page 19 of 50 2.1 Application Interface 29 2.1.6 I2C Interface I2C is a serial, 8-bit oriented data transfer bus for bit rates up to 400kbps in Fast mode. It consists of two lines, the serial data line I2CDAT and the serial clock line I2CCLK. The module acts as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-directional line.
Cinterion® PLS62-W Hardware Interface Overview Page 20 of 50 2.1 Application Interface 29 2.1.11 Fast Shutdown The GPIO4 interface line can be configured as fast shutdown signal line FST_SHDN. The configured FST_SHDN line is an active low control signal and must be applied for at least 1 milliseconds. If unused this line can be left open because of a configured internal pull-up resistor. 2.1.
Cinterion® PLS62-W Hardware Interface Overview Page 21 of 50 2.2 RF Antenna Interface 29 2.2 RF Antenna Interface The PLS62-W GSM/UMTS/LTE antenna interface comprises a GSM/UMTS/LTE main antenna as well as a UMTS/LTE Rx diversity antenna to improve signal reliability and quality1. The RF interface has an impedance of 50Ω. PLS62-W is capable of sustaining a total mismatch at the antenna line without any damage, even when transmitting at maximum RF power.
Cinterion® PLS62-W Hardware Interface Overview Page 22 of 50 2.2 RF Antenna Interface 29 2.2.1 Antenna Installation The antenna is connected by soldering the antenna pads (ANT_MAIN and ANT_DRX) and their neighboring ground pads directly to the application’s PCB. The distance between the antenna pads and their neighboring GND pads has been optimized for best possible impedance. To prevent mismatch, special attention should be paid to these pads on the application’ PCB.
Cinterion® PLS62-W Hardware Interface Overview Page 23 of 50 2.2 RF Antenna Interface 29 Micro-Stripline This section gives two line arrangement examples for micro-stripline. • Micro-Stripline on 1.0mm Standard FR4 2-Layer PCB The following two figures show examples with different values for D1 (ground strip separation). Application board Ground line Antenna line Ground line Figure 9: Micro-Stripline on 1.0mm standard FR4 2-layer PCB - example 1 t PLS62-W_hio_v02.
Cinterion® PLS62-W Hardware Interface Overview Page 24 of 50 2.2 RF Antenna Interface 29 Application board Ground line Antenna line Ground line Figure 10: Micro-Stripline on 1.0mm Standard FR4 PCB - example 2 t PLS62-W_hio_v02.
Cinterion® PLS62-W Hardware Interface Overview Page 25 of 50 2.2 RF Antenna Interface 29 • Micro-Stripline on 1.5mm Standard FR4 2-Layer PCB The following two figures show examples with different values for D1 (ground strip separation). Application board Ground line Antenna line Ground line Figure 11: Micro-Stripline on 1.5mm Standard FR4 PCB - example 1 t PLS62-W_hio_v02.
Cinterion® PLS62-W Hardware Interface Overview Page 26 of 50 2.2 RF Antenna Interface 29 Application board Ground line Antenna line Ground line Figure 12: Micro-Stripline on 1.5mm Standard FR4 PCB - example 2 t PLS62-W_hio_v02.
Cinterion® PLS62-W Hardware Interface Overview Page 27 of 50 2.2 RF Antenna Interface 29 2.2.2.2 Routing Example Interface to RF Connector Figure 13 shows a sample connection of a module‘s antenna pad at the bottom layer of the module PCB with an application PCB‘s coaxial antenna connector. Line impedance depends on line width, but also on other PCB characteristics like dielectric, height and layer gap. The sample stripline width of 0.
Cinterion® PLS62-W Hardware Interface Overview Page 28 of 50 2.3 Sample Application 29 2.3 Sample Application Figure 15 shows a typical example of how to integrate a PLS62-W module with an application. Usage of the various host interfaces depends on the desired features of the application. Because of the very low power consumption design, current flowing from any other source into the module circuit must be avoided, for example reverse current from high state external control lines.
Cinterion® PLS62-W Hardware Interface Overview Page 29 of 50 2.3 Sample Application 29 Main antenna GND VDDLP ANT_MAIN VDDLP GND 100k IGT IGT Diversity antenna GND ANT_DRX VDDLP GND 10k 1k EMERG_OFF EMERG_OFF 1nF V180 V180 BATT+RF E.g., VBATT BATT+BB 150µF, Low ESR! 53 BEAD* 204 Power supply E.g., 100k 150µF, Low ESR! PWR_IND BEAD*: It is recommended to add the BEAD as shown to theBATT+BB line. The purpose of this is to mitigate noise from baseband power supply.
Cinterion® PLS62-W Hardware Interface Overview Page 30 of 50 3 Operating Characteristics 31 3 Operating Characteristics 3.1 Operating Modes The table below briefly summarizes the various operating modes referred to throughout the document. Mode Function Normal GSM / operation GPRS / UMTS / HSPA / LTE SLEEP Power saving set automatically when no call is in progress and the USB connection is suspended by host or not present and no active communication via ASC0.
Cinterion® PLS62-W Hardware Interface Overview Page 31 of 50 3.2 Power Supply 31 3.2 Power Supply PLS62-W needs to be connected to a power supply at the SMT application interface - 4 lines BATT+, and GND. There are two separate voltage domains for BATT+: • BATT+BB with two lines for the general power management. • BATT+RF with four lines for the GSM power amplifier supply. Please note that throughout the document BATT+ refers to both voltage domains and power supply lines - BATT+BB and BATT+RF.
Cinterion® PLS62-W Hardware Interface Overview Page 32 of 50 4 Mechanical Dimensions, Mounting and Packaging 33 4 Mechanical Dimensions, Mounting and Packaging 4.1 Mechanical Dimensions of PLS62-W Figure 16 shows the top and bottom view of PLS62-W and provides an overview of the board's mechanical dimensions. For further details see Figure 17. Top view Bottom view Figure 16: PLS62-W– top and bottom view t PLS62-W_hio_v02.
Cinterion® PLS62-W Hardware Interface Overview Page 33 of 50 4.1 Mechanical Dimensions of PLS62-W 33 Top view Figure 17: Dimensions of PLS62-W (all dimensions in mm) t PLS62-W_hio_v02.
Cinterion® PLS62-W Hardware Interface Overview Page 34 of 50 5 Regulatory and Type Approval Information 42 5 Regulatory and Type Approval Information 5.1 Directives and Standards PLS62-W is designed to comply with the directives and standards listed below.
Cinterion® PLS62-W Hardware Interface Overview Page 35 of 50 5.1 Directives and Standards 42 Table 6: Standards of European type approval Draft ETSI EN 301 48901 V2.2.0 Electromagnetic Compatibility (EMC) standard for radio equipment and services; Part 1: Common technical requirements; Harmonized Standard covering the essential requirements of article 3.
Cinterion® PLS62-W Hardware Interface Overview Page 36 of 50 5.1 Directives and Standards 42 Table 9: Standards of the Ministry of Information Industry of the People’s Republic of China SJ/T 11363-2006 “Requirements for Concentration Limits for Certain Hazardous Substances in Electronic Information Products” (2006-06). SJ/T 11364-2006 “Marking for Control of Pollution Caused by Electronic Information Products” (2006-06).
Cinterion® PLS62-W Hardware Interface Overview Page 37 of 50 5.2 SAR requirements specific to portable mobiles 42 5.2 SAR requirements specific to portable mobiles Mobile phones, PDAs or other portable transmitters and receivers incorporating a GSM/UMTS module must be in accordance with the guidelines for human exposure to radio frequency energy.
Cinterion® PLS62-W Hardware Interface Overview Page 38 of 50 5.3 Reference Equipment for Type Approval 42 5.
Cinterion® PLS62-W Hardware Interface Overview Page 39 of 50 5.4 Compliance with FCC and ISED Rules and Regulations 42 5.4 Compliance with FCC and ISED Rules and Regulations The Equipment Authorization Certification for the Thales reference application described in Section 5.
Cinterion® PLS62-W Hardware Interface Overview Page 40 of 50 5.4 Compliance with FCC and ISED Rules and Regulations 42 IMPORTANT: Manufacturers of portable applications incorporating PLS62-W modules are required to have their final product certified and apply for their own FCC Grant related to the specific portable mobile. This is mandatory to meet the SAR requirements for portable mobiles (see Section 5.2 for detail).
Cinterion® PLS62-W Hardware Interface Overview Page 41 of 50 5.4 Compliance with FCC and ISED Rules and Regulations 42 Notes (ISED): (EN) This Class B digital apparatus complies with Canadian ICES-003 and RSS-210. Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.
Cinterion® PLS62-W Hardware Interface Overview Page 42 of 50 5.5 Compliance with Japanese Rules and Regulations 42 5.5 Compliance with Japanese Rules and Regulations The PLS62-W reference application described in Section 5.
Cinterion® PLS62-W Hardware Interface Overview Page 43 of 50 6 Document Information 47 6 Document Information 6.1 Revision History Preceding document: "Cinterion® PLS62-W Hardware Interface Overview" Version 02.000e New document: "Cinterion® PLS62-W Hardware Interface Overview" Version 02.010aa Chapter What is new 5.4 Added new FCC ID Preceding document: "Cinterion® PLS62-W Hardware Interface Overview" Version 00.090 New document: "Cinterion® PLS62-W Hardware Interface Overview" Version 02.
Cinterion® PLS62-W Hardware Interface Overview Page 44 of 50 6.3 Terms and Abbreviations 47 Abbreviation Description AGC Automatic Gain Control ANSI American National Standards Institute ARFCN Absolute Radio Frequency Channel Number ARP Antenna Reference Point ASC0/ASC1 Asynchronous Controller.
Cinterion® PLS62-W Hardware Interface Overview Page 45 of 50 6.
Cinterion® PLS62-W Hardware Interface Overview Page 46 of 50 6.
Cinterion® PLS62-W Hardware Interface Overview Page 47 of 50 6.4 Safety Precaution Notes 47 6.4 Safety Precaution Notes The following safety precautions must be observed during all phases of the operation, usage, service or repair of any cellular terminal or mobile incorporating PLS62-W. Manufacturers of the cellular terminal are advised to convey the following safety information to users and operating personnel and to incorporate these guidelines into all manuals supplied with the product.
Cinterion® PLS62-W Hardware Interface Overview Page 48 of 50 7 Appendix 49 7 Appendix 7.
Cinterion® PLS62-W Hardware Interface Overview Page 49 of 50 7.1 List of Parts and Accessories 49 Table 13: Molex sales contacts (subject to change) Molex For further information please click: http://www.molex.com Molex Deutschland GmbH Otto-Hahn-Str. 1b 69190 Walldorf Germany Phone: +49-6227-3091-0 Fax: +49-6227-3091-8100 Email: mxgermany@molex.com American Headquarters Lisle, Illinois 60532 U.S.A.
THALES DIS AIS Deutschland GmbH Werinherstrasse 81 81541 Munich Germany © Thales 2020. All rights reserved. Thales, the Thales logo, are trademarks and service marks of Thales and are registered in certain countries.
