Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Version: DocId: 04.000 ehs5_hio_v04.000 GEMALTO.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 2 of 46 2 Document Name: Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Version: 04.000 Date: 2019-01-16 DocId: ehs5_hio_v04.000 Status Confidential / Preliminary GENERAL NOTE THE USE OF THE PRODUCT INCLUDING THE SOFTWARE AND DOCUMENTATION (THE "PRODUCT") IS SUBJECT TO THE RELEASE NOTE PROVIDED TOGETHER WITH PRODUCT. IN ANY EVENT THE PROVISIONS OF THE RELEASE NOTE SHALL PREVAIL.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 3 of 46 Contents 46 Contents 1 Introduction ................................................................................................................. 7 1.1 Key Features at a Glance .................................................................................. 7 1.2 EHS5-E/EHS5-USR4 System Overview .......................................................... 11 2 Interface Characteristics ............................................
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 4 of 46 Contents 46 7 Appendix.................................................................................................................... 44 7.1 List of Parts and Accessories........................................................................... 44 ehs5_hio_v04.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 5 of 46 Tables 46 Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Signals of the SIM interface (SMT application interface) ............................... GPIO lines and possible alternative assignment............................................ Return loss in the active band........................................................................
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 6 of 46 Figures 46 Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: EHS5-E/EHS5-USR4 system overview ......................................................... USB circuit ..................................................................................................... Serial interface ASC0...................................
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 7 of 46 1 Introduction 11 1 Introduction This document1 describes the hardware of the Cinterion® EHS5-E/EHS5-USR4 module. It helps you quickly retrieve interface specifications, electrical and mechanical details and information on the requirements to be considered for integrating further components. 1.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 8 of 46 1.1 Key Features at a Glance 11 Feature Implementation HSPA features 3GPP Release 6, 7 DL 7.2Mbps, UL 5.7Mbps HSDPA Cat.8 / HSUPA Cat.6 data rates Compressed mode (CM) supported according to 3GPP TS25.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 9 of 46 1.1 Key Features at a Glance 11 Feature Implementation Java™ Open Platform Java™ Open Platform with • Java™ profile IMP-NG & CLDC 1.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 10 of 46 1.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 11 of 46 1.2 EHS5-E/EHS5-USR4 System Overview 11 1.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 12 of 46 2 Interface Characteristics 28 2 Interface Characteristics EHS5-E/EHS5-USR4 is equipped with an SMT application interface that connects to the external application. The SMT application interface incorporates the various application interfaces as well as the RF antenna interface. 2.1 Application Interface 2.1.1 USB Interface EHS5-E/EHS5-USR4 supports a USB 2.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 13 of 46 2.1 Application Interface 28 2.1.2 Serial Interface ASC0 EHS5-E/EHS5-USR4 offers an 8-wire unbalanced, asynchronous modem interface ASC0 conforming to ITU-T V.24 protocol DCE signalling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state). EHS5-E/EHS5-USR4 is designed for use as a DCE.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 14 of 46 2.1 Application Interface 28 2.1.3 Serial Interface ASC1 EHS5-E/EHS5-USR4 provides a 4-wire unbalanced, asynchronous modem interface ASC1 conforming to ITU-T V.24 protocol DCE signalling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state). The ASC1 interface lines are originally available as GPIO lines.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 15 of 46 2.1 Application Interface 28 2.1.4 UICC/SIM/USIM Interface EHS5-E/EHS5-USR4 has an integrated UICC/SIM/USIM interface compatible with the 3GPP 31.102 and ETSI 102 221. This is wired to the host interface in order to be connected to an external SIM card holder. Five pads on the SMT application interface are reserved for the SIM interface. The UICC/SIM/USIM interface supports 3V and 1.8V SIM cards.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 16 of 46 2.1 Application Interface 28 The figure below shows a circuit to connect an external SIM card holder. V180 CCIN CCVCC SIM 220nF 1nF CCRST CCIO CCCLK Figure 5: External UICC/SIM/USIM card holder circuit The total cable length between the SMT application interface pads on EHS5-E/EHS5-USR4 and the pads of the external SIM card holder must not exceed 100mm in order to meet the specifications of 3GPP TS 51.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 17 of 46 2.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 18 of 46 2.1 Application Interface 28 2.1.8 SPI Interface Four EHS5-E/EHS5-USR4 GPIO interface lines can be configured as Serial Peripheral Interface (SPI). The SPI is a synchronous serial interface for control and data transfer between EHS5E/EHS5-USR4 and the external application. Only one application can be connected to the SPI and the interface supports only master mode. The transmission rates are up to 6.5Mbit/s.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 19 of 46 2.2 RF Antenna Interface 28 2.2 RF Antenna Interface The RF interface has an impedance of 50. EHS5-E/EHS5-USR4 is capable of sustaining a total mismatch at the antenna line without any damage, even when transmitting at maximum RF power. The external antenna must be matched properly to achieve best performance regarding radiated power, modulation accuracy and harmonic suppression.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 20 of 46 2.2 RF Antenna Interface 28 2.2.1 Antenna Installation The antenna is connected by soldering the antenna pad (RF_OUT, i.e., pad #59) and its neighboring ground pads (GND, i.e., pads #58 and #60) directly to the application’s PCB. The antenna pad is the antenna reference point (ARP) for EHS5-E/EHS5-USR4. All RF data specified throughout this document is related to the ARP.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 21 of 46 2.2 RF Antenna Interface 28 Figure 6: Embedded Stripline with 65µm prepreg (1080) and 710µm core ehs5_hio_v04.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 22 of 46 2.2 RF Antenna Interface 28 Micro-Stripline This section gives two line arrangement examples for micro-stripline. • Micro-Stripline on 1.0mm Standard FR4 2-Layer PCB The following two figures show examples with different values for D1 (ground strip separation). Application board Ground line Antenna line Ground line Figure 7: Micro-Stripline on 1.0mm standard FR4 2-layer PCB - example 1 ehs5_hio_v04.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 23 of 46 2.2 RF Antenna Interface 28 Application board Ground line Antenna line Ground line Figure 8: Micro-Stripline on 1.0mm Standard FR4 PCB - example 2 ehs5_hio_v04.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 24 of 46 2.2 RF Antenna Interface 28 • Micro-Stripline on 1.5mm Standard FR4 2-Layer PCB The following two figures show examples with different values for D1 (ground strip separation). Application board Ground line Antenna line Ground line Figure 9: Micro-Stripline on 1.5mm Standard FR4 PCB - example 1 ehs5_hio_v04.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 25 of 46 2.2 RF Antenna Interface 28 Application board Ground line Antenna line Ground line Figure 10: Micro-Stripline on 1.5mm Standard FR4 PCB - example 2 ehs5_hio_v04.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 26 of 46 2.2 RF Antenna Interface 28 2.2.2.2 Routing Example Interface to RF Connector Figure 11 shows the connection of the module‘s antenna pad with an application PCB‘s coaxial antenna connector. Please note that the EHS5-E/EHS5-USR4 bottom plane appears mirrored, since it is viewed from EHS5-E/EHS5-USR4 top side. By definition the top of customer's board shall mate with the bottom of the EHS5-E/EHS5-USR4 module.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 27 of 46 2.3 Sample Application 28 2.3 Sample Application Figure 12 shows a typical example of how to integrate a EHS5-E/EHS5-USR4 module with an application. Usage of the various host interfaces depends on the desired features of the application. Because of the very low power consumption design, current flowing from any other source into the module circuit must be avoided, for example reverse current from high state external control lines.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 28 of 46 2.3 Sample Application 28 VDDLP Main Antenna GND RF OUT AUTO_ON / ON GND EMERG_RST 100k RESET 33pF VDDLP V180 PWR_IND BATT+RF VCORE 22k BATT+BB 53 5 Power supply 100k 150礔 , Low ESR! 4.7k 33pF EHS5 100k Blocking** Blocking** 4 4 8 3 GPIO20...GPIO23/ PCM (DAI) ASC1/ GPIO16...GPIO19/ SPI ASC0 (including GPIO1...
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 29 of 46 3 Operating Characteristics 30 3 Operating Characteristics 3.1 Operating Modes The table below briefly summarizes the various operating modes referred to throughout the document. Table 4: Overview of operating modes Mode Function Normal GSM / operation GPRS / UMTS / HSPA SLEEP No call is in progress and the USB connection is suspended by host (or is not present) and no active communication via ASC0.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 30 of 46 3.2 Power Supply 30 3.2 Power Supply EHS5-E/EHS5-USR4 needs to be connected to a power supply at the SMT application interface - 2 lines BATT+, and GND. There are two separate voltage domains for BATT+: • BATT+BB with a line mainly for the baseband power supply. • BATT+RF with a line for the GSM power amplifier supply.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 31 of 46 4 Mechanics 32 4 Mechanics 4.1 Mechanical Dimensions of EHS5-E/EHS5-USR4 Figure 13 shows the top and bottom view of EHS5-E/EHS5-USR4 and provides an overview of the board's mechanical dimensions. For further details see Figure 14. Product label Top view Bottom view Figure 13: EHS5-E/EHS5-USR4– top and bottom view ehs5_hio_v04.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 32 of 46 4.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 33 of 46 5 Regulatory and Type Approval Information 38 5 Regulatory and Type Approval Information 5.1 Directives and Standards EHS5-E/EHS5-USR4 is designed to comply with the directives and standards listed below.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 34 of 46 5.1 Directives and Standards 38 Table 7: Standards of European type approval1 ETSI EN 301 908-1 V11.1.1 IMT cellular networks; Harmonised Standard covering the essential requirements of article 3.2 of the Directive 2014/53/EU; Part 1: Introduction and common requirements ETSI EN 301 908-2 V11.1.2 IMT cellular networks; Harmonised Standard covering the essential requirements of article 3.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 35 of 46 5.1 Directives and Standards 38 Table 9: Standards of the Ministry of Information Industry of the People’s Republic of China SJ/T 11363-2006 “Requirements for Concentration Limits for Certain Hazardous Substances in Electronic Information Products” (2006-06). SJ/T 11364-2006 “Marking for Control of Pollution Caused by Electronic Information Products” (2006-06).
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 36 of 46 5.2 SAR requirements specific to portable mobiles 38 5.2 SAR requirements specific to portable mobiles Mobile phones, PDAs or other portable transmitters and receivers incorporating a GSM module must be in accordance with the guidelines for human exposure to radio frequency energy.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 37 of 46 5.3 Reference Equipment for Type Approval 38 5.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 38 of 46 5.4 Compliance with FCC and IC Rules and Regulations 38 5.4 Compliance with FCC and IC Rules and Regulations The Equipment Authorization Certification for the Gemalto M2M reference application described in Section 5.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 39 of 46 6 Document Information 43 6 Document Information 6.1 Revision History Preceding document: "EHS5-E/EHS5-US Hardware Interface Overview" Version 03.510 New document: "EHS5-E/EHS5-USR4 Hardware Interface Overview" Version 04.000 Chapter What is new 5.1 Updated Table 7 New document: "EHS5-E/EHS5-USR4 Hardware Interface Overview" Version 03.510 Chapter What is new -- Initial document setup 6.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 40 of 46 6.3 Terms and Abbreviations 43 Abbreviation Description CS Coding Scheme CSD Circuit Switched Data CTS Clear to Send DAC Digital-to-Analog Converter DAI Digital Audio Interface dBm0 Digital level, 3.14dBm0 corresponds to full scale, see ITU G.711, A-law DCE Data Communication Equipment (typically modems, e.g.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 41 of 46 6.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 42 of 46 6.3 Terms and Abbreviations 43 Abbreviation Description SELV Safety Extra Low Voltage SIM Subscriber Identification Module SMD Surface Mount Device SMS Short Message Service SMT Surface Mount Technology SRAM Static Random Access Memory TA Terminal adapter (e.g.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 43 of 46 6.4 Safety Precaution Notes 43 6.4 Safety Precaution Notes The following safety precautions must be observed during all phases of the operation, usage, service or repair of any cellular terminal or mobile incorporating EHS5-E/EHS5-USR4.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 44 of 46 7 Appendix 45 7 Appendix 7.
Cinterion® EHS5-E/EHS5-USR4 Hardware Interface Overview Page 45 of 46 7.1 List of Parts and Accessories 45 Table 12: Molex sales contacts (subject to change) Molex For further information please click: http://www.molex.com Molex Deutschland GmbH Otto-Hahn-Str. 1b 69190 Walldorf Germany Phone: +49-6227-3091-0 Fax: +49-6227-3091-8100 Email: mxgermany@molex.com American Headquarters Lisle, Illinois 60532 U.S.A.
About Gemalto Since 1996, Gemalto has been pioneering groundbreaking M2M and IoT products that keep our customers on the leading edge of innovation. We work closely with global mobile network operators to ensure that Cinterion® modules evolve in sync with wireless networks, providing a seamless migration path to protect your IoT technology investment.
