User Manual

Introduction and Specifications
RVP8 User’s Manual
October 2006
1–2
Open Hardware and Software Design
Compared to previous processors that were built around proprietary DSP chips, perhaps the most
innovative aspect of the RVP8 is that it is implemented on standard PC hardware and software
that can be purchased from a wide variety of sources. The Intel Pentium/PCI approach promises
continued improvement in processor speed, bus bandwidth and the availability of low–cost
compatible hardware and peripherals. The performance of an entry level RVP8 (currently dual
2.4 GHz Pentium processors) is 6 times faster than the fastest RVP7 ever produced (with two
RVP7/AUX boards).
Aside from the open hardware approach, the RVP8 has an open software approach as well. The
RVP8 runs in the context of the Linux operating system. The code is structured and public API’s
are provided so that research customers can modify/replace existing SIGMET algorithms, or
write their own software from scratch using the RVP8 software structure as a foundation on
which to build.
The advantage of the open hardware and software PCI approach is reduced cost and the ability
for customers to maintain, upgrade and expand the processor in the future by purchasing
standard, low cost PC components from local sources.
SoftPlane High–Speed I/O Interconnect
There are potentially many different I/O signals emanating from the backpanel of the RVP8.
Most of these conform to well-known electrical and protocol standards (VGA, SCSI, 10–BaseT,
RS-232 Serial, PS/2 Keyboard, etc.), and can be driven by standard commercial boards that are
available from multiple vendors. However, there are other interface signals such as triggers and
clocks that require careful timing. These precise signals cannot tolerate the PCI bus latency. For
signals that have medium–speed requirements (~1 microsec latency) for which the PCI bus is
inappropriate; and others that require a high–speed (~ 1 ns latency) connection that can only be
achieved with a dedicated wire, the RVP8 Softplane
t provides the solution.
Physically, the Softplanet is a 16-wire digital “daisy-chain” bus that plugs into the tops of the
RVP8/Rx, RVP8/Tx, and I/O boards. The wires connect to the FPGA chips on each card, and the
function of each wire is assigned at run–time based on the connectivity needs of the overall
system. The Softplanet allocates a dedicated wire to carry each high-speed signal; but groups of
medium-speed signals are multiplexed onto single wires in order to conserve resources. Even
though there are only 16 wires available, the Softplane is able to carry several high-speed signals
and hundreds of medium–speed signals, as long as the total bandwidth does not exceed about
600MBits/sec.
The Softplanet I/O is configured at run–time based on a file description rather than custom
wiring such as wirewrap. Neither the PCI backplane nor the physical Softplanet are customized
in any way. Since there is no custom wiring, a failed board can be replaced with a generic
off–the–shelf spare, and that spare will automatically resume whatever functions had been
assigned to the original board. Similarly, if the chassis itself were to fail, then simply plugging
the boards into another generic chassis would restore complete operation. Cards and chassis can
be swapped between systems without needing to worry about custom wiring.