RVP8 User’s Manual September 2005 Hardware Installation 2. Hardware Installation 2.1 Overview and Input Power Requirements This chapter describes how to install the RVP8 hardware. Topics include mechanical installation and siting, electrical specifications of the interface signals, system-level considerations and the standard connector panel that is provided. There are three major modules supplied with the RVP8. These are: IFD (IF Digitizer) Typically mounted in the radar receiver cabinet.
RVP8 User’s Manual September 2005 2.2 Hardware Installation IFD IF Digitizer Module Installation The IFD mains power is to be permanently “hard wired” in a NEMA electrical enclosure that is accessible only to a trained technician. The ground (earth) connection should be attached directly to the IFD case mounting screw then brought to the power supply ground connection. Disconnect the the mains power before opening the IFD for service.
RVP8 User’s Manual September 2005 2.2.2 Hardware Installation IFD Revision History There have been several hardware revisions of the IFD module since its introduction initially with the RVP7. Table 2–1 summarizes the differences among all of the versions that have been manufactured so far. The remainder of this chapter covers only the 14-bit units, although the previous generation 12-bit units are compatible with the RVP8 as well. Table 2–1: Differences Among Versions of the IFD Rev.B A/D Chip Rev.
RVP8 User’s Manual September 2005 2.2.3 Hardware Installation IFD Power, Size and Mounting Considerations The IFD is a compact sealed module with dimensions 23.6 x 10.9 x 3.0 cm. (9.3 x 4.3 x 1.2 in). The unit is designed to be mounted on edge such that the 23.6 x 3.0 cm. surface is flush on the back of the receiver cabinet with 10.9 cm. protrusion into the cabinet. The unit is typically placed where a traditional LOG receiver would be installed.
RVP8 User’s Manual September 2005 2.2.4 Hardware Installation IFD I/O Summary The connectors on the IFD are labelled and described below for each hardware revision. Table 2–2: IFD Connectors (All Revisions) IFD I/O Summary Connector Label Style Description Reference J1 IFĆIN SMA IF signal from LNA/mixer; via an antiĆaliasing filter 2.2.6 centered at IF (supplied by SIGMET). 50W, + 6.5 dBm 2.2.7 max 2.2.8 2.2.
RVP8 User’s Manual September 2005 2.2.5 Hardware Installation IFD Adjustments and Test/Status Indicators The IFD is packaged in a tight metal enclosure for maximum noise immunity. The only adjustments on the module are the internal gain and offset pots that adjust the AFC analog output. Two switches on the unit provide standalone test features to verify the proper functioning of the IFD and to assist with setting the voltage span of the AFC DAC.
RVP8 User’s Manual September 2005 Hardware Installation framing protocols, and yellow indicates that the green LED is ON at the other end, i.e., that the other end is receiving our transmissions correctly and is able to communicate that information back to us. The internal jumper settings are summarized in the following table. Please also refer to Sections 2.2.11 and 2.2.12 for more information on setting up the AFC or External Clock options. Table 2–7: JP1 IFD Internal Jumper Settings Rev.B Rev.C Rev.
RVP8 User’s Manual September 2005 2.2.6 Hardware Installation IFD Input A/D Saturation Levels There are two analog signals that must be supplied to the IFD: S IF receiver signal S IF Tx Sample (Burst Pulse) for magnetron, or COHO reference for klystron. Both of these inputs are on SMA connectors. The IF signal should be driven by the front-end mixer/LNA/IF-Amp. components, similar to the way that a LOG receiver would normally be installed.
RVP8 User’s Manual September 2005 2.2.7 Hardware Installation IF Bandwidth and Dynamic Range The RVP8 performs best with a wide bandwidth IF input signal. This is because a wideband signal can be made free of phase distortions within the (relatively narrow) matched passband of the received signal. The RVP8 uses an external analog anti-aliasing filter at each of its IF and Burst inputs. The purpose of these filters is to block frequencies that would otherwise alias into the matched filter passband.
RVP8 User’s Manual September 2005 Hardware Installation Thus, the overall dynamic range at 1MHz bandwidth (approx. 1 msec transmit pulse) is 88+6+4 = 98dB. For a 0.5 msec pulse the dynamic range would be reduced to 95dB; but it would increase to 101dB for a 2.0 msec pulse. An actual calibration curve demonstrating this performance is shown in Figure 2–1, for which the RVP8’s digital bandwidth was set to 0.53MHz and external signal generator steps of 1dB were used over the full operating range.
RVP8 User’s Manual September 2005 2.2.8 Hardware Installation IF Gain and System Performance The previous discussion was concerned with measuring the dynamic range of a stand-alone IFD. We will now examine how the unit performs in the context of a complete radar receiver. We assume that an LNA/Mixer has already been selected that offers an appropriate balance between price and noise figure.
RVP8 User’s Manual September 2005 Hardware Installation noise power of the IFD over some bandwidth. Similarly, let N LNA represent the LNA/Mixer thermal noise power over that same bandwidth, and after amplification by all RF and IF stages. Note that N IFD is primarily due to the quantization noise that is introduced by the A/D converter, whereas N LNA has its origins in the fundamental thermal noise of the receiving system.
RVP8 User’s Manual September 2005 Hardware Installation 3. Thus, the RF/IF gain must bring the front-end thermal noise at –112dBm/MHz up to a level that is 6.1dB higher than the IFD noise density of –82dBm/MHz. The gain is therefore (–82dBm/MHz + 6dB) – (–112dBm/MHz) = 36dB. Note that this gain does not depend on bandwidth, and therefore will be correct for all pulsewidth/bandwidth combinations. 4. The dynamic range for the complete system at 0.5MHz bandwidth may now be calculated as 101dB – 7dB = 94dB.
RVP8 User’s Manual September 2005 Hardware Installation When two amplifiers are cascaded so that the output of the first drives the input of the second, the overall gain is the product of the two linear gains G 1lin and G 2lin , and the overall noise figure is computed from the two noise factors F 1lin and F 2lin as: NoiseFigure + 10 log 10 ƪ ǒ F 1lin ) F 2lin * 1 G 1lin Ǔƫ where the two noise factors are simply the linear representations of the noise figures that were expressed in deciBels: NoiseFig
RVP8 User’s Manual September 2005 Hardware Installation For similar reasons (i.e., transition band width), the digital FIR filter itself also becomes difficult to design when its passband is near a Nyquist multiple. But there is an additional constraint that the digital filter should have a very large attenuation at DC. This is so that fixed offsets in the A/D converter do not propagate into the synthesized “I” and “Q” data.
RVP8 User’s Manual September 2005 Hardware Installation There are two special concerns that may come up when the RVP8 is used in the above manner within a synchronous radar system. Both concerns are the result of the IFD’s sampling clock being asynchronous with the radar system clock. S RVP8 Generates the Radar Trigger The trigger signals supplied by the RVP8 are synchronous with the IFD data sampling clock.
RVP8 User’s Manual September 2005 Hardware Installation 128 (See also, Section 3.2.6). The tuning range of the VCXO is purposely kept very narrow (to improve the clock stability), and is restricted to approximately +/–50ppm. Thus, the input reference clock frequency (range 2–60MHz) must be precisely specified so as to stay within these limits. The reference clock input power level level should be between –10 and 0dBm. Use the following configuration to allow a Rev.
RVP8 User’s Manual September 2005 Hardware Installation for the data pairs and outer cable shield. In most radar applications it is highly recommended that shielded twisted pair cable be used rather than the more common unshielded variety. The DC shield ground is established only at the RVP8/Rx side to avoid ground loops between the IFD and PCI chassis. Three of the four CAT-5E twisted pairs are used as dedicated downlink channels, and the fourth pair carries a dedicated uplink channel.
RVP8 User’s Manual September 2005 Hardware Installation being used as the RF source, then you may want to lock your RVP8 to the STALO’s own reference clock (generally 10MHz). For dual-pol magnetron systems you must lock the RVP8 in this manner to measure differential phase. S For klystron and other synchronous radars there will always be some kind of reference clock in the system.
RVP8 User’s Manual September 2005 2.3 RVP8 Chassis 2.3.1 RVP8 Chassis Overview Hardware Installation The RVP8 main chassis can assume a variety of forms depending on the customer requirements. Appendix C describes a standard SIGMET system. A typical unit supplied by SIGMET contains at least the following: S A dual CPU on either motherboard or SBC in a passive PCI backplane S RVP8/Rx Card S I/O-62 Card and Connector Panel The system is also shipped with an integrated hard disk drive (HDD), 1.
RVP8 User’s Manual September 2005 2.3.3 Hardware Installation Main Chassis Direct Connections The direct connections to the RVP8 chassis are made either to the back of the unit to PCI cards (e.g., left) or to the remote connector panel. The direct connections are summarized in the table below.
RVP8 User’s Manual September 2005 Hardware Installation Depending on the installation, the jumpers on the I-O 62, Rx and Tx Cards may require configuration. These are described in Appendix C. 2.3.4 External Pre-Trigger Input Users may supply the RVP8 with their own CMOS-Level pre-trigger for installations in which adequate trigger control already exists. The trigger input is provided directly on the Rx Card (bottom BNC connector on the card panel labeled “TR-2 / In).
RVP8 User’s Manual September 2005 Hardware Installation S EXT LED indicates that the 12V input power is present S INT LED indicates that +3.3V is present S GO LED indicates that the panel is properly communicating with the PCI card. It will blink slowly when communication is absent and very rapidly during the BRIEF times that the backpanel firmware are being updated with an rdaflash command. It will be solid when the panel is being used by the RCP8 software. The table in Section 1.9.
RVP8 User’s Manual September 2005 Hardware Installation If larger current and voltage loads are required, then the connector panel relays can be used to switch external relays provided by the customer. Another alternative is to use the additional 4, 12V relay signals (up to 200mA) that are also supported on this connector. Hazard: External relays must be equipped with proper diode protection against back-EMF or damage to the I/O-62 and or the connector panel might result.
RVP8 User’s Manual September 2005 Hardware Installation J15-18: TRIG1-4- Output triggers The waveforms appearing on the four trigger outputs are programmed by the user to meet the radar’s exact timing needs. These correspond to the trigger generators TGEN1, TGEN2, TGEN3 and TGEN4. More triggers can be configured on the “SPARE” connectors if they are required.
RVP8 User’s Manual September 2005 2.3.6 Hardware Installation Power-Up Details WARNING: The Main Chassis redundant power supplies are NOT auto-ranging like the IFD. These are factory configured for the expected voltage, but should be VERIFIED by the customer before power is applied to the system. When the RVP8 is powered–up or reset, the host Linux PC goes through an automated boot process that ultimately starts the RVP8 application. The RVP8 then runs extensive internal diagnostics.
RVP8 User’s Manual September 2005 2.3.7 Hardware Installation Socket Interface The RVP8 as shipped is configured to listen on a network port. It is ready to interface to a host computer via the network using a program called DspExport. It is also ready to run some commands on the RVP8 itself. The RVP8 comes with some built–in SIGMET supplied utilities such as setup, dspx and ascope. These utilities are described in the IRIS Utilities Manual.
RVP8 User’s Manual September 2005 Hardware Installation Ack|CanCompress=1,Model=RVP8,Version=7.32 Your program can choose to evaluate or ignore any of these keywords. “CanCompress=1” indicates that the DspExport computer supports compression. The host computer can then choose to use compression if it wants to. When you first connect, you are in the “info only” mode. That means that the server will only respond to INFO and OPEN commands.
RVP8 User’s Manual September 2005 Hardware Installation Open the connection for I/O (OPEN) Example: “OPEN” This means switch from open for “info only” mode to open for I/O. If the signal processor is in use by another device, you will get an error in response to this command. Multiple clients are allowed to connect for info only, but only one can do I/O.
RVP8 User’s Manual September 2005 2.4 Hardware Installation Digital AFC Module (DAFC) The DAFC is a small self-contained circuit board which can passively “eavesdrop” on the RVP8’s serial uplink transmissions. Its purpose is to generate a set of digital AFC control lines that could be applied, for example, to a custom STALO frequency synthesizer. A full size (3”x3.75”) assembly diagram of the board is shown in Figure 2–3.
RVP8 User’s Manual September 2005 Hardware Installation assure a valid TTL low level of 0.6V max. requires that the STALO inputs be pulled up to +5 with nothing less than (approx.) 1.2KW. Put another way, the low level input current of the receiving device should not exceed 4.5mA. Most STALOs that we have seen use 5-20KW pull-up resistors, so this should not be a problem. All twenty five pins of the “D” connector are wired identically on the DAFC board, i.e.
RVP8 User’s Manual September 2005 Hardware Installation The DAFC board runs off of a single +5V power supply which can be applied either from the STALO through the “D” connector, or externally through the terminal block. There are also provisions for supplying +24V (approx.) between the terminal block and the “D” connector, which is handy for cabling power to a STALO that requires the second voltage. Two green LEDs indicate the presence of +5V and +24V.
RVP8 User’s Manual September 2005 Hardware Installation Table 2–11: Pinout for the CTI “MVSR-xxx” STALO Ribbon Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 “D” Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Function Ground +5V +24V Alarm –– Bit–2 Bit–3 Bit–11 Bit–9 Bit–8 Bit–7 Bit–12 Inhb Ribbon Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 “D” Pin 14 15 16 17 18 19 20 21 22 23 24 25 –– Function –– –– –– –– Bit–0 Bit–1 Bit–10 Bit–4 Bit–5 Bit–6 Ground Bit–13 –– First configure the IFD pins themselves.
RVP8 User’s Manual September 2005 2.4.2 Hardware Installation Example Hookup to a MITEQ “MFS-xxx” STALO The electrical interface for this STALO uses a 25-pin “D” connector with the following pin assignments S GROUND on pins 1 and 2. S Four BCD digits of 1KHz, 10KHz, 100KHz, and 1MHz frequency steps, using Pins <25:22>, <21:18>, <17:14>, <13:10>. S Seven binary bits of representing 10MHz steps, Bits<0:6> on Pins<9:3>. First configure the IFD pins themselves.
RVP8 User’s Manual September 2005 2.5 Hardware Installation RVP8 Custom Interfaces This section describes some additional points of interface to the RVP8. These hookups are less conventional than the “standard” interfaces described earlier in this chapter, but they sometimes can supply exactly what is needed in exactly the right place. For the most part, these custom interfaces are merely taps into existing internal signals that would normally not be seen by the user. 2.5.
RVP8 User’s Manual September 2005 Hardware Installation The uplink signal, shown in Figure 2–5, is periodic at the radar pulse repetition frequency, and conveys two distinct types of information to the IFD. The signal is normally low most of the time (to minimize driver and termination power), but begins a transition sequence at the beginning of each transmitted pulse. Figure 2–5: Timing Diagram of the IFD Coax Uplink t burst ts ts ts ts ts 1 2 3 4 5 6 7 8 9 10...
RVP8 User’s Manual September 2005 Hardware Installation The period t s of the serial data is (128ń f aq) , where f aq is the acquisition clock frequency given in the Mc section of the RVP8 setup menu. For the default clock frequency of 71.9502MHz, the period of the serial data will be 1.779μsec. The logic that is receiving the serial data should first locate the center of the first data bit at (0.5 t s) past the falling edge at the end of the burst window.
RVP8 User’s Manual September 2005 Hardware Installation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | | | | | | | | | | | | | | | | | | Command | Data | CMD/DATA |_______________|_______________________________________________| Commands #1, #2, and #3 control the 25 output pin levels of the DAFC board. These transmissions may be interspersed with the PLL-16 format in systems that require both clock locking and AFC, e.g., a dual-receiver magnetron system using a digitally synthesized COHO.
