UWB DWM100 USER MANUAL HOW TO USE, CONFIGURE AND PROGRAM THE UWB DWM100 TRANSCEIVER This document is subject to change without notice © 2021 B. Thermal Solutions srl Tel +390717822026 Mail info@brandoni.com Version 2.
UWB DWM100 User Manual Table of Contents LIST OF FIGURES ........................................................ 3 LIST OF TABLES .......................................................... 4 1 INTRODUCTION ................................................. 7 1.1 ABOUT THE UWB DWM100 ............................ 7 1.2 ABOUT THIS DOCUMENT ............................................. 7 2 OVERVIEW OF THE UWB DWM100 ...................10 2.1 INTRODUCTION ......................................................
UWB DWM100 User Manual List of Figures FIGURE 1: SPI READ AND WRITE TRANSACTIONS .........................11 FIGURE 2: SINGLE OCTET HEADER OF THE NON-INDEXED SPI TRANSACTION .......................................................................12 FIGURE 3: EXAMPLE NON-INDEXED READ OF THE DEVICE ID REGISTER (0X00) .................................................... 12 FIGURE 4: TWO OCTET HEADER OF THE SHORT INDEXED SPI TRANSACTION .......................................................................
UWB DWM100 User Manual List of Tables TABLE 1: MAIN UWB DWM100 OPERATIONAL STATES / MODES .........................................................................................................16 TABLE 2: MODE 2 EXCERPT FROM UWB DWM100 DATA SHEET OPERATIONAL MODES TABLE ..............................................20 TABLE 3: GPIO DEFAULT FUNCTIONS ...........................................21 TABLE 4: REGISTER ACCESSES REQUIRED TO LOAD LDE MICROCODE ....................................................
UWB DWM100 User Manual TABLE 57: RECOMMENDED PREAMBLE LENGTHS ....................... 212 TABLE 58: TRANSMISSIONS PER SECOND USING ALOHA ....... 213 TABLE 59: TECHNIQUES TO SAVE POWER IN RECEIVING............. 215 TABLE 60: PREAMBLE PARAMETERS ........................................... 219 TABLE 61: UWB DWM100 SUPPORTED UWB CHANNELS AND RECOMMENDED PREAMBLE CODES ................................... 220 TABLE 62: FRAME TYPE FIELD VALUES ........................................
UWB DWM100 User Manual © 2021 B. Thermal Solutions srl Tel +390717822026 Mail info@brandoni.com Version 2.
UWB DWM100 User Manual 1 Introduction 1.1 About the UWB DWM100 The UWB DWM100 is a module that incorporate the DW1000, a fully integrated low power, single chip CMOS radio transceiver IC compliant with theIEEE 802.15.4-2011 ultra-wideband (UWB) standard. • • • • • • It facilitates proximity detection to an accuracy of +/- 10 cm using two-way ranging time-of-flight (TOF) measurements.
UWB DWM100 User Manual Section Section Name No 8 UWB DWM100 Calibration Information covered Describes the parameters of the UWB DWM100 that require calibration; the methodology that should be used in calibrating them and how often they require calibration. Operational design choices when employing the UWB DWM100 Discusses some of the issues to be considered and trade-offs to be made when building systems based on the UWB DWM100 10 APPENDIX 1: The IEEE 802.15.
UWB DWM100 User Manual Mean PRF values are 16.1/15.6 MHz and 62.89/62.4 MHz. Refer to [1] for full details of peak and mean PRFs. Data Rate Where a data rate of 6.8 Mbps is referred to, this is equivalent to the 6.81/6.8 Mbps data rate in [1]. © 2021 B. Thermal Solutions srl Tel +390717822026 Mail info@brandoni.com Version 2.
UWB DWM100 User Manual 2 Overview of the UWB DWM100 2.1 Introduction The UWB DWM100 consists of an analog front-end (both RF and baseband) containing a receiver and transmitter and a digital back-end that interfaces to a host processor, controls the analog front-end, accepts data from the host processor for transmission and provides received data to the host processor over an industry standard SPI interface. A variety of control schemes are implemented to maintain and optimize transceiverperformance.
UWB DWM100 User Manual by the UWB DWM100, and for a write transaction all octets output by the UWB DWM100 should be ignored by the hostsystem.
UWB DWM100 User Manual Bit number: 7 6 Meaning: Operation: 0 = Read 1 = Write 5 Bit = 0, says sub-index is not present 4 3 2 1 0 Transaction Header Octet Register file ID – Range 0x00 to 0x3F (64 locations) Figure 2: Single octet header of the non-indexed SPI transaction The remaining octets of the transaction, the transaction body, immediately following this one-octet header are read from (or written to) the selected register file beginning at index zero.
UWB DWM100 User Manual MOSI 0x40 0x02 MISO 0xCA 0xDE Short sub-indexed read 2-octets beginning at index 2 in register file ID 0x00. This reads the high two octets of this 32-bit register, the result is 0xDECA. SPICSn Figure 5: Example short-indexed read of 3rd and 4th octets of register 0x00 2.2.1.2.2 SPI transaction with a 3-octet header Figure 6 shows the fields within the three octet transaction header of a long-indexed SPI transaction.
UWB DWM100 User Manual address. Octet 3 of the transaction header then contains 00000010, the remaining eight high order bits of the sub-address index, which is 0x02 in hex. The UWB DWM100 parameters that may be read and written using these SPI transactions are detailed in section 7 – The UWB DWM100 register set. 2.2.2 Interrupts The UWB DWM100 can be configured to assert its IRQ pin on the occurrence of one or more status events.
UWB DWM100 User Manual Power off OFF N 3.3 V rail > POR threshold? Y WAKEUP Crystal stable, RSTn released & Digital 1.
UWB DWM100 User Manual 2.3.2 Overview of main operational states Table 1: Main UWB DWM100 operational states / modes State Name State Description OFF In the OFF state the UWB DWM100 is completely powered off, with no voltages applied toany of its input pins. Power consumption = 0 µA. No I/O pins should be driven or power will leak through the I/O cells. WAKEUP During the WAKEUP state the crystal oscillator and the band-gap are enabled.
UWB DWM100 User Manual In the SLEEP state the IC consumes < 1 µA from the external power supply inputs. All internal LDOs are turned off. In the SLEEP state the UWB DWM100 internal low powered ring oscillator is running and is used to clock the sleep counter whose expiry SLEEP is programmed to “wake up” the UWB DWM100 and progress into the WAKEUP state. While inSLEEP power should not be applied to GPIO, SPICLK or SPIMISO pins as this will cause an increase in leakage current. © 2021 B.
UWB DWM100 User Manual State Name State Description With the exception of the OFF state, the DEEPSLEEP state is the lowest power state of the device. In DEEPSLEEP all internal circuitry is powered down with the exception of the alwayson memory which can be used to hold the device configuration for restoration on wakeup Once in DEEPSLEEP the UWB DWM100 remains there until the occurrence of a wakeupevent. This can be either: DEEPSLEEP 1. the SPICSn line pulled low or 2.
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UWB DWM100 User Manual State Name State Description expires. The snooze count times are in units of the raw 19.2 MHz XTI clock rate, (since the 125 MHz digital PLL clock is not running). 2.4 Power On Reset (POR) When the external power source is applied to the UWB DWM100 for the first time, the internal Power On Reset (POR) circuit compares the externally applied supply voltage to an internal power-on threshold (approximately 1.
UWB DWM100 User Manual The frequency of the low power oscillator is dependent on process variations within the IC, but is generally somewhere in between 7,000 and 13,000 Hz. There are facilities within the IC to measure the length of an LP oscillator cycle, in counts of the IC crystal oscillator divided by two, (i.e. this is 38.4 MHz ÷ 2, or 19.2 MHz). 2.4.1.
UWB DWM100 User Manual 2.4.2 Specific state sequences supported by the UWB DWM100 The UWB DWM100 supports a number of state sequences intended to minimize power consumption in certainapplications. These are: Mode Name Mode Description SNIFF MODE In SNIFF mode the UWB DWM100 alternates between the RX (on) and the IDLE (off) states.Further details on this mode are given in section 4.5.1 – SNIFF.
UWB DWM100 User Manual see sections Register file: 0x0E – System Event Mask Register and Register file: 0x0F – System Event Status Register. GPIOs are set to mode 0, their default function as shown in Table 3.
UWB DWM100 User Manual The RF PLL and Clock PLL are configured for channel 5 operation by default, please refer to Register file: 0x2B – Frequency synthesiser control block for channel configuration settings for each channel. 2.5.3 Default Transmitter Configuration Transmit RF channel configurations are set for channel 5 by default – see Sub-Register 0x28:0C– RF_TXCTRL. Transmit Smart power is enabled by default via the DIS_STXP bit in SYS_CFG register, refer to Register file: 0x04 – System Configuration.
UWB DWM100 User Manual 2.5.5.3 DRX_TUNE2 DRX_TUNE2 is set to 0x311E0035 by default which is not the optimal value for the default PRF and PAC. For best performance the user should set this value to 0x311A002D before proceeding to use the default device configuration. Refer to Sub-Register 0x27:08 – DRX_TUNE2. 2.5.5.4 NTM NTM is set to 0xC by default and may be set to 0xD for better performance, refer to Sub-Register 0x2E:0806 – LDE_CFG1. 2.5.5.
UWB DWM100 User Manual Table 4: Register accesses required to load LDE microcode Step Number L-1 L-2 L-3 2.5.5.11 Instruction Write Sub-Register Write Sub-Register Wait 150 µs Write Sub-Register 0x36:00 (PMSC_CTRL0) 0x2D:06 (OTP_CTRL) Data Length (Bytes) 2 2 0x0301 0x8000 0x36:00 (PMSC_CTRL0) 2 0x0200 Register Address Data (Write/Read) LDOTUNE It is necessary to load the LDOTUNE_CAL value from the OTP if it has been programmed during IC production test calibration.
UWB DWM100 User Manual 3 Message Transmission 3.1 Basic Transmission The transmission of data frames is one of the basic functions of the UWB DWM100 transceiver. Figure 10 showsthe elements of the transmitted frame.
UWB DWM100 User Manual Further transmission features are described in the following sections: • • • • 3.2 Transmit message time-stamping – see section 3.2 –Transmission timestamp. Delayed transmission – see section 3.3 – Delayed Transmission. Long transmit frames – see section 3.4 – Extended Length Data Frames. High Speed transmit – see section 3.5 – High Speed Transmission. Transmission timestamp During frame transmission the start of the PHR (PHY header) is the event nominated by the IEEE 802.15.
UWB DWM100 User Manual to minimise this the host microprocessor may sometimes be late invoking the delayed TX, i.e. so that the system clock has passed the specified start time (i.e. internal start time mentioned above) and then the IC has to complete almost a whole clock count period before the start time is reached.
UWB DWM100 User Manual operating with standard frame encoding because the SECDED error check sequence of the PHR in long frame mode is incompatible with the standard encoding. Note also that the probability of an error occurring within a frame increases as the frame length is increased, and as a result of this increasing the frame length may or may not improve system throughput depending on the frame error rate and the need to retransmit frames when there is an error.
UWB DWM100 User Manual number of preamble symbols received to additionally inform the choice of preamble length for any response frames. The SECDED (single error correct, double error detect) field, S5–S0, is a set of six parity check bits that are used to protect the PHR from errors caused by noise and channel impairments. The SECDED calculation is the same as that defined in the IEEE 802.15.
UWB DWM100 User Manual Clearly to do this care needs to be taken to have the frame length setup ready for inclusion in the PHR and to have the data written into the TX_BUFFER before it is consumed, and, mechanisms are needed to ensure that the wrong data cannot be sent as a good frame. The mechanisms to achieve this involves using SFCST to suppress FCS transmission until all data is written to the TX_BUFFER and then CANSFCS to cancel this suppression so that the FCS will be sent.
UWB DWM100 User Manual frame will be sent with a good CRC, and that is essentially the end of the discussion on this technique. If the host system has not been quick enough in writing the data this will result in the frame being sent with the wrong data but with a bad CRC also.
UWB DWM100 User Manual 4 Message Reception 4.1 Basic Reception The reception of a frame is enabled by a host request or by an automatic re-enabling of the receiver. The receiver will search for preamble continually until preamble has been detected or acquired, when a demodulation will be attempted. A preamble detection timeout may be set to allow the receiver to stop searching for preamble after a desired period. A basic receive sequence is shown in Figure 12. IDLE 4.1.
UWB DWM100 User Manual 0x27:24 – DRX_PRETOC. This may be useful after sending a message where a response is being awaited. Here if the preamble is not detected then the awaited response is not coming. The preamble detection time-out can be used to abandon the reception at the earliest possible time, saving power. The preamble detection state also has the possibility of operating in a mode called pulsed preamble detection mode (PPDM), or SNIFF mode, programmable through Register file: 0x1D – SNIFF Mode.
UWB DWM100 User Manual approximately 1 Mbps). If the PHR is indicating 850 kbps then the data demodulation continues at this rate, but if the PHR is indicating 6.8 Mbps then the demodulation changes to this rate at the end of the PHR as data demodulation begins. 4.1.5 Data Demodulation Section 10.2 – Data modulation scheme describes the modulation scheme.
UWB DWM100 User Manual 4.2 Delayed Receive In Delayed receive operation the receiver turn-on time is programmed into Register file: 0x0A – Delayed Send or Receive Time and then the delayed receiving is initiated by setting both RXDLYE and RXENAB controls in Register file: 0x0D – System Control Register.
UWB DWM100 User Manual Table 7: Registers in the RX double-buffered swinging-set RX double-buffered registers LDEDONE, RXDFR, RXFCE and RXFCG bits in Register file: 0x0F – System Event Status Register All of Register file: 0x10 – RX Frame Information Register All of Register file: 0x11 – RX Frame Buffer All of Register file: 0x12 – Rx Frame Quality Information All of Register file: 0x13 – Receiver Time Tracking Interval All of Register file: 0x14 – Receiver Time Tracking Offset All of Register file: 0x15 –
UWB DWM100 User Manual Status Register). Reception of a new frame with good CRC will cause the ICRBP bit to increment (or toggle). In the case that a received frame is rejected by frame filtering or bad CRC the ICRBP will not move on and the buffer will be reused for the next incoming frame. Thus, as noted in section 4.3.1 above, before enabling the receiver it is important to align both host and IC receivers.
UWB DWM100 User Manual Set up RX channel and other parameters as required Set DIS_DRXB bit = 0 in reg:04 to Enable double buffering Set RXAUTR bit = 1 in reg:04 to enable RX auto-re-enable Read SYS_STATUS reg:0F to checking that HSRBP == ICRBP YES HSRBP == ICRBP ? NO Issue the HRBPT command in reg:0x0D Set RXENAB bit = 1, in reg:0D, to enable the receiver Await frame arrival, as signalled by the RXFCG event flag (IRQ) Read the data in RX_BUFFER reg:11. Read other registers of interest e.g.
UWB DWM100 User Manual Mask Double buffered status bits; FCE, FCG, DFR, LDE_DONE to prevent glitch when cleared Set TXRXOFF bit = 1, in reg:0D, to disable the receiver Clear RX event flags in SYS_STATUS reg:0F; bits FCE, FCG, DFR, LDE_DONE Unmask Double buffered status bits; FCE, FCG, DFR, LDE_DONE Figure 15 : TRXOFF in Double-Buffered Mode 4.3.5 Overrun An overrun condition may occur in the IC receiver if the host side is not keeping up with the arrival rate of frames.
UWB DWM100 User Manual not return to sleep but continues to receive preamble and the data frame, and after successful reception can generate a receive frame interrupt to wake the host microprocessor to process the frame. A typical example of this would be to use a sleep time of 1 second and a wake-up period of 2 PAC intervals, where the average current for briefly listening and going back to sleep is very low.
UWB DWM100 User Manual 2 RX attempts with no RX detected, Host RX End. Sample Wakeup Event: Sleep counter expires SLEEP Cryst al stable, RSTn=1 RX CLKPLL locked IDLE WAKEUP RX SNOOZE INIT Preamble Snooze Count (Reg:36.0c) Timeout in PACs (in 19.2MHz cycles) IDLE INIT GO2SLP SLEEP PLL Lock Time (~5uS) Figure 17: Power profile for low power listening mode where no frame is received 4.4.
UWB DWM100 User Manual disabling the feature. Using SNIFF mode causes a reduction in sensitivity depending on the ratio and durations of the on and off periods. There are two variations of low power SNIFF mode; these are termed SNIFF and Low duty-cycle SNIFF described in the sub-sections below.
UWB DWM100 User Manual should always be 1 less than the desired total. The off duration is programmed in units of 1 µs. When both on and off durations are programmed with non-zero values SNIFF will be operational from the next RX enable. As an example if the PAC size is 8 symbols, (this is approximately 8 µs), and we want to have a 50:50 on-off duty cycle, then we could set SNIFF_ONT to its minimum of 2 PAC intervals (by programming the counter with a value of 1) and the SNIFF_OFFT to a value of 16 µs.
UWB DWM100 User Manual NOTE: In the INIT state the 125 MHz digital PLL clock is not running, instead the system is clocked at the raw 19.2 MHz XTI clock rate. Thus, in Low duty-cycle SNIFF mode the off period configured in the SNIFF_OFFT is in multiples of 6.6 µs (instead of the 1 µs units that apply in the SNIFF mode). The power saving of Low duty-cycle SNIFF mode is only realised when the off period is greater than 1 (i.e. > 6.6 µs).
UWB DWM100 User Manual In a network it may be useful to assess the quality of message reception from a particular node in order to change network routing or configurations related to that node to improve the reliability of the communications. For example to improve communications reliability the frame length might be shortened, or the data rate might be reduced, or the preamble length might be increased.
UWB DWM100 User Manual 4.7.
UWB DWM100 User Manual -65 Estimated RX LEVEL (16MHz PRF Free Space) -70 Estimated RX LEVEL (64MHz PRF Free Space) Estimated RX LEVEL (64MHz PRF Multipath) -75 Actual RX LEVEL -80 Estimated RX LEVEL -85 (dBm) -90 -95 -100 -105 -105 -100 -95 -90 -85 -80 Actual RX LEVEL (dBm) -75 -70 -65 Figure 22: Estimated RX level versus actual RX level © 2021 B. Thermal Solutions srl Tel +390717822026 Mail info@brandoni.com Version 2.
UWB DWM100 User Manual 5 Media Access Control (MAC) hardware features This section describes the features for media access control (MAC) that have been implemented in the UWB DWM100. 5.1 Cyclic redundancy check The UWB DWM100 includes a CRC generation function capable of automatically calculating and appending the 16-bit CRC frame check sequence (FCS) at the end of each transmitted frame.
UWB DWM100 User Manual • The frame type must be allowed for reception: o The FFAB configuration bit must be set to allow a Beacon frame to be received. o The FFAD configuration bit must be set to allow a Data frame to be received. o The FFAA configuration bit must be set to allow an Acknowledgment frame to be received. o The FFAM configuration bit must be set to allow a MAC command frame to be received. o The FFAR configuration bit allows IEEE 802.15.
UWB DWM100 User Manual 5.2.2 Frame Filtering Notes The frame filtering does not take any notice of the Security Enabled field, in the frame control, so it is up to the host software to decode any security information and accept/reject the frame is it sees fit. See section 11.2.2 – Security enabled Field for details.
UWB DWM100 User Manual the IEEE 802.14.4 standard, but the UWB DWM100 supports other preamble lengths. To cope with this the UWB DWM100 selects © 2021 B. Thermal Solutions srl Tel +390717822026 Mail info@brandoni.com Version 2.
UWB DWM100 User Manual preamble length as reported in the RXPSR field but also uses the Preamble Accumulation Count value reported in the RXPACC field of Register file: 0x10 – RX Frame Information Register. Table 8 presents the resulting preamble length used for the ACK frame as a function of RXPSR and RXPACC fields.
UWB DWM100 User Manual because the accumulation stops when any tap value grows to be a 16-bit number. This is typically when the sending device is close to the receiver, but in any case the number reported has been sufficient for correct reception of the frame being acknowledged, so even if this results in a shorter preamble for the auto-ACK frame this preamble should still have ample length for correct reception.
UWB DWM100 User Manual Please refer to the standard [1] for details of this. The UWB DWM100 does not automatically determine the framepending bit inserted into the automatically-generated ACK frames. Instead it copies the value of the AACKPEND configuration bit (from Register file: 0x04 – System Configuration), which is zero by default. 5.3.5 Host Notification The AAT status bit (Register file: 0x0F – System Event Status Register) indicates that an acknowledgement has been requested.
UWB DWM100 User Manual 6 Other features of the UWB DWM100 6.1 External Synchronisation This feature is used to synchronise UWB DWM100 with external clocks or events or with other UWB DWM100’s. For example, this would be required in a TDOA RTLS system employing wired clock synchronisation of the anchornodes.
UWB DWM100 User Manual To configure UWB DWM100 for OSTR mode, the OSTRM bit in the EC_CTRL register is set and the WAIT value is setto the desired delay value. When a counter running on the 38.4 MHz external clock and initiated on the rising edge of the SYNC signal equals the WAIT programmed value, the UWB DWM100 timebase counter will be reset. See Register file: 0x24 – External Synchronisation Control for register details.
UWB DWM100 User Manual External Clock 38.4 MHz SYNC WAIT Cycles wrt EXT_CLK 124.8MHz TX START Figure 24: Synchronised Transmission 6.1.3 One Shot Receive Synchronisation (OSRS) Mode One Shot Receive Synchronisation (OSRS) mode provides a second timebase in UWB DWM100 that can be synchronised to an external timebase and used to timestamp receive events. This allows a user to have a timebase outside the UWB DWM100, and to receive timing information about the receive events in this timebase.
UWB DWM100 User Manual = (N+1) x TExternal -T1+T3. Where: • • • • • N is the number of external clock cycles since the SYNC signal captured in timestamp and may be read from EC_RXTC in the RS_TS_EST field, see Sub-Register 0x24:04 EC_RXTC. TExternal is the period of the external clock. T2 is time from the rising edge of the external clock to the RMARKER. T1 is the time in ns reported by EC_GOLP in the OFFSET_EXT field, see Sub-Register 0x24:08 EC_GOLP.
UWB DWM100 User Manual 6.3.1 OTP memory map The OTP memory locations are as defined in Table 10. The OTP memory locations are each 32-bits wide, OTP addresses are word addresses so each increment of address specifies a different 32-bit word. Table 10: OTP memory map OTP Address Size (Used Bytes) 0x000 4 64 bit EUID 0x001 4 (These 64 bits get automatically copied over to Register File 0x01:EUI on each reset.
UWB DWM100 User Manual The SR (“Special Register”) is a 32-bit segment of OTP that is directly readable via the register interface upon power up. To programme the SR register follow the normal OTP programming method but set the OTP address to 0x400. The value of the SR register can be directly read back at address Register file: 0x2D – OTP Memory Interface. Table 11: OTP_SRDAT Register Bit 31:5 4:3 Function Reserved. Defaults to all “0”.
UWB DWM100 User Manual Step Number Register Address Instruction C-15 Write Sub-Register 0x2D:06 (OTP_CTRL) Configure OTP for Programming – Stage 3: C-16 Write Sub-Register 0x2D:07 (OTP_CTRL+1) C-17 Write Sub-Register 0x2D:00 (OTP_WDAT) C-18 Write Sub-Register 0x2D:06 (OTP_CTRL) Wait 1ms C-19 Write Sub-Register 0x2D.
UWB DWM100 User Manual 6.4 Measuring IC temperature and voltage The UWB DWM100 is equipped with a low speed 8-bit SAR A/D convertor which can be configured to sample values from an internal IC temperature sensor and also from a battery voltage monitor on the VDDAON power supply input. These readings can be manually run under host control, or they can be configured to berun automatically each time the UWB DWM100 enters the WAKEUP state.
UWB DWM100 User Manual 7 The UWB DWM100 register set The UWB DWM100 is controlled by an associated host microcontroller system using the SPI interface to access aseries of registers within the device. The UWB DWM100 register set includes configuration registers, status registers, control registers, data buffer registers, and diagnostic registers. Section 2.2 – The SPI Interface described the SPI interface and the low level transactions for reading and writing the parameters of the UWB DWM100.
UWB DWM100 User Manual ID Length (octets) Type Mnemonic RX_TIME TX_TIME TX_ANTD SYS_STATE ACK_RESP_T RX_SNIFF TX_POWER CHAN_CTRL USR_SFD AGC_CTRL EXT_SYNC ACC_MEM GPIO_CTRL DRX_CONF RF_CONF TX_CAL FS_CTRL AON OTP_IF LDE_CTRL DIG_DIAG 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 to 0x35 14 10 2 5 4 4 4 4 41 33 12 4064 44 44 58 52 21 12 18 41 ROD RO RW RO RW RW RW RW RW RW RW RO RW RW RW RW RW RW RW RW RW -
UWB DWM100 User Manual 7.2 Detailed register description 7.2.1 Terminology Section 7.1 gives an overview of the UWB DWM100 register set presenting all top level register file ID addresses in Table 15. This section describes in detail the contents and functionality of these register files in separate subsections.
UWB DWM100 User Manual The Device Identifier register contains the following sub-fields: REG:00:00 – DEV_ID – Device Identifier 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RIDTAG MODEL VER REV 1 1 0 1 1 1 1 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 Definition of the sub fields of REG:00:00 – DEV_ID: Device Identifier: Field REV Description of fields within Register file: 0x00 – Device Identifier Revision: This number will be updated for minor corrections an
UWB DWM100 User Manual 7.2.3 Register file: 0x01 – Extended Unique Identifier ID 0x01 Length (octets) 8 Type RW Mnemonic EUI Description Extended Unique Identifier – the 64-bit IEEE device address Register map register file 0x01 is the Extended Unique Identifier register. For IEEE 802.15.4 compliance every device should have a unique 64-bit device identifier. The high-order 24-bits of the EUI are a company identifier assigned by the IEEE Registration Authority, (see http://standards.ieee.
UWB DWM100 User Manual The ordering of octets read from the Extended Unique Identifier register is designed to be directly compatible with the octet ordering of the 64-bit source address fields of IEEE 802.15.4 standard MAC frames easing the task of inserting it into a frame for transmission. 7.2.4 Register file: 0x02 – Reserved ID 0x02 Length (octets) Type Mnemonic - - - Description Reserved – this register file is reserved Register map register file 0x02 is reserved for future use.
UWB DWM100 User Manual The host software (MAC) only needs to program this register if it is using the UWB DWM100’s receive frame filtering and automatic acknowledgement generation functions. The sub-fields are: Field Description of fields within Register file: 0x03 – PAN Identifier and Short Address SHORT_ADDR Short Address.
UWB DWM100 User Manual Field FFBC reg:04:00 bit:1 FFAB reg:04:00 bit:2 FFAD reg:04:00 bit:3 FFAA reg:04:00 bit:4 FFAM reg:04:00 bit:5 FFAR reg:04:00 bit:6 FFA4 reg:04:00 bit:7 Description of fields within Register file: 0x04 – System Configuration Frame Filtering Behave as a Coordinator. FFEN must be set to enable this frame filtering operation. A coordinator will accept a frame without a destination address if the source address has the PAN_ID matching the coordinator’s PAN_ID.
UWB DWM100 User Manual Field FFA5 reg:04:00 bit:8 HIRQ_POL reg:04:00 bit:9 SPI_EDGE reg:04:00 bit:10 DIS_FCE reg:04:00 bit:11 DIS_DRXB reg:04:00 bit:12 DIS_PHE reg:04:00 bit:13 Description of fields within Register file: 0x04 – System Configuration Frame Filtering Allow frames with frame type field of 5, (binary 101). IEEE 802.15.4-2011 frames begin with three frame type bits, b3 to b0. The value of binary 100 is not defined in IEEE 802.15.4-2011.
UWB DWM100 User Manual Field DIS_RSDE reg:04:00 bit:14 FCS_INIT2F reg:04:00 bit:15 PHR_MODE reg:04:00 bits:17,16 DIS_STXP reg:04:00 bit:18 Description of fields within Register file: 0x04 – System Configuration Disable Receiver Abort on RSD error. During normal reception (i.e.
UWB DWM100 User Manual Field RXM110K Description of fields within Register file: 0x04 – System Configuration Receiver Mode 110 kbps data rate. This configuration when set to 1 will cause the receiver to look for long SFD and process the PHY Header and RX data as per the 110 kbps frame mode. When this configuration is 0, (the default), the receiver will look for short SFD and will determine the RX data rate from the PHY header as either 850 kbps or 6.8 Mbps.
UWB DWM100 User Manual 7.2.8 Register file: 0x06 – System Time Counter ID Length (octets) 0x06 5 Type RO Mnemonic SYS_TIME Description System Time Counter (40-bit) Register map register file 0x06 is the System Time Counter register. System time and time stamps are designed to be based on the time units which are nominally at 64 GHz, or more precisely 499.2 MHz × 128 which is 63.8976 GHz.
UWB DWM100 User Manual The fields of the TX_FCTRL register identified above are individually described below: Field TFLEN reg:08:00 bits:6–0 TFLE Description of fields within Register file: 0x08 – Transmit Frame Control Transmit Frame Length. Standard IEEE 802.15.4 UWB frames can be up to 127 bytes long. The value specified here determines the length of the data portion of the transmitted frame.
UWB DWM100 User Manual Field TXPSR reg:08:00 bits:19,18 PE reg:08:00 bits:21,20 Description of fields within Register file: 0x08 – Transmit Frame Control Transmit Preamble Symbol Repetitions (PSR). This sets the length of the transmitted preamble sequence in symbols. Each preamble symbol is approximately 1 µs in duration1.The two TXPSR bits are copied into the PHY Header. The receiving end is thus made aware of how much preamble was sent.
UWB DWM100 User Manual Field Description of fields within Register file: 0x08 – Transmit Frame Control Inter-Frame Spacing. This delay in preamble symbol times will be applied between successive transmitted frames. One use of the IFSDELAY is to allow the receiver time to unload and process the frame before another frame is sent to it. For this reason IFSDELAY is logically considered to be a post-amble to the transmitted frame, and it begins counting down after the last symbol of data is sent.
UWB DWM100 User Manual Refer to the TX_PSTM field of Sub-Register 0x2F:24 – Digital Diagnostics Test Mode Control for details of how to program this register for use in Transmit Power Spectrum Test Mode and note that bits 31:0 only are used in this mode, whilst the 9 least significant bits are ignored in functional modes. 7.2.
UWB DWM100 User Manual When frame filtering is employed, any frames rejected are not treated as valid RX frames (neither RXDFR or RXFCG are set) so the receiver and the receive frame wait timeout just continues its countdown Register file: 0x0C – Receive Frame Wait Timeout Period contains the following fields: REG:0C:00 – RX_FWTO – Receive Frame Wait Timeout Period 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - RXFWTO 0 0 0 0 0 0 0 0 0 0 0
- - - - - - - - - - - - - - - - - - - - - CANSFCS TXDLYS TXSTRT SFCST - RXDLYE RXENAB WAIT4RESP TRXOFF - HRBPT UWB DWM100 User Manual 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Field SFCST reg:0D:00 bit:0 TXSTRT reg:0D:00 bit:1 Description of fields within Register file: 0x0D – System Control Register Bits marked ‘-’ in register 0x0D are reserved and should always be written as zero. Suppress auto-FCS Transmission (on this next frame).
UWB DWM100 User Manual Field TXDLYS reg:0D:00 bit:2 Description of fields within Register file: 0x0D – System Control Register Transmitter Delayed Sending. This control works in conjunction with TXSTRT and the DX_TIME value specified by Register file: 0x0A – Delayed Send or Receive Time. When the user wants to control the time of sending of a frame, the send time is programmed into DX_TIME, and then both TXDLYS and TXSTRT should be set at the same time to correctly invoke the delayed sending feature.
UWB DWM100 User Manual Field Description of fields within Register file: 0x0D – System Control Register WAIT4RESP Wait for Response. The WAIT4RESP control works in conjunction with TXSTRT bit above and the W4R_TIM value in Register file: 0x1A – Acknowledgement time and response time.
UWB DWM100 User Manual - - MLDEERR MRXRFTO MRXRFSL MRXFCE MRXFCG MRXDFR MRXPHE MRXPHD MLDEDON MRXSFDD MRXPRD MTXFRS MTXPHS MTXPRS MTXFRB MAAT MESYNCR MCPLOCK - MAFFREJ MTXBERR MHPDWAR MPLLHILO MRFPLLLL MRFPLLLL MSLP2INIT MGPIOIRQ MRXPTO MRXOVRR REG:0E:00 – SYS_MASK – System Event Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The system event mask bits of the SYS_MASK register identified abo
UWB DWM100 User Manual Field MRXPHD reg:0E:00 bit:11 MRXPHE reg:0E:00 bit:12 MRXDFR reg:0E:00 bit:13 MRXFCG reg:0E:00 bit:14 MRXFCE reg:0E:00 bit:15 MRXRFSL reg:0E:00 bit:16 MRXRFTO reg:0E:00 bit:17 MLDEERR reg:0E:00 bit:18 – reg:0F:00 Description of fields within Register file: 0x0E – System Event Mask Register Mask receiver PHY header detect event. When MRXPHD is 0 the RXPHD event status bit will not generate an interrupt.
UWB DWM100 User Manual Field MRXSFDTO reg:0E:00 bit:26 Description of fields within Register file: 0x0E – System Event Mask Register Mask Receive SFD timeout event. When MRXSFDTO is 0 the RXSFDTO event status bit will not generate an interrupt. When MRXSFDTO is 1 and the RXSFDTO event status bit is 1, the hardware IRQ interrupt line will be asserted to generate an interrupt. MHPDWARN Mask Half Period Delay Warning event. When MHPDWARN is 0 the HPDWARN event status bit will not generate an interrupt.
UWB DWM100 User Manual - - - - - TXPUTE RXPREJ RXRSCS REG:0F:04 – SYS_STATUS – System Status Register (octet 4) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 The system event status bits of the SYS_STATUS register identified above are individually described below: Field IRQS reg:0F:00 bit:0 CPLOCK reg:0F:00 bit:1 ESYNCR reg0F:00 bit:2 AAT reg:0F:00 bit:3 Description of fields within Register file: 0x0F – System Event Status Register Int
UWB DWM100 User Manual Field TXPRS reg:0F:00 bit:5 TXPHS reg:0F:00 bit:6 TXFRS reg:0F:00 bit:7 RXPRD reg:0F:00 bit:8 RXSFDD reg:0F:00 bit:9 LDEDONE reg:0F:00 bit:10 RXPHD reg:0F:00 bit:11 Description of fields within Register file: 0x0F – System Event Status Register Transmit Preamble Sent. This event status bit is set at the end of preamble when SFD sending begins. The TXPRS bit is automatically cleared at the next transmitter enable. It can also be cleared explicitly by writing a 1 to it.
UWB DWM100 User Manual Field RXPHE reg:0F:00 bit:12 RXDFR reg:0F:00 bit:13 Description of fields within Register file: 0x0F – System Event Status Register Receiver PHY Header Error. This event status bit is set to indicate that the receiver has found a non-correctable error in the PHR. The PHR includes a SECDED error check sequence (see section 10.4) that can correct a single bit error and detect a double bit error.
UWB DWM100 User Manual Field RXRFSL reg:0F:00 bit:16 RXRFTO reg:0F:00 bit:17 LDEERR reg:0F:00 bit:18 – reg:0F:00 Description of fields within Register file: 0x0F – System Event Status Register Receiver Reed Solomon Frame Sync Loss. The RXRFSL event status bit is set to indicate that the receiver has found a non-correctable error during the Reed Solomon decoding of the data portion of the frame.
UWB DWM100 User Manual Field RXPTO reg:0F:00 bit:21 Description of fields within Register file: 0x0F – System Event Status Register Preamble detection timeout. This event status bit is set when the preamble detection timeout occurs. The preamble detection timer is started when the receiver is enabled and begins preamble hunt. This may begin immediately in the case of issuing an RXENAB command or after a delay in the case of issuing a RXDLYE command.
UWB DWM100 User Manual Field RXSFDTO reg:0F:00 bit:26 HPDWARN reg:0F:00 bit:27 Description of fields within Register file: 0x0F – System Event Status Register Receive SFD timeout. This event status bit is set when the SFD detection timeout occurs. The SFD detection timeout starts running as soon as preamble is detected. If the SFD sequence is not detected before the timeout period expires then the timeout will act to abort the reception currently in progress.
UWB DWM100 User Manual Field TXBERR reg:0F:00 bit:28 AFFREJ reg:0F:00 bit:29 HSRBP reg:0F:00 bit:30 ICRBP reg:0F:00 bit:31 RXRSCS reg:0F:04 bit:0 RXPREJ reg:0F:04 bit:1 Description of fields within Register file: 0x0F – System Event Status Register Transmit Buffer Error. The TXBERR event status flag bit indicates that a write to a transmitted data buffer location has occurred whilst CRC was suppressed. Section 3.
UWB DWM100 User Manual receiver enable, including those caused by the RXAUTR auto-re-enable. © 2021 B. Thermal Solutions srl Tel +390717822026 Mail info@brandoni.com Version 2.
UWB DWM100 User Manual Field TXPUTE Description of fields within Register file: 0x0F – System Event Status Register Transmit power up time error. This is a low-level event status flag. It applies when delayed transmission is being used. Frame transmission will continue if this condition is detected, and the RMARKER will be sent at the correct time, but that the initial few preamble symbols may not transmit correctly. This may have a performance effect when a short preamble sequence is being employed.
UWB DWM100 User Manual Field RXFLEN reg:10:00 bits:6–0 RXFLE reg:10:00 bits:9–7 - Description of fields within Register file: 0x10 – RX Frame Information Register Receive Frame Length. This value is copied from the PHR of the received frame when a good PHR is detected (when the RXPHD status bit is set). The frame length from the PHR is used in the receiver to know how much data to receive and decode, and where to find the FCS (CRC) to validate the received data.
UWB DWM100 User Manual Field RXBR reg:10:00 bits:14,13 RNG reg:10:00 bit:15 RXPRFR reg:10:00 bits:17,16 RXPSR reg:10:00 bits:19,18 Description of fields within Register file: 0x10 – RX Frame Information Register Receive Bit Rate report. This field reports the received bit rate. This information is signalled in the received frame’s PHR (see 10.4 for details). Expected values supported by the UWB DWM100 are: 00 = 110 kbps, 01 =850 kbps, and 10 = 6.
UWB DWM100 User Manual Field RXPACC Description of fields within Register file: 0x10 – RX Frame Information Register Preamble Accumulation Count. This reports the number of symbols of preamble accumulated. reg:10:00 bits:31–20 This may be used to estimate the length of TX preamble received and also during diagnostics as an aid to interpreting the accumulator data.
UWB DWM100 User Manual Table 18: RXPACC Adjustments by SFD code SFD Standard Short (8symbol) Standard Long (64symbol) Sequence Adjustment to RXPACC -6+2-1=-5 0+0−+00−0+0−+00–00+0−0+0+000−0−0−00+0–0−+0000++00−−−+−++0000++ -62+14-16=64 0+0-+00- 7.2.19 Register file: 0x11 – RX Frame Buffer ID 0x11 Length (octets) 1024 Type Mnemonic ROD RX_BUFFER Description RX Frame Data Buffer – included in swinging set Register map register file 0x11 is the receive data buffer.
UWB DWM100 User Manual Register map register file 0x12 gives information about quality of reception for the current frame. This register consists of a number of sub-fields separately identified and described below: Register file: 0x12 – Rx Frame Quality Information is in the RX double-buffered swinging-set. See section 4.3 – Double Receive Buffer for more details.
UWB DWM100 User Manual Field Description of fields within Register file: 0x12 – Rx Frame Quality Information Channel Impulse Response Power. This is a 16-bit value reporting the sum of the squares of the magnitudes of the accumulator from the estimated highest power portion of the channel, which is related to the receive signal power. This value can be used in assessing the quality of the received signal and/or the receive timestamp produced by the LDE algorithm. For more details please refer to section 4.
UWB DWM100 User Manual Register file: 0x14 – Receiver Time Tracking Offset is in the RX double-buffered swinging-set. See section 4.3 – Double Receive Buffer for more details.
UWB DWM100 User Manual UWB DWM100 takes a coarse timestamp of the symbol in which the RMARKER event occurs and to this adds various correction factors to give a resultant time stamp value. Please refer to section 4.1.6 – RX Messagetimestamp for more details of the corrections applied. Register file: 0x15 – Receive Time Stamp is in the RX double-buffered swinging-set. See section 4.3 – Double Receive Buffer for more details.
UWB DWM100 User Manual Field FP_INDEX Description of fields within Register file: 0x15 – Receive Time Stamp First path index. This is a 16-bit value reporting the position within the accumulator that the LDE algorithm has determined to be the first path. This value is set during the LDE algorithm’s analysis of the accumulator data and is updated when the LDE execution has completed (when the LDEDONE status bit is set).
UWB DWM100 User Manual Register map register file 0x17 reports the transmit time stamp information. During frame transmission the start of the PHR is the nominal point which is time-stamped by the IC. The IEEE 802.15.4 UWB standard calls this point the RMARKER. The UWB DWM100 takes a timestamp of the symbol in which the RMARKER event occursand to this adds the antenna delay to give a resultant time stamp value, of when the RMARKER is launched from the antenna.
UWB DWM100 User Manual Antenna Delay for details of calibration of antenna delay. The units here are the same as those used for system time and time stamps, i.e. 499.2 MHz × 128, so the least significant bit is about 15.65 picoseconds. NB: This register is not preserved during SLEEP or DEEPSLEEP and so needs reprogramming after a wakeup event in order to obtain the correct adjustment of the TX_STAMP.
UWB DWM100 User Manual Field ACK_TIM Description of fields within Register file: 0x1A – Acknowledgement time and response time Auto-Acknowledgement turn-around Time. This 8-bit field is used to configure the turnaround time between the correct receipt of a data frame (or a MAC command frame) and the transmission by the UWB DWM100 of the acknowledgement frame. The time here is specifiedin units of preamble symbols.
UWB DWM100 User Manual The transmitting device needs to be sending a sufficiently long preamble to allow for the SNIFF mode to operate and leave sufficient preamble remaining thereafter to get a good reception and RX timestamp. The power saving is dependent on the configured on/off times for this sampling. See additionally section 2.4.2 – Specific state sequences supported by the UWB DWM100 and 4.5 – Low-Power SNIFF mode for additional discussion.
UWB DWM100 User Manual (The UWB DWM100 has an area of OTP memory reserved for this. Please refer to section 8 –UWB DWM100 Calibration and section 6.3 – Using the on-chip OTP memory for more details). The transmitter output power can be adjusted using this Register file: 0x1E – Transmit Power Control. This contains four octets each of which specifies a separate transmit power setting. These separate settings are applied by the IC in one of two ways. These two alternatives are described in section 7.2.31.
UWB DWM100 User Manual power and still remain within regulatory power limits which are typically specified as average power per millisecond. When DIS_STXP is 0 and the data rate is configured to 6.8 Mbps, Smart Tx power is enabled. The UWB DWM100selects one of the fields of the TX Power Control register (BOOSTxxxx) depending on the overall frame duration.
UWB DWM100 User Manual Field BOOSTP250 reg:1E:00 bits:23–16 Description of fields within Register file: 0x1E – Transmit Power Control (when DIS_STXP is 0) This value sets the power applied to the preamble and data portions of the frame during transmission at the 6.8 Mbps data rate for frames that are less than 0.25 ms duration which is determined by the following criteria: -- Preamble Length of 64 symbols and Frame Length of <= 123 bytes. -- Preamble Length of 128 symbols and Frame Length of <= 67 bytes.
UWB DWM100 User Manual REG:1E:00 – TX_POWER – Transmit Power Control (When DIS_STXP = 1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not applicable TXPOWSD TXPOWPHR Not applicable 0x0E 0x08 0x02 0x22 The individual sub-fields are described below. Field TXPOWPHR Description of fields within Register file: 0x1E – Transmit Power Control (when DIS_STXP is 0) This power setting is applied during the transmission of the PHY header (PHR) portion of the frame. Section 7.2.
UWB DWM100 User Manual Table 19: Reference values for Register file: 0x1E – Transmit Power Control, for Smart Transmit Power Control TX Channel Example Register file: 0x1E – Transmit Power Control values for 16 MHz, with DIS_STXP = 0 Example Register file: 0x1E – Transmit Power Control values for 64 MHz, with DIS_STXP = 0 1, 2 0x15355575 0x07274767 3 0x0F2F4F6F 0x2B4B6B8B 4 0x1F1F3F5F 0x3A5A7A9A 5 0x0E082848 0x25456585 7 0x32527292 0x5171B1D1 Table 20: Reference values Register file: 0x1E
UWB DWM100 User Manual The individual sub-fields are described below: Field TX_CHAN reg:1F:00 bits:3–0 RX_CHAN reg:1F:00 bits:7–4 - Description of fields within Register file: 0x1F – Channel Control This selects the transmit channel. Supported channels are 1, 2, 3, 4, 5, and 7. Other values should not be used. Both TX_CHAN and RX_CHAN (below) should be set to the same value.
UWB DWM100 User Manual DWSFD When DWSFD is 0, and TNSSFD and RNSSFD are deasserted low, then the SFD sequence used by the UWB DWM100 will bethe one prescribed by the IEEE 802.15.4-2011 standard. reg:1F:00 bit:17 For the 110 kbps this SFD is 64 symbols long (as normal), but for 850 kbps the SFD may be either 8 or 16 symbols long, this is selected by the SFD length field within Register file: 0x21 – User defined SFD sequence. Other length values are invalid and should not be used. (For 6.
UWB DWM100 User Manual the performance in 110 kbps mode. Table 22 below presents additional SFD sequence programming options. Note: The selection of SFD sequences other than the IEEE 802.15.4-2011 UWB standard compliant SFD sequence may improve performance, but will of course make it impossible to interwork with a device configured to use the standard defined SFD (or with a third party devices using the standard SFD).
UWB DWM100 User Manual Field Description of fields within Register file: 0x1F – Channel Control 110 kbps 0 1 1 x When the UWB DWM100 is operatingat 110 kbps, this selects the useof a user configured SFD with fixed length of 64 symbols. In this mode the user is responsible for correctly programming the SFD sequencein Register file: 0x21 – User defined SFD sequence. Note: Configurations other than those defined in Table 21 or Table 22 are not recommended.
UWB DWM100 User Manual 7.2.33 Register file: 0x20 – Reserved ID 0x20 Length (octets) Type Mnemonic - - - Description Reserved – this register file is reserved Register map register file 0x20 is reserved for future use. Please take care not to write to this register as doing so may cause the UWB DWM100 to malfunction. 7.2.
UWB DWM100 User Manual Data Rate 6.8 Mbps 850 kbps 110 kbps DWSFD TNSSFD RNSSFD SFD_LENGTH reg:1F:00 bit:17 reg:1F:00 bit:20 0 1 1 0 1 0 reg:1F:00 bit:21 0 1 0 Description reg:21:00 bits:0–7 x When the UWB DWM100 is operating at 6.8 Mbps, this programming selects the standard IEEE 8- symbol SFD which gives sufficient robustness since the data is already the weakest part of theframe. 16 The standard IEEE 8-symbol SFD is weaker than data at 850 kbps.
UWB DWM100 User Manual Table 22: Other possible SFD sequence configurations Data Rate 850 kbps 110 kbps 850 kbps 6.8 Mbps or 850 kbps 110 kbps DWSFD TNSSFD RNSSFD SFD_LENGTH reg:1F:00 bit:17 reg:1F:00 bit:20 0 0 1 0 0 0 0 0 1 1 reg:1F:00 bit:21 Description reg:21:00 bits:0–7 0 x This programming selects the 8-symbol SFD as defined in the IEEE 802.15.4 standard, when operating at 850 kbps. 0 x This programming selects the 64-symbol SFD as defined in the IEEE 802.15.
UWB DWM100 User Manual Sub-Index Field 0 SFD_LENGTH reg:21:00 1 reg:21:01 2 reg:21:02 3 reg:21:03 4 reg:21:04 5 reg:21:05 6 reg:21:06 7 reg:21:07 8 reg:21:08 9 reg:21:09 10 reg:21:0A 11 reg:21:0B 12 reg:21:0C 13 reg:21:0D 14 reg:21:0E 15 reg:21:0F 16 reg:21:10 TX_SSFD_MAGL (Symbols 7..0) TX_SSFD_MAGH (Symbols 15..8) TX_SSFD_SGNL (Symbols 7..0) TX_SSFD_SGNH (Symbols 15..8) RX_SSFD_MAGL (Symbols 7..0) TX_SSFD_SGNH (Symbols 15..8) RX_SSFD_SGNL (Symbols 7..0) TX_SSFD_SGNH (Symbols 15..
UWB DWM100 User Manual Sub-Index Field 17 TX_LSFD_SGN0 (Symbols 7..0) reg:21:11 18 reg:21:12 19 reg:21:13 20 reg:21:14 21 reg:21:15 22 reg:21:16 23 reg:21:17 24 reg:21:18 25 reg:21:19 26 reg:21:1A 27 reg:21:1B 28 reg:21:1C 29 reg:21:1D 30 reg:21:1E 31 reg:21:1F 32 reg:21:20 33 reg:21:21 34 reg:21:22 35 reg:21:23 36 reg:21:24 37 reg:21:25 38 reg:21:26 39 reg:21:27 40 reg:21:28 TX_LSFD_SGN1 (Symbols 15..8) TX_LSFD_SGN2 (Symbols 23..16) TX_LSFD_SGN3 (Symbols 31..
UWB DWM100 User Manual Table 21: Recommended SFD sequence configurations for best performance Data Rate 6.8 Mbps 850 kbps 110 kbps DWSFD TNSSFD RNSSFD SFD_LENGTH reg:1F:00 bit:17 reg:1F:00 bit:20 0 1 1 0 1 0 reg:1F:00 bit:21 0 1 0 Description reg:21:00 bits:0–7 x When the UWB DWM100 is operating at 6.8 Mbps, this programming selects the standard IEEE 8- symbol SFD which gives sufficient robustness since the data is already the weakest part of theframe.
UWB DWM100 User Manual Table 22: Other possible SFD sequence configurations Data Rate 850 kbps 110 kbps 850 kbps 6.8 Mbps or 850 kbps 110 kbps DWSFD TNSSFD RNSSFD SFD_LENGTH reg:1F:00 bit:17 reg:1F:00 bit:20 0 0 1 0 0 0 0 0 1 1 reg:1F:00 bit:21 Description reg:21:00 bits:0–7 0 x This programming selects the 8-symbol SFD as defined in the IEEE 802.15.4 standard, when operating at 850 kbps. 0 x This programming selects the 64-symbol SFD as defined in the IEEE 802.15.
UWB DWM100 User Manual 7.2.35 Register file: 0x22 – Reserved ID 0x22 Length (octets) Type Mnemonic - - - Description Reserved – this register file is reserved Register map register file 0x22 is reserved for future use. Please take care not to write to this register as doing so may cause the UWB DWM100 to malfunction. 7.2.
UWB DWM100 User Manual 7.2.36.2 ID 23:02 Sub-Register 0x23:02 – AGC_CTRL1 Length (octets) 2 Type Mnemonic RW AGC_CTRL1 Description AGC Control #1 Register file: 0x23 –AGC configuration and control, sub-register 0x02 is a 16-bit control register for the measurement function of the AGC.
UWB DWM100 User Manual Register file: 0x23 –AGC configuration and control, sub-register 0x04 is a 16-bit tuning register for the AGC. The value here needs to change depending on the PRF. The values needed depending on the RXPRF configuration are given in Table 24 below. Please take care not to write other values to this register as doing so may cause the UWB DWM100 to malfunction. Table 24: Sub-Register 0x23:04 – AGC_TUNE1 values 7.2.36.
UWB DWM100 User Manual Register file: 0x23 –AGC configuration and control, sub-register 0x10 is a reserved register. Please take care not to write to this register as doing so may cause the UWB DWM100 to malfunction. Sub-Register 0x23:12 – AGC_TUNE3 7.2.36.7 ID 23:12 Length (octets) 2 Type Mnemonic RW AGC_TUNE3 Description AGC Tuning register 3 Register file: 0x23 –AGC configuration and control, sub-register 0x12 is a 16-bit tuning register for the AGC.
UWB DWM100 User Manual Field EDG1 Description of fields within Sub-Register 0x23:1E – AGC_STAT1 This 5-bit gain value relates to input noise power measurement. EDG1 can be used in conjunction with the EDV2 value to give a measure of the background in-band noise energy level. This might be used for an Energy Detect (ED channel scan) as part of implementing the IEEE 802.15.4 standard’s MLME-SCAN request primitive.
UWB DWM100 User Manual OFFSET in Register 0x24 0x00 0x04 0x08 7.2.37.
UWB DWM100 User Manual 7.2.37.2 ID Sub-Register 0x24:04 EC_RXTC Length (octets) 24:04 4 Type Mnemonic RO EC_RXTC Description External clock synchronisation counter captured on RMARKER. Register file: 0x24 – External Synchronisation Control, sub-register 0x04 is the External clock synchronisation counter value captured on RMARKER, EC_RXTC. The EC_RXTC register is used to timestamp the received packet with respect to the external clock, see section 6.1.
UWB DWM100 User Manual Field Description of fields within Sub-Register 0x24:08 EC_GOLP OFFSET_EXT This register contains the 1 GHz count from the arrival of the RMARKER and the next edge of the external clock. See section 6.1.3 – One Shot Receive Synchronisation (OSRS) Modefor reg:24:08 details of its use. bits: 5:0 7.2.
UWB DWM100 User Manual Sub-Index Description of fields within Register file: 0x25 – Accumulator CIR memory Field CIR[1015].real.hi8 4061 reg:25:FDD 4062 CIR[1015].imag.lo8 reg:25:FDE CIR[1015].imag.
UWB DWM100 User Manual MSGP0 - MSGP1 - MSGP2 - MSGP3 - MSGP4 - MSGP5 - MSGP6 - MSGP7 - MSGP8 REG:26:00 – GPIO_MODE – GPIO Mode Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The fields of the GPIO_MODE register identified above are individually described below: Field MSGP0 reg:26:00 bits:7,6 MSGP1 reg:26:00 bits:9,8 MSGP2 reg:26:00 bits:11,10 MSGP
UWB DWM100 User Manual Field MSGP4 reg:26:00 bits:15,14 MSGP5 reg:26:00 bits:17,16 MSGP6 reg:26:00 bits:19,18 MSGP7 reg:26:00 bits:21,20 MSGP8 reg:26:00 bits:23,22 7.2.39.2 ID 26:04 Description of fields within Sub-Register 0x26:00 – GPIO_MODE Mode Selection for GPIO4/EXTPA. Allowed values are: 00: The pin operates as GPIO4– This is the default (reset) state. 01: The pin operates as the EXTPA output. 10: Reserved. Do not select this value. 11: Reserved. Do not select this value.
UWB DWM100 User Manual Register file: 0x26 – GPIO control and status, sub-register 0x08 is the GPIO Direction Control Register, GPIO_DIR. The GPIO_DIR register applies to the GPIO pins when they are selected to operate as GPIOs via the GPIO_MODE register. It contains a bit for each GPIO to individually configure that GPIO as an input or an output. The register is designed to allow software to change the direction of a single pin without knowing the settings needed for other pins.
UWB DWM100 User Manual Field GDP7 Description of fields within Sub-Register 0x26:08 – GPIO_DIR Direction Selection for the GPIO7. (See GDP0). bit:11 GDM4 Mask for setting the direction of GPIO4. (See GDM0). bit:12 GDM5 Mask for setting the direction of GPIO5. (See GDM0). bit:13 GDM6 Mask for setting the direction of GPIO6. (See GDM0). bit:15 GDM7 Mask for setting the direction of GPIO7. (See GDM0). reg:26:08 bit:15 GDP8 Direction Selection for GPIO8. (See GDP0).
UWB DWM100 User Manual The fields of the GPIO_DOUT register identified above are individually described below: Field GOP0 reg:26:0C bit:0 GOP1 Description of fields within Sub-Register 0x26:0C – GPIO_DOUT Bits marked ‘-’ are reserved and should be written as zero. Output state setting for the GPIO0 output. Reading this bit shows the current setting for GPIO0. Value 1 = logic 1 voltage high output and, value 0 = logic 1 voltage low output.
UWB DWM100 User Manual Register file: 0x26 – GPIO control and status, sub-register 0x10 is the GPIO interrupt enable register. The GPIO_IRQE register allows a GPIO input pin to be selected as an interrupt source into the UWB DWM100.
UWB DWM100 User Manual Register file: 0x26 – GPIO control and status, sub-register 0x14 is the GPIO interrupt sense selection register. The GPIO_ISEN register acts to set the state/event that gives rise to a GPI interrupt.
UWB DWM100 User Manual Register file: 0x26 – GPIO control and status, sub-register 0x18 is the GPIO interrupt mode selection register. Assuming that the GPIO is an input and enabled as an interrupt via the GPIO_IRQE register, then this GPIO_IMODE register acts to select whether the interrupt is level sensitive or edge triggered. The GPIO_IMODE register contains a bit for each GPIO pin to allow each to be individually configured.
UWB DWM100 User Manual register overrides the GPIO_ISEN register to select both edges as which edge triggers the interrupt. The GPIO_IBES register contains a bit for each GPIO pin to allow each to be individually configured.
UWB DWM100 User Manual sensitive interrupts are latched, if the active level persists, then clearing the latch will be ineffective, since the interrupt will occur again immediately.
UWB DWM100 User Manual de-bounce filter is active when a state change of the GPIO input needs to persist for two cycles of this clock before it will be seen by the interrupt handling logic.
UWB DWM100 User Manual GRAWP8 GRAWP7 GRAWP6 GRAWP5 GRAWP4 GRAWP3 GRAWP2 GRAWP1 GRAWP0 REG:26:28 – GPIO_RAW – GPIO raw state 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 The bits of the GPIO_IDBE register identified above are individually described below: Field GRAWP0 Description of fields within Sub-Register 0
UWB DWM100 User Manual OFFSET in Register 0x27 0x06 0x08 0x20 0x24 0x26 0x2C 7.2.40.
UWB DWM100 User Manual Data Rate 6.8 Mbps 850 kbps 110 kbps DWSFD TNSSFD RNSSFD SFD_LENGTH reg:1F:00 bit:17 reg:1F:00 bit:20 0 1 1 0 1 0 reg:1F:00 bit:21 0 1 0 Description reg:21:00 bits:0–7 x When the UWB DWM100 is operating at 6.8 Mbps, this programming selects the standard IEEE 8- symbol SFD which gives sufficient robustness since the data is already the weakest part of theframe. 16 The standard IEEE 8-symbol SFD is weaker than data at 850 kbps.
UWB DWM100 User Manual Table 22: Other possible SFD sequence configurations Data Rate 850 kbps 110 kbps 850 kbps 6.8 Mbps or 850 kbps 110 kbps DWSFD TNSSFD RNSSFD SFD_LENGTH reg:1F:00 bit:17 reg:1F:00 bit:20 0 0 1 0 0 0 0 0 1 1 reg:1F:00 bit:21 Description reg:21:00 bits:0–7 0 x This programming selects the 8-symbol SFD as defined in the IEEE 802.15.4 standard, when operating at 850 kbps. 0 x This programming selects the 64-symbol SFD as defined in the IEEE 802.15.
UWB DWM100 User Manual 7.2.40.3 ID 27:04 Sub-Register 0x27:04 – DRX_TUNE1a Length (octets) 2 Type Mnemonic RW DRX_TUNE1a Description Digital Tuning Register 1a Register file: 0x27 – Digital receiver configuration, sub-register 0x04 is a 16-bit tuning register. The value here needs to change depending on the RXPRF configuration. The values needed are given in Table 31 below. Please take care not to write other values to this register as doing so may cause the UWB DWM100 to malfunction.
UWB DWM100 User Manual 7.2.40.5 ID 27:08 Sub-Register 0x27:08 – DRX_TUNE2 Length (octets) 4 Type Mnemonic Description RW DRX_TUNE2 Digital Tuning Register 2 Register file: 0x27 – Digital receiver configuration, sub-register 0x08 is a tuning register. The value here needs to change depending on a number of parameters. The values needed are given in Table 33 below. Please take care not to write other values to this register as doing so may cause the UWB DWM100 to malfunction.
UWB DWM100 User Manual 7.2.40.7 ID 27:20 Sub-Register 0x27:20 – DRX_SFDTOC Length (octets) 2 Type Mnemonic RW DRX_SFDTOC Description SFD detection timeout count Register file: 0x27 – Digital receiver configuration, sub-register 0x20 is used to set the 16-bit SFD detection timeout counter period, in units of preamble symbols. The SFD detection timeout starts running as soon as preamble is detected.
UWB DWM100 User Manual period expires then the timeout will act to abort the reception currently in progress, and set the RXPTO event status bit in Register file: 0x0F – System Event Status Register. In cases where a response is expected at a particular time, this timeout can be used to flag that the expected response is not starting on time and hence to turn off the receiver earlier than would otherwise be the case, (i.e. if just employing the frame wait timeout).
UWB DWM100 User Manual 7.2.40.11 ID 27:28 Sub-Register 0x27:28 – DRX_CAR_INT Length (octets) 2 Type Mnemonic Description RO DRX_CAR_INT Carrier Recovery Integrator Register Register file: 0x27 – Digital receiver configuration, sub-register 0x28 is a read-only 21 bit register. The UWB DWM100 receiver needs to compensate for frequency offsets between the timing references at thetransmitting device and itself to successfully receive a packet.
UWB DWM100 User Manual Sub-Register 0x27:2C – RXPACC_NOSAT 7.2.40.12 ID Length Type (octets) 27:2C 2 RO Mnemonic Description RXPACC_NOSAT Digital debug register. Unsaturated accumulated preamble symbols. Register file: 0x27 – Digital receiver configuration, sub-register 0x2C is a read-only debug value containing a count of accumulated preamble symbols without saturation. Note that the accumulated SFD symbols minus two (two SFD symbols are always ignored in the receiver) are also included. 7.2.
UWB DWM100 User Manual TXRXSW REG:28:00 – RF_CONF – RF Configuration Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 - LDOFEN PLLFEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 TXFEN 0 0 0 0 0 0 0 0 0 0 0 0 0 Definition of the bit fields within Sub-Register 0x28:00 – RF_CONF Description of fields within Sub-Register 0x28:00 – RF_CONF Field Reserved These fields are reserved, and should not be set to 1 (may be overwritten with 0).
UWB DWM100 User Manual 7.2.41.3 ID 28:0B Sub-Register 0x28:0B– RF_RXCTRLH Length (octets) 1 Type Mnemonic RW RF_RXCTRLH Description Analog RX Control Register Register file: 0x28 – Analog RF configuration block, sub-register 0x0B is an 8-bitcontrol register for the receiver. The value here needs to be set depending on the RX channel selected by the RX_CHAN configuration in Register file: 0x1F – Channel Control. The values required are given in Table 37.
UWB DWM100 User Manual REG:28:0C – RF_TXCTRL – Transmitter Analog Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TXMQ TXMTUNE 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 Definition of the bit fields within Sub-Register 0x28:0C– RF_TXCTRL: Field Reserved Description of fields within Sub-Register 0x28:0C– RF_TXCTRL These fields are reserved. Program only as directed in Table 38.
UWB DWM100 User Manual Field CPLLLOCK Description of fields within Sub-Register 0x28:2C – RF_STATUS Clock PLL Lock status. This is a READ ONLY status flag. CPLLLOCK indicates that the digital clock PLL is locked. Note: The PLLLDT bit in Register file 0x24:00 –EC_CTRL should be set to ensure reliable operation of this CPLLLOCK bit. reg:28:2C bit:0 Clock PLL Low flag status bit. This indicates PLL is running a little lower than its target frequency, which may be an early indication of lock issues.
UWB DWM100 User Manual 7.2.42 Register file: 0x29 – Reserved ID 0x29 Length (octets) Type Mnemonic - - - Description Reserved – this register file is reserved Register file: 0x29 – Reserved is reserved. Please take care not to write to this register as doing so may cause the UWB DWM100 to malfunction. 7.2.
UWB DWM100 User Manual Definition of the bit fields within Sub-Register 0x2A:00 – TC_SARC: Field SAR_CTRL Description of fields within Sub-Register 0x2A:00 – TC_SARC Writing 1 sets SAR enable and writing 0 clears the enable. The enable should set for a minimum of 2.5 µs to allow the SAR time to complete its reading. reg:2A:00 bit:0 Bits marked ‘-’ in register 0x2A:00 are reserved and should always be written as zero to avoid any malfunction of the UWB DWM100.
UWB DWM100 User Manual Field SAR_LTEMP Description of fields within Sub-Register 0x2A:03 – TC_SARL Latest SAR reading for Temperature level. The 8-bit value reported here is the temperature reading from the SAR A/D sampling of the UWB DWM100 internal temperature sensor. The LSB is approximately 0.8 °C. The value can be converted to an actual voltageby employing the formula: reg:2A:03 bits:15–8 Temperature (°C )= ( (SAR_LTEMP – OTP_READ(Vtemp @ 23°C) ) x 1.
UWB DWM100 User Manual Sub-Register 0x2A:08 – TC_PG_CTRL 7.2.43.
UWB DWM100 User Manual The reference value required for temperature bandwidth compensation is the contents of the TC_PG_STATUS register, PG_DELAY_CNT, which represents a counter that increments with every pulse generated by the UWB DWM100 IC’s internal pulse generator. This count value will vary inversely with the TC_PGDELAY value – if the delay between pulses increases, the number of pulses within a given timeframe will decrease, and vice versa.
UWB DWM100 User Manual Register file: 0x2A – Transmitter Calibration block, sub-register 0x0C is an 8-bit configuration register for use in setting the transmitter into continuous wave (CW) mode. This CW mode is employed during the crystal trimming operation which may be done at module manufacturing stage as part of calibrating the crystal oscillator’s operating frequency. At all other times, for normal operation, the value in this register should be left in its default power on value of 0x00.
UWB DWM100 User Manual Register file: 0x2B – Frequency synthesiser control block, sub-register 0x00 is a reserved register. Please take care not to write to this area as doing so may cause the UWB DWM100 to malfunction. 7.2.44.2 ID 2B:07 Sub-Register 0x2B:07 – FS_PLLCFG Length (octets) 4 Type Mnemonic RW FS_PLLCFG Description Frequency synthesiser – PLL configuration Register file: 0x2B – Frequency synthesiser control block, sub-register 0x07 is the PLL configuration register.
UWB DWM100 User Manual 7.2.44.4 ID 2B:0C Sub-Register 0x2B:0C – FS_RES2 Length (octets) 2 Type Mnemonic RW FS_RES2 Description Frequency synthesiser – Reserved area 2 Register file: 0x2B – Frequency synthesiser control block, sub-register 0x0C is a reserved area. Please take care not to write to this area as doing so may cause the UWB DWM100 to malfunction. 7.2.44.
UWB DWM100 User Manual 7.2.45 Register file: 0x2C – Always-on system control interface ID 0x2C Length (octets) Type - - Mnemonic AON Description Always on system control interface block Register map register file 0x2C is the Always-On system control block, (AON). The AON block contains a low-power configuration array that remains powered-up as long as power (from the battery, for example) is supplied to the UWB DWM100 via the VDDAON pin.
UWB DWM100 User Manual - - - - - ONW_RX ONW_RAD - ONW_LEUI - PRES_SLEE ONW_L64 ONW_LDC - ONW_LLD ONW_LLDE REG:2C:00 – AON_WCFG – AON Wake-up Configuration register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Definition of the bit fields within Sub-Register 0x2C:00 – AON_WCFG: Field ONW_RADC reg:2C:00 bit:0 ONW_RX reg:2C:00 bit:1 reg:2C:00 bits:[various] ONW_LEUI reg:2C:00 bit:3 ONW_LDC reg:2C:00 bit:6 ONW_L64P
UWB DWM100 User Manual Description of fields within Sub-Register 0x2C:00 – AON_WCFG Preserve Sleep. This bit determines what the UWB DWM100 does with respect to the ARXSLP and ATXSLP sleep controls in Sub-Register 0x36:04 – PMSC_CTRL1 after a wake-up event. When the PRES_SLEEP bit is set to 1 these sleep controls are not cleared upon wakeup, so that the UWB DWM100 can return to sleep after a failed reception (say). This needs to be set for correct operation of call Low-Power Listening. See section 4.
UWB DWM100 User Manual Field SAVE reg:2C:02 bit:1 UPL_CFG reg:2C:02 bit:2 DCA_READ reg:2C:02 bit:3 – reg:2C:02 bits:6–4 DCA_ENAB reg:2C:02 bit:7 Description of fields within Sub-Register 0x2C:02 – AON_CTRL When this bit is set the UWB DWM100 will copy the user configurations from the host interface register set into the AON memory. It will then proceed to upload the AON block configurations. The SAVE bit will auto clear when this command is executed. Upload the AON block configurations to the AON.
UWB DWM100 User Manual Table 46: Configurations maintained in the AON Memory Array Configuration Register Configuration Register Register file: 0x03 – PAN Identifier and Short Address Sub-Register 0x28:0B– RF_RXCTRLH Register file: 0x04 – System Configuration Sub-Register 0x28:0C– RF_TXCTRL Register file: 0x08 – Transmit Frame Control 2 Sub-Register 2A:0B – TC_PGDELAY Register file: 0x0E – System Event Mask Register Sub-Register 0x2B:07 – FS_PLLCFG Register file: 0x1D – SNIFF Mode3 Sub-Register
UWB DWM100 User Manual 7.2.45.3 ID 2C:03 Sub-Register 0x2C:03 – AON_RDAT Length (octets) 1 Type Mnemonic Description RW AON_RDAT AON Direct Access Read Data Result Register file: 0x2C – Always-on system control, sub-register 0x03 is an 8-bit register used to return the result of a direct access read of a location in the AON memory array.
UWB DWM100 User Manual 7.2.45.5 ID 2C:04 Sub-Register 0x2C:04 – AON_ADDR Length (octets) 1 Type Mnemonic RW AON_ADDR Description AON Direct Access Address Register file: 0x2C – Always-on system control, sub-register 0x04 is an 8-bit register used to specify the address for a direct access read of the AON memory array. The read is initiated using the DCA_READ control bit in Sub-Register 0x2C:02 – AON_CTRL and the read result is returned in Sub-Register 0x2C:03 – AON_RDAT. 7.2.45.
UWB DWM100 User Manual Field WAKE_PIN Description of fields within Sub-Register 0x2C:06 – AON_CFG0 Wake using WAKEUP pin. This configuration bit enables the WAKEUP line to bring the UWB DWM100 out of SLEEP or DEEPSLEEP states into operational mode. By default the reg:2C:06 WAKE_PIN configuration is 1 enabling the WAKEUP line as a wake-up signal. Setting the bit:1 WAKE_PIN configuration bit to 0 will mean that the WAKEUP line cannot wake the UWB DWM100 from SLEEP or DEEPSLEEP.
UWB DWM100 User Manual NOTE: There are three mechanisms to wake the UWB DWM100: using the WAKEUP line when the WAKE_PIN configuration is 1, using SPICSn when the WAKE_SPI configuration is 1, and using the sleep timer when the WAKE_CNT configuration is 1 and the sleep counter is enabled via the SLEEP_CEN bit in © 2021 B. Thermal Solutions srl Tel +390717822026 Mail info@brandoni.com Version 2.
UWB DWM100 User Manual Sub-Register 0x2C:0A – AON_CFG1. If none of these wakeup mechanisms are enabled and the UWB DWM100 is put into DEEPSLEEP mode then there will be no way to take the IC out of sleep except byremoving power at the VDDAON pin, (and short it to 0 volts to hasten the power down of the IC). Sub-Register 0x2C:0A – AON_CFG1 7.2.45.
UWB DWM100 User Manual Field Description of fields within Sub-Register 0x2C:0A – AON_CFG1 The recommended operating procedure for this is then using this is then is to: (a) Ensure that the SPI operating frequency is set < 3MHz. (During procedure the system uses the 19.2 MHz XTI clock which will not support higher SPI data rates). (b) Set this LPOSC_CAL bit to 1, and upload it into the AON block by toggling the UPL_CFG bit (in AON_CTRL) to 1 and back to 0.
UWB DWM100 User Manual OFFSET in Register 0x2D 0x06 0x08 0x0A 0x0E 0x12 7.2.46.1 ID 2D:00 Mnemonic OTP_CTRL OTP_STAT OTP_RDAT OTP_SRDAT OTP_SF Description OTP Control OTP Status OTP Read Data OTP SR Read Data OTP Special Function Sub-Register 0x2D:00 – OTP_WDAT Length (octets) 4 Type Mnemonic RW OTP_WDAT Description OTP Write Data Register file: 0x2D – OTP Memory Interface, sub-register 0x00 is a 32-bit register.
UWB DWM100 User Manual Sub-Register 0x2D:06 – OTP_CTRL 7.2.46.3 ID Length (octets) 2D:06 2 Type Mnemonic RW OTP_CTRL Description OTP Control Register file: 0x2D – OTP Memory Interface, sub-register 0x06 is a 16-bit register used to control the operation of the OTP memory through the process of reading and writing.
UWB DWM100 User Manual Field LDELOAD reg:2D:06 bit:15 Description of fields within Sub-Register 0x2D:06 – OTP_CTRL This bit forces a load of LDE microcode. The LDE algorithm is responsible for generating an accurate RX timestamp and calculating some signal quality statistics related to the received packet. See Register file: 0x2E – Leading Edge Detection Interface for more details about the LDE functionality.
UWB DWM100 User Manual Field - Description of fields within Sub-Register 0x2D:08 – OTP_STAT Reserved. Bits marked ‘-’ are reserved. reg:2D:00 bits:various 7.2.46.5 ID 2D:0A Sub-Register 0x2D:0A – OTP_RDAT Length (octets) 4 Type Mnemonic R OTP_RDAT Description OTP Read Data Register file: 0x2D – OTP Memory Interface, sub-register 0x0A is a 32-bit register. The data value read from an OTP location will appear here after invoking the OTP read function.
UWB DWM100 User Manual Field OPS_KICK reg:2D:12 bit:0 LDO_KICK reg:2D:12 bit:1 OPS_SEL reg:2D:12 bits:6,5 Description of fields within Sub-Register 0x2D:08 – OTP_STAT This bit when set initiates a load of the operating parameter set selected by the OPS_SEL configuration below. (This control is in the OTP block because the parameter sets are in OTP memory during their development, only moving to ROM for the production IC).
UWB DWM100 User Manual Set Description 01 – Tight This operating parameter set maximises the operating range of the system. However this performance optimization again comes at a cost, which is that the total crystal offset between transmitter and receiver must be kept very tight, at or below about 1 ppm. This might be done, for example, by using very high quality 0.5 ppm TCXOs in both the transmitter and the receiver.
UWB DWM100 User Manual Register file: 0x2E – Leading Edge Detection Interface, sub-register 0x0000 is a 16-bit status register reporting the threshold that was used to find the first path. This threshold is calculated based on an estimate of the noise made during the LDE algorithm’s analysis of the accumulator data. This threshold report may be of diagnostic interest in certain circumstances. 7.2.47.
UWB DWM100 User Manual 7.2.47.4 ID 2E:1002 Sub-Register 0x2E:1002 – LDE_PPAMPL Length (octets) 2 Type Mnemonic RO LDE_PPAMPL Description LDE Peak Path Amplitude Register file: 0x2E – Leading Edge Detection Interface, sub-register 0x1002, is the LDE Peak Path Amplitude (LDE_PPAMPL) register.
UWB DWM100 User Manual Table 50: Sub-Register 0x2E:1806– LDE_CFG2 values 7.2.47.
UWB DWM100 User Manual RX_PCODE9 configuration LDE_REPC value to set RX_PCODE configuration LDE_REPC value to set 9 0x28F4 21 0x3AE0 10 0x3332 22 0x3850 11 0x3AE0 23 0x30A2 12 0x3D70 24 0x3850 NB: When operating at 110 kbps the unsigned values in Table 51 have to be divided by 8, (right shifted 3, shifting zeroes into the high order bits), before programming into Sub-Register 0x2E:2804 – LDE_REPC. 7.2.
UWB DWM100 User Manual Sub-Register 0x2F:00 – Event Counter Control 7.2.48.1 Length ID (octets) 2F:00 4 Type Mnemonic SRW Description EVC_CTRL Event Counter Control Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x00 is the event counter control register.
UWB DWM100 User Manual REG:2F:04 – EVC_PHE – PHR Error Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - EVC_PHE - - - 0 The fields of the EVC_PHE register are described below: Field EVC_PHE reg:2F:04 bits:11–0 - Description of fields within Sub-Register 0x2F:04 – PHR Error Counter PHR Error Event Counter. The EVC_PHE field is a 12-bit counter of PHY Header Errors.
UWB DWM100 User Manual REG:2F:08 – EVC_FCG – Frame Check Sequence Good Event Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - EVC_FCG - - - 0 The bits of the EVC_FCG register are described below: Field EVC_FCG reg:2F:08 bits:11–0 - Description of fields within Sub-Register 0x2F:08 – FCS Good Counter Frame Check Sequence Good Event Counter. The EVC_FCG field is a 12-bit counter of the frames received with good CRC/FCS sequence.
UWB DWM100 User Manual REG:2F:0C – EVC_FFR – Frame Filter Rejection Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - EVC_FFR - - - 0 The bits of the EVC_FFR register are described below: Field EVC_FFR reg:2F:0C bits:11–0 - Description of fields within Sub-Register 0x2F:0C – Frame Filter Rejection Counter Frame Filter Rejection Event Counter. The EVC_FFR field is a 12-bit counter of the frames rejected by the receive frame filtering function.
UWB DWM100 User Manual REG:2F:10 – EVC_STO – SFD Timeout Error Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - EVC_STO - - - 0 The bits of the EVC_STO register are described below: Field EVC_STO reg:2F:10 bits:11–0 - Description of fields within Sub-Register 0x2F:10 – SFD Timeout Error Counter SFD timeout errors Event Counter. The EVC_STO field is a 12-bit counter of SFD Timeout Error events.
UWB DWM100 User Manual Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x14 is the RX Frame Wait Timeout Event Counter. REG:2F:14 – EVC_FWTO – RX Frame Wait Timeout Event Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - EVC_FWTO - - - 0 The bits of the EVC_FWTO register are described below: Field Description of fields within Sub-Register 0x2F:14 – RX Frame Wait Timeout Event Counter EVC_FWTO RX Frame Wait Timeout Event Counter.
UWB DWM100 User Manual Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x18 is the Half Period Warning Counter. REG:2F:18 – EVC_HPW – Half Period Warning Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - EVC_HPW - - - 0 The bits of the EVC_HPW register are described below: Field EVC_HPW reg:2F:18 bits:11–0 - Description of fields within Sub-Register 0x2F:18 – Half Period Warning Counter Half Period Warning Event Counter.
UWB DWM100 User Manual 7.2.48.14 ID 2F:1C Sub-Register 0x2F:1C – EVC_RES1 Length (octets) 8 Type RW Mnemonic EVC_RES1 Description Digital Diagnostics Reserved Area 1 Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x1C is a reserved register. Please take care not to write to this register as doing so may cause the UWB DWM100 to malfunction. 7.2.48.
UWB DWM100 User Manual 7.2.49 Register files: 0x30 to 0x35 – Reserved ID 0x30 to 0x35 Length (octets) Type Mnemonic - - - Description Reserved – these register files are reserved Register map register files 0x30 through 0x35 are reserved for future use. Please take care not to write to these registers as doing so may cause the UWB DWM100 to malfunction. 7.2.
UWB DWM100 User Manual - - - - - - - - - SYSCLKS - RXCLKS - TXCLKS - FACE - ADCCE - GPDRN GPDCE GPRN GPCE AMCE SOFTRESET KHZCLKEN REG:36:00 – PMSC_CTRL0 – PMSC Control Register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 The fields of the PMSC_CTRL0 register identified above are individually described below: Field SYSCLKS reg:36:00 bits:1,0 Description of fields within Sub-Re
UWB DWM100 User Manual Field FACE reg:36:00 bit:6 ADCCE reg:36:00 bit:10 AMCE reg:36:00 bit:15 GPCE reg:36:00 bit:16 GPRN reg:36:00 bit:17 GPDCE reg:36:00 bit:18 Description of fields within Sub-Register 0x36:00 – PMSC_CTRL0 Force Accumulator Clock Enable. In normal operation this bit should be set to 0 to allow the PMSC to control the accumulator clock as necessary for normal receiver operation.
UWB DWM100 User Manual Field Description of fields within Sub-Register 0x36:00 – PMSC_CTRL0 SOFTRESET These four bits reset the IC TX, RX, Host Interface and the PMSC itself, essentially allowing a reset of the IC under software control. These bits should be cleared to zero to force a reset reg:36:00 and then returned to one for normal operation.
UWB DWM100 User Manual Field ATXSLP reg:36:04 bit:11 ARXSLP reg:36:04 bit:12 SNOZE reg:36:04 bit:13 SNOZR reg:36:04 Description of fields within Sub-Register 0x36:04 – PMSC_CTRL1 After TX automatically Sleep. If this bit is set then the UWB DWM100 will automatically transition into SLEEP or DEEPSLEEP mode after transmission of a frame has completed so long as thereare no unmasked interrupts pending.
UWB DWM100 User Manual Field Description of fields within Sub-Register 0x36:04 – PMSC_CTRL1 KHZCLKDIV Kilohertz clock divisor. This field specifies a clock divider designed to give a kilohertz range reg:36:04 clock that is used in the UWB DWM100 for the LED blink functionality and also for the GPIO bits:31–26 de- bounce functionality. The input to the kHz divider is the 19.2 MHz XTI clock (which is the raw 38.4 MHz XTAL ÷ 2).
UWB DWM100 User Manual Sub-Register 0x36:10 – PMSC_RES2 7.2.50.5 ID Length (octets) 36:10 22 Type Mnemonic RW PMSC_RES2 Description PMSC reserved area 2 Register file: 0x36 – Power Management and System Control, sub-register 0x10 is a reserved register. Please take care not to write to this register as doing so may cause the UWB DWM100 to malfunction. Sub-Register 0x36:26 – PMSC_TXFSEQ 7.2.50.
UWB DWM100 User Manual Register file: 0x36 – Power Management and System Control, sub-register 0x28 is a 32-bit LED control register.
UWB DWM100 User Manual 8 UWB DWM100 Calibration The operating characteristics and performance of the UWB DWM100 is dependent on the IC itself and on itsexternal circuitry and on its operating environment. To give optimum performance it is necessary to calibrate the IC to account for factors which affect its operation. Some calibration parameters are dependent solely on natural variations that occur within the silicon of the IC during its manufacture.
UWB DWM100 User Manual by switching in internal capacitor banks in parallel with the external loading capacitors associated with the chosen crystal. This trimming can be used to reduce the crystal initial frequency error and to compensate for temperature and aging drift, if required. The amount of trimming is programmable through Sub-Register 0x2B:0E – FS_XTALT. 8.1.1 Calibration Method The 38.
UWB DWM100 User Manual Enable CW mode: Set Sub-Register 0x2A:0C – TC_PGTEST to 0x13 to enable Continuous Wave (CW) Test Mode. Set trim register to mid-range setting, e.g. 0x0F, whilst maintaining the required reserved values in the most significant bits of the register, see reserved field notes for Sub-Register 0x2B:0E – FS_XTALT: Set Sub-Register 0x2B:0E – FS_XTALT to 0x6F. While monitoring the CW frequency, adjust the trim register (5 bits) until the desired frequency is obtained.
UWB DWM100 User Manual designed such that if the transmit power is within mean power spectral density limits then it will automatically be within peak power limits although this should be checked during product design verification. As this is an analog circuit, there will be some variation in output power levels from IC to IC and hence UWB DWM100 should be calibrated and the calibrated power setting stored in the OTP memory.
UWB DWM100 User Manual 1. Write the correct value for the selected channel to Sub-Register 0x28:0C– RF_TXCTRL, e.g. 0x045CA0 for channel 2. 2. Write an appropriate value for TX_POWER to Register file: 0x1E – Transmit Power Control, e.g. for channel 2 at 16 MHz PRF, write 0x75757575. See Table 20. 3. Write the value for the selected channel to Sub-Register 0x2B:07 – FS_PLLCFG, e.g. 0x08400508 for channel 2, see Table 43: Sub-Register 0x2B:07 – FS_PLLCFG values. 4.
UWB DWM100 User Manual In UWB DWM100 applications using transmit power calibration, the calibrated TX_POWER value should be read by the application from OTP memory as part of setup and programmed into Register file: 0x1E – Transmit Power Control. This register is preserved in the AON memory as long as the IC is powered. This facilitates theuse of this value when the IC wakes up from SLEEP or DEEPSLEEP modes. 8.2.1.
UWB DWM100 User Manual To calibrate the antenna delay, range is measured at a known distance using 2 UWB DWM100 systems. Antennadelay is adjusted until the known distance and reported range agree. The antenna delay can be stored in OTP memory. There is a Transmitter Antenna Delay and a Receiver Antenna Delay. The Transmitter Antenna Delay is used to account for the delay between the internal digital timestamp of the RMARKER (at the start of the PHR, see 3.
UWB DWM100 User Manual Channel PRF (MHz) Calibration Separation (m) 2 3 3 4 5 5 7 64 16 64 16/64 16 64 16/64 8.14 11.47 7.24 8.68 7.94 5.01 5.34 The combined transmitter and receiver antenna delay is calibrated by choosing a distance (or receive power) for calibration and modifying the receiver antenna delay until the range reading given by the device is correct. A method to calibrate combined receiver and transmitter antenna delay is as follows: 1.
UWB DWM100 User Manual 9 Operational design choices when employing the UWB DWM100 This chapter discusses some of the operational considerations to using the UWB DWM100 in general RF transceiverapplications, with some additional focus on its use in real-time location systems, (RTLS). 9.1 Operating range The operational range of the UWB DWM100 depends on the frame data rate and the preamble length. In free- space, line-of-sight (LOS), this may vary from 60 m at the 6.
UWB DWM100 User Manual good long-range performance and allows its accurate determination of the first path arrival time for the RX timestamp. The preamble sequence used at all data rates is the same, i.e. it does not depend on the chosen data rate. The preamble sequence length, (i.e. the number of symbol intervals for which it is repeated), has a significant effect on the operational range and the accuracy of timestamps.
UWB DWM100 User Manual This 18% air utilisation comes into play when deploying a population of RTLS tags periodically blinking. Table 58 gives some indications of the blink transmission rates corresponding to some typical data rate / preamble length combinations and with a minimum 12-byte blink frame sending the Tag ID. The number of transmissions that can be made within the 18% air-utilisation is highest for the shortest duration frame (64symbol preamble and 6.
UWB DWM100 User Manual 9.7 Location schemes This part of the discussion on operational design choices relates to RTLS location schemes. Some of the ideas and points discussed may be more generally applicable. In general to locate a mobile node measurements are needed to be referenced to a number of fixed known location “anchor” nodes.
UWB DWM100 User Manual In an RTLS the accuracy of the UWB DWM100’s RX timestamps can give sub 10 cm resolution. Note, however thatthe geometry of anchors with respect to the tag can smear the accuracy of the calculated location when individual measurements are combined. Having additional anchors in range of the tag can offset this if it allows the system to select anchors with best geometry and best receive signal quality with respect to the tag being located. 9.
UWB DWM100 User Manual Name Slotted listening Sniff mode Description periodically sending the poll and listening for a short time for a response that does not come. In this technique all devices listen for a periodic beacon from which slots are timed and then listen in their assigned slot for a message. The amount of slots and the amount of listening is dependent on the network size and required response times. The frequency of listening for beacons depends on the super-frame size and the clock drift.
UWB DWM100 User Manual 10 APPENDIX 1: The IEEE 802.15.4 UWB physical layer This appendix gives an introduction to the modulation scheme and frame structure of the UWB physical layer as specified in the IEEE 802.15.4 – 2011 standard and as implemented by the UWB DWM100 transceiver IC.This is useful in understanding the operation of the UWB DWM100 transceiver and its configuration options. 10.1 Frame structure overview The UWB communications are based around the transmission and reception of frames.
UWB DWM100 User Manual In addition the quarter symbol interval is sub-divided into 2, 4, or 8 sub-intervals and a pseudo random sequence used to determine both the burst shape and which of the sub-intervals are actually used for the burst transmission. This gives more immunity to interference and whitens the output spectrum allowing a higher signal power to be used in the transmitter. Forward error correction (FEC) is also included in the PHR and Data parts of the frame.
UWB DWM100 User Manual Table 60: Preamble parameters Mean PRF (MHz) #Chips Per Symbol Preamble Symbol Duration (ns) 16 nominal 496 993.59 64 nominal 508 1017.63 The standard defines PSR settings of 16, 64, 1024 and 4096. The UWB DWM100 supports these (although it will not receive frames with preamble length below 64 symbols) and in addition supports PSR settings of 128,256, 512, 1536 and 2048.
UWB DWM100 User Manual Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 R1 R0 L6 L5 L4 L3 L2 L1 L0 RNG EXT P1 P0 C5 C4 C3 C2 C1 C0 Frame Length Header Extension Ranging Packet Data Rate Preamble Duration SECDED Check Bits Figure 33: PHR bit assignment Figure 33 above shows the bits of the PHR. These are transmitted bit-0 first in time.
UWB DWM100 User Manual proximity with long preambles. This may mean that it is not possible to achieve the separation envisioned by the standard’s authors. The IEEE 802.15.4 UWB PHY standard includes a feature called dynamic preamble select (DPS) intended for use a security mechanism for two-way ranging, where devices switch to using one of the DPS specific preamble codes for the ranging exchange, and perhaps a different one for each direction of communication.
UWB DWM100 User Manual Frame Control Sequence Number Destination PAN Identifier Destination Address Source PAN Identifier Source Address Aux Security Header Frame Payload FCS 2 octets 1 octet 0 or 2 octets 0, 2 or 8 octets 0 or 2 octets 0, 2 or 8 octets 0, 5, 6 10 or 14 octets Variable number of octets 2 octets Figure 34: General MAC message format The MAC header is parsed by the UWB DWM100 as part of the frame filtering function to determine if its destination address matches the IC’s add
UWB DWM100 User Manual 11.2 The frame control field in the MAC header The frame control field is a two-octet (16-bit) field that begins every IEEE 802.15.4 MAC frame. Its role is to identify the frame type and indicate what components are incorporated in the remainder of the MAC header. Figure 35 shows the frame control this and identifies the sub-fields within it. These are described below.
UWB DWM100 User Manual beingsecured this processing must be done by the host system. For more detail on the IEEE 802.15.4 MAC security process please refer to the standard [1]. 11.2.3 Frame pending field This bit indicates that the sending device has more data for the recipient. The reader is referred to the standard [1] for the details of this MAC protocol. The UWB DWM100 receiver does not use the frame pending fieldin the receiver so it is up to the host software to handle it appropriately.
UWB DWM100 User Manual Table 63: Destination addressing mode field values Destination addressing mode (FC bits 11 & 10) Meaning 0, 0 No destination address or destination PAN ID is present in the frame 0, 1 Reserved The destination address field is a short (16-bit) address. The destination address field is an extended (64-bit) address. 1, 0 1, 1 11.2.7 Frame version field The frame version field (2-bits) specifies the version number of the frame.
UWB DWM100 User Manual transmittedframe. As each new frame is transmitted (not a re-transmission of an unacknowledged frame) the sequence number should be incremented by 1 (modulo-256) after it is used in the transmitted frame. 11.
UWB DWM100 User Manual 12 APPENDIX 3: Two-Way Ranging 12.1 Introduction This appendix is for information only and describes various methods of implementing a two-way ranging scheme between two nodes. The chosen two-way ranging algorithm is implemented by host system software and is not a feature of the UWB DWM100. The UWB DWM100 just provides the facilities for message time-stamping and precise control of messagetransmission times that enable these algorithms. See section 4.1.6 – RX Message timestamp, 3.
UWB DWM100 User Manual In this scheme the error in the measured Tprop is given by the following: 𝑒𝑟𝑟𝑜𝑟 = 𝑇̂ 𝑝𝑟𝑜𝑝 1 ≈ (𝑒 − 𝑒 ) × 𝑇 𝐴 𝑟𝑒𝑝𝑙𝑦 2 𝐵 −𝑇 𝑝𝑟𝑜𝑝 Table 65: Typical clock induced errors in SS-TWR time of flight estimation clock error 2 ppm 5 ppm 10 ppm 20 ppm 40 ppm 100 µs 0.1 ns 0.25 ns 0.5 ns 1 ns 2 ns 200 µs 0.2 ns 0.5 ns 1 ns 2 ns 4 ns 500 µs 0.5 ns 1.25 ns 2.5 ns 5 ns 10 ns 1 ms 1 ns 2.5 ns 5 ns 10 ns 20 ns 2 ms 2 ns 5 ns 10 ns 20 ns 40 ns 5 ms 5 ns 12.
UWB DWM100 User Manual 12.3 Double-sided Two-way Ranging 12.3.1 Using 4 messages Double-sided two-way ranging (DS-TWR), is an extension of the basic single-sided two-way ranging in which two round trip time measurements are used and combined to give a time-of-flight result which has a reduced error even for quite long response delays.
UWB DWM100 User Manual Both of the above schemes are denoted ASYMMETRIC because they do not require the reply times from each device to be the same. Using this scheme, the typical clock induced error is in the low picosecond range even with 20 ppm crystals. At these error levels the precision of determining the arrival time of the messages at each of the receivers is a more significant contributor to overall Tprop error than the clock-induced error.
UWB DWM100 User Manual As the difference in reply time of the two devices increases there is a linear increase in the error in the calculated time of flight which can approach 30 cm for a reply-time difference of 100 µs. Advantages Requires only simple mathematical operations to derive a result Drawbacks Reply times must be the same – this is difficult to achieve.
UWB DWM100 User Treply2C Tround1C Tround1B Treply2B Tround1A Tag TX Poll Treply2A RX RespA RX RespB RX RespC TX Final RMARKER TpropA TpropA TpropA time The Final message communicates the tag’s Tround and Treply times to the anchors, which each calculate the range to the tag as follows.
UWB DWM100 User 12.3.4.4 Infrastructure-less Peer-to-peer networks In the case of a peer-to-peer network of N mobile nodes where each node wants to find its distance to every other peer node as part of solving their relative location then this is ½N(N-1) distance measurements. For example, for a 5 node system, this is 10 distance measurements. With symmetric double-sided ranging this needs 3 messages per distance measurement.
UWB DWM100 User 13 APPENDIX 4: Abbreviations and acronyms Abbreviation Full Title Explanation AGC automatic gain control A scheme that automatically adjusts the gain of the UWB DWM100 receiverdepending on the power in the received signal ACK acknowledgement (frame) A frame sent by the UWB DWM100 in response to a received frame indicating successful reception. UWB DWM100 allows the automatic generation of such frames when appropriately configured.
UWB DWM100 User Abbreviation Full Title Explanation can no longer regulate correctly. UWB DWM100 uses a number of suchregulators.
UWB DWM100 User Abbreviation Full Title Explanation RMARKER ranging marker (start of PHR at antenna) Defined in the context of the IEEE802.15.4-2011 [1] standard. Defines the start of the PHR at the antenna in either transmit or receive RTLS real time location systems System intended to provide information on the location of various items in real-time.
UWB DWM100 User Abbreviation Full Title 38.4 MHz XTAL oscillator input ÷ 2) B. Thermal Solutions srl Tel +390717822026 Mail info@brandoni.com Explanation Version 2.
UWB DWM100 User 14 APPENDIX 5: References [1] IEEE 802.15.4-2011 or “IEEE Std 802.15.4™‐2011” (Revision of IEEE Std 802.15.4-2006). IEEE Standard for Local and metropolitan area networks – Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs). IEEE Computer Society Sponsored by the LAN/MAN Standards Committee. Available from http://standards.ieee.org/.
UWB DWM100 User REGULATORY INFORMATION USA Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
