Intel® 820 Chipset Design Guide July 2000 Order Number: 290631-004
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Contents 1 Introduction ................................................................................................................1-1 1.1 1.2 1.3 1.4 2 About This Design Guide ..............................................................................1-1 References....................................................................................................1-2 System Overview ..........................................................................................1-2 1.3.
2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 3 Advanced System Bus Design ..................................................................................3-1 3.1 3.2 3.3 3.4 iv System Bus Design ....................................................................................2-46 2.9.1 100/133 MHz System Bus .............................................................2-46 2.9.2 System Bus Ground Plane Reference ...........................................2-47 S.E.C.C.
3.5 3.6 4 Clocking .....................................................................................................................4-1 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 5 Clock Generation ..........................................................................................4-1 Component Placement and Interconnection Layout Requirements..............4-6 4.2.1 14.318 MHz Crystal to CK133 .........................................................4-6 4.2.2 CK133 to DRCG ..............................
Figures 1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 2-33 2-34 2-35 2-36 2-37 2-38 2-39 2-40 2-41 2-42 2-43 vi Intel® 820 Chipset Platform Performance Desktop Block Diagram ..............1-5 Intel® 820 Chipset Platform Performance Desktop Block Diagram (with ISA Bridge)...........................................................................................
2-44 2-45 2-46 2-47 2-48 2-49 2-50 2-51 2-52 2-53 2-54 2-55 2-56 2-57 2-58 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 BREQ0# Circuitry for DP Systems..............................................................2-53 HA7# Strapping Option Example Circuit (For Debug Purposes Only)........2-54 Host-Side IDE Cable Detection...................................................................2-57 Drive-Side IDE Cable Detection..
Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 4-4 4-5 4-6 4-7 5-1 5-2 6-1 6-2 viii Intel® 820 Chipset Platform Bandwidth Summary ........................................1-4 AGP 2X Data/Strobe Association .................................................................2-6 Placement Guidelines for Motherboard Routing Lengths .............................2-9 Copper Tab Area Calculation .......................................................
Revision History Revision -001 Description Initial Release. Date November 1999 • Added dual-processor schematics (Appendix B). -002 -003 -004 • Uni-processor schematics have been updated (Appendix A). See the schematic revision history page at the end of Appendix A for details. - The following update is not in the schematic revision history. Cap C249 (schematic page 9) has been changed from 0.022 uF to 0.047 uF. • Updated the text descriptions in the two paragraphs in Section 4.2.3, “MCH to DRCG”.
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1 Introduction
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Introduction Introduction 1 The Intel® 820 Chipset Design Guide provides design recommendations for systems using the Intel® 820 chipset. This includes motherboard layout and routing guidelines, system design issues and requirements, debug recommendations, and board schematics. The design recommendations should be used during system design. The guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board-related issues.
Introduction 1.2 References • Intel® 820 Chipset: Intel® 82820 Memory Controller Hub (MCH) Datasheet • • • • • • • • • • • • • 1.
Introduction configurable AC’97 audio and modem coder/decoders (codecs) instead of the traditional ISA devices. The ISA bus can be implemented through the use of the optional 82380AB PCI-ISA bridge. The Intel® 820 chipset contains two core components: the Memory Controller Hub (MCH) and the I/O Controller Hub (ICH). The MCH integrates the 133 MHz processor system bus controller, AGP 2.0 controller, 400 MHz Direct RDRAM controller and a high-speed hub interface for communication with the ICH.
Introduction I/O Controller Hub (ICH) The I/O Controller Hub provides the I/O subsystem with access to the rest of the system. Additionally, it integrates many I/O functions. The ICH integrates the following functions: • • • • • • • • • • • Upstream hub interface for access to the MCH 2 channel Ultra ATA/66 Bus Master IDE controller USB controller I/O APIC SMBus controller FWH interface (FWH Flash BIOS) LPC interface AC’97 2.1 interface PCI 2.
Introduction 1.3.3 System Configuration The following figures show typical platform configurations using the Intel® 820 chipset. Figure 1-1. Intel® 820 Chipset Platform Performance Desktop Block Diagram Processor 4X AGP Graphics Controller AGP 2.0 82820 Memory Controller Hub (MCH) Main Memory Hub Interface PCI Slots 4 IDE Drives PCI Bus 2 USB Ports AC'97 Codec(s) (optional) Keyboard, Mouse, FD, PP, SP, IR AC'97 2.
Introduction Figure 1-2. Intel® 820 Chipset Platform Performance Desktop Block Diagram (with ISA Bridge) Processor 4X AGP Graphics Controller AGP 2.0 82820 Memory Controller Hub (MCH) Main Memory Hub Interface PCI Slots 4 IDE Drives PCI Bus 2 USB Ports AC'97 Codec(s) (optional) Keyboard, Mouse, FD, PP, SP, IR AC'97 2.
Introduction Figure 1-3. Intel® 820 Chipset Platform Dual-Processor Performance Desktop Block Diagram Processor Processor Optional 2-Way/MP 4X AGP Graphics Controller AGP 2.0 82820 Memory Controller Hub (MCH) Main Memory Hub Interface PCI Slots 4 IDE Drives PCI Bus 2 USB Ports AC'97 Codec(s) (optional) Keyboard, Mouse, FD, PP, SP, IR AC'97 2.
Introduction 1.4 Platform Initiatives 1.4.1 Direct Rambus* The Direct Rambus* (RDRAM) initiative provides the memory bandwidth necessary to obtain optimal performance from the Pentium III processor as well as a high-performance AGP graphics controller. The MCH RDRAM interface supports 266 MHz, 300 MHz, 356 MHz, and 400 MHz operation; the latter delivers 1.6 GB/s of theoretical memory bandwidth; twice the memory bandwidth of 100 MHz SDRAM systems.
Introduction 1.4.5 Manageability The Intel® 820 chipset platform integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller. TCO Timer The ICH integrates a programmable TCO Timer. This timer is used to detect system locks.
Introduction 1.4.6 AC’97 The Audio Codec’97 (AC’97) Specification defines a digital link that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC), or both an AC and an MC. The AC’97 Specification defines the interface between the system logic and the audio or modem codec known as the AC’97 Digital Link. The ability to add cost-effective audio and modem solutions is important as the platform migrates away from ISA.
Introduction Figure 1-4. (a-d) AC’97 Connections a) AC'97 With Audio Codec ICH (241 mBGA) AC'97 Digital Link AC'97 Audio Codec Audio Ports b) AC'97 With Modem Codec ICH (241 mBGA) AC'97 Digital Link AC'97 Modem Codec Modem Port c) AC'97 With Audio/Modem Codec ICH (241 mBGA) AC'97 Digital Link AC'97 Audio/ Modem Codec Modem Port Audio Ports d) AC'97 With Audio and Modem Codec ICH (241 mBGA) AC'97 Digital Link AC'97 Modem Codec AC'97 Audio Codec 1.4.
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2 Layout and Routing Guidelines
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Layout/Routing Guidelines Layout/Routing Guidelines 2 This chapter documents motherboard layout and routing guidelines for Intel® 820 chipset based systems. This section does not discuss the functional aspects of any bus, or the layout guidelines for an add-in device. Caution: 2.1 If the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations are completed for each design.
Layout/Routing Guidelines Figure 2-1. MCH 324-uBGA Quadrant Layout (Top View) System Bus AGP 2.0 System Bus Hub Interface MCH (324-uBGA) Direct RDRAM Figure 2-2.
Layout/Routing Guidelines 2.3 Intel® 820 Chipset Component Placement Notes: 1. The ATX placements and layouts shown in Figure 2-3 is recommended for single (UP) Intel® 820 chipset based system design. 2. The trace length limitation between critical connections will be addressed later in this document. 3. The figure is for reference only. Figure 2-3. Sample ATX MCH/ICH Component Placement Processor Host Bus MCH H ub In te rfa ce AGP 2.
Layout/Routing Guidelines 2.4 Core Chipset Routing Recommendations Figure 2-4 and Figure 2-5 show MCH core routing examples. Figure 2-4.
Layout/Routing Guidelines Figure 2-5. Secondary Side MCH Core Routing Example (ATX) 2.5 Source Synchronous Strobing Source synchronous strobing is one of the technologies used in AGP 4X, Direct RDRAM and hub interface that allow very high data transfer rates. As buses get faster, and cycle times get shorter, the propagation delay is becoming a limiting factor in bus speed. Source synchronous strobing is used to minimize the impact of propagation delay (Tprop) on maximum bus frequency.
Layout/Routing Guidelines Figure 2-6. Data Strobing Example Data Sample Clock Strobe Data data_str.vsd For a source synchronous strobed interface, it is very important that the strobe signals are routed carefully. These signals must be very clean (free of noise). Data signals are typically latched on the rising or falling edge of the strobe signal (or both). If there is noise on these signals, it could cause an extra “edge” to be detected, thus latching incorrect data. Refer to Figure 2-7 for examples.
Layout/Routing Guidelines When routing strobes and their associated data lines, trace length mismatch is very important (in addition to noise immunity). The primary benefit of source synchronous strobing is that the data and the strobe arrive at the receiver simultaneously. Thus, a strobe and its associated data signals have very critical length mismatch requirements.
Layout/Routing Guidelines 2.6.1 Stackup The perfect matching of transmission line impedance and uniform trace length are essential for the Direct RDRAM interface to work properly. Maintaining 28 Ω (±10%) loaded impedance for every RSL (Direct Rambus* Signaling Level) signal has changed the requirements for trace width and prepreg thickness for the Intel® 820 chipset platform (refer to Section 5.3, “Stackup Requirement” on page 5-1).
Layout/Routing Guidelines Figure 2-9. RSL Routing Dimensions RIMM_0 RIMM_1 MCH 0"-3.50" 0.4"-0.45" 0"-3" A B C RIMM to RIMM RIMM to Termination MCH to First RIMM To maintain a nominal 28 Ω trace impedance, the RSL signals must be 18 mils wide. To control crosstalk and odd/even mode velocity deltas, there must be a 10 mil ground isolation trace routed between adjacent RSL signals. The 10 mil ground isolation traces must be connected to ground with a via every 1”.
Layout/Routing Guidelines Figure 2-11 and Figure 2-12 show a top view of an example RSL breakout and route. Figure 2-11.
Layout/Routing Guidelines Figure 2-12. Secondary Side RSL Breakout Example 2.6.2.2 RSL Termination All RSL signals must be terminated to 1.8V (Vterm) using 27Ω-2% or 28Ω-1% resistors at the end of the channel opposite the MCH. Resistor packs are acceptable. Vterm must be decoupled using high speed bypass capacitors (one 0.1 µF ceramic chip capacitor per two RSL lines) near the terminating resistors. Additionally, bulk capacitance is required.
Layout/Routing Guidelines Note: It is necessary to compensate for the slight difference in electrical characteristics between a dummy via and a real via. Refer to Section 2.6.2.7, “VIA Compensation” on page 2-23 for more information on Via Compensation. Figure 2-14.
Layout/Routing Guidelines 2.6.2.3 Direct Rambus* Ground Plane Reference All RSL signals must be referenced to GND to provide an optimal current return path. The direct Rambus ground plane reference must be continuous to the Vterm capacitors. The ground reference island under the RSL signals must be continuous from the last RIMM to the back of the termination capacitors. Choose the reference island shape such that power delivery to the components is not compromised.
Layout/Routing Guidelines All 4 layers of the motherboard require correct grounding between the RSL signals on the motherboard: • • • • Layer 1 = Ground Isolation Layer 2 = Ground Plane Layer 3 = Ground Reference in the Power Plane Layer 4 = Ground Isolation All ground vias and pins MUST be connected to all 4 layers. 2.6.2.4 Direct Rambus* Connector Compensation The RIMM connector inductance causes an impedance discontinuity on the Direct Rambus* channel. This may reduce voltage and timing margin.
Layout/Routing Guidelines Table 2-3. Copper Tab Area Calculation Dielectric Thickness (D) Separation Between Signal Trace & Copper Tab Minimum Ground flood Air Gap between Signal & GND Flood Compensating Capacitance in pF Copper Tab (C-TAB) Area (A) In sq mils 4.5 6 10 6 0.65 2800 C-TAB Shape (mils) 140 L x 20 W 70 L x 40 W Based on Equation 1, the tab area is 2800 sq mils, where εr is 4.2 and D is 4.5. These values are based on 2116 prepreg material.
Layout/Routing Guidelines Figure 2-17.
Layout/Routing Guidelines Figure 2-18. Section A1, Top Layer Outer C-tab Inner C-tab NOTES: 1. Refer to Figure 2-17.
Layout/Routing Guidelines Figure 2-19. Section A1, Bottom Layer NOTES: 1. Refer to Figure 2-17.
Layout/Routing Guidelines Figure 2-20. Section B1, Top Layer NOTES: 1. Refer to Figure 2-17.
Layout/Routing Guidelines Figure 2-21. Section B1, Bottom Layer NOTES: 1. Refer to Figure 2-17. Ground flood removed from picture for clarity 2.6.2.5 RSL Signal Layer Alternation RSL signals must alternate layers as they are routed through the channel. If a signal is routed on the primary layer from the MCH to the first RIMM socket, it must be routed on the secondary layer from the first RIMM to the second RIMM as shown in Figure 2-22 (signal B).
Layout/Routing Guidelines Figure 2-22. RSL Signal Layer Alternation Signal B Signal on Secondary Side Signal on Primary Side Signal A Signal A MCH Route on EITHER layer. Ground Isolation is REQUIRED! Term Signal B Table 2-4. RSL Routing Layer Requirements 2.6.2.
Layout/Routing Guidelines Equation 2-2. RDRAM RSL Signal Trace Length Calculation Package Dimension + Board Trace Length = Nominal RSL Length ± 10mils Figure 2-23.
Layout/Routing Guidelines 2.6.2.7 VIA Compensation As described in Section 2.8.2, “Strobe Signals” on page 2-44, all signals must have the same number of vias. As a result, each trace will have 1 via (near the BGA pad) because some of the RSL signals must be routed on the bottom of the motherboard. Therefore, it is necessary to place a dummy via on all signals that are routed on the top layer.
Layout/Routing Guidelines Table 2-5. Line Matching and Via Compensation Example1,2,3,4,5,6,7,8,9,10 Signal Ball on MCH Nominal RSL Length (mils) Package Dimension (mils) Motherboard Trace Length when Routed on Bottom (i.e., Real Via) Min (mils) Max (mils) Formula A Motherboard Trace Length when Routed on Top (i.e., Dummy Via) Min (mils) Recommended To Route On Max (mils) Formula B DQA0 DQA1 DQA2 DQA3 A13 C13 A14 C14 2000 2000 2000 2000 138.14 19.11 163.16 39.87 1851.86 1970.89 1826.84 1950.
Layout/Routing Guidelines 2.6.3 Direct Rambus* Reference Voltage The Direct Rambus* reference voltage (RAMREF) must be generated as shown in Figure 2-25. RAMREF should be generated from a typical resistor divider using 2% tolerance resistors. Additionally, RAMREF must be decoupled locally at EACH RIMM connector, at the resistor divider and at the MCH. Finally, as shown in Figure 2-25, a 100 Ω series resistor is required near the MCH. The RAMREF signal should be routed with a 10 mil wide trace.
Layout/Routing Guidelines Figure 2-26. High-Speed CMOS Termination RIMM_0 RIMM_1 Vterm R1 91 Ω R2 39 Ω MCH 2.6.4.1 SIO Routing The SIO signal must be routed from RIMM to RIMM as shown in Figure 2-17. The SIO signal requires a 2.2 KΩ – 10 KΩ terminating resistor on the SOUT pin of the last RIMM. SIO is routed with a standard 5 mil wide 60 Ω trace. The motherboard routing lengths for the SIO signal are the same as RSL signals (see Figure 2-17). Figure 2-27.
Layout/Routing Guidelines To minimize impedance discontinuities, the traces for CMD and SCK must have a neckdown from 18 mil traces to 5 mil traces for 175 mils on either side of the SCK/CMD attach point as shown in Figure 2-28. Figure 2-28.
Layout/Routing Guidelines 2.6.5 Direct Rambus* Clock Routing Refer to Chapter 4, “Clocking” for Intel® 820 chipset platform Direct Rambus* clock routing guidelines. 2.6.6 Direct Rambus* Design Checklist Use the following checklist as a final check to ensure the motherboard incorporates solid design practices. This list is only a reference. For correct operation, all of the design guidelines within this document must be followed. Table 2-6.
Layout/Routing Guidelines • • • • — Vterm island should be 50 – 75 mils wide — Vterm island should not be broken — If any RSL signals are routed out of the last RIMM (towards termination) on the bottom side (even for a short distance), ensure Ground Reference Plane (on the third layer) is continuous under the termination resistors/capacitors — Ensure current path for power delivery to the MCH does not go through the Vterm island CTM/CTM# Routed Properly — CTM/CTM# are routed differentially from DRCG to
Layout/Routing Guidelines • • — ALL RSL, CMD/SCK and CTM/CTM#/CFM/CFM# signals have CTABs on each RIMM connector pin — All RSL signals are routed adjacent to a ground reference plane. This includes all signals from the last RIMM to the termination. If signals are routed on the bottom from the last RIMM to the termination, the ground reference plane on the 3rd layer MUST extend under these signals AND include the ground side of the Vterm decoupling capacitors.
Layout/Routing Guidelines 2.7 AGP 2.0 For detailed AGP Interface functionality (protocols, rules and signaling mechanisms, etc.) refer to the latest AGP Interface Specification revision 2.0, which can be obtained from http:// www.agpforum.org. This document focuses only on specific Intel® 820 chipset platform recommendations. The AGP Interface Specification revision 2.0 enhances the functionality of the original AGP Interface Specification (revision 1.
Layout/Routing Guidelines 2.7.1 AGP Interface Signal Groups The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X timing domain signals and miscellaneous signals. Each group has different routing requirements. In addition, within the 2X/4X timing domain signals, there are three sets of signals. All signals in the 2X/4X timing domain must meet minimum and maximum trace length requirements as well as trace width and spacing requirements.
Layout/Routing Guidelines Table 2-7. AGP 2.0 Data/Strobe Associations Associated Strobe in 1X Data Associated Strobe in 2X Associated Strobes in 4X AD[15:0] and C/BE[1:0]# Strobes are not used in 1X mode. All data is sampled on rising clock edges. AD_STB0 AD_STB0, AD_STB0# AD[31:16] and C/BE[3:2]# Strobes are not used in 1X mode. All data is sampled on rising clock edges. AD_STB1 AD_STB1, AD_STB1# SBA[7:0] Strobes are not used in 1X mode. All data is sampled on rising clock edges.
Layout/Routing Guidelines The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB and SB_STB#) act as clocks on the source synchronous AGP interface; therefore, special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5 mil traces with at least 15 mils of space (1:3) between them.
Layout/Routing Guidelines This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length matched to less than ±0.1” (i.e., a strobe and its compliment must be the same length within 0.1”). All AGP Interfaces The 2X/4X Timing Domain Signals can be routed with 5 mil spacing when breaking out of the MCH. The routing must widen to the documented requirements within 0.3” of the MCH package.
Layout/Routing Guidelines 2.7.5 AGP Clock Routing The maximum total AGP clock skew (between the MCH and the graphics component) is 1 ns for all data transfer modes. This 1 ns includes skew and jitter which originates on the motherboard, add-in card, and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but at all points on the clock edge that fall in the switching range. The 1 ns skew budget is divided such that the motherboard is allotted 0.
Layout/Routing Guidelines Figure 2-30. Top Signal Layer Must add six 0.01 uF ceramic 603 Type Capacitors Ground Reference It is strongly recommended that, at a minimum, the following critical signals be referenced to ground from the MCH to an AGP connector (or to an AGP video controller if implemented as a “down” solution) utilizing a minimum number of vias on each net; AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_GTRY#, G_IRDY#, G_GNT# and ST[2:0].
Layout/Routing Guidelines AGP 2.0 requires that these power planes be separate. In conjunction with the 4X data rate, the AGP 2.0 Interface Specification provides for low-voltage (1.5V) operation. The AGP 2.0 Specification implements a TYPEDET# (type detect) signal on the AGP connector that determines the operating voltage of the AGP 2.0 interface (VDDQ). The motherboard must provide either 1.5V or 3.3V to the add-in card depending on the state of the TYPEDET# signal (refer to Table 2-9. The 1.
Layout/Routing Guidelines Figure 2-31. AGP VDDQ Generation Example Circuit +3.3V O +12V O VDDQ O C2 47 uF U1 1 LT1575 SHDN IPOS VIN INEG 5 6 2 5Ω C3 220 uF R2 R1 1 KΩ 3 C1 1 uF 4 GND GATE FB COMP 7 8 C4 10 pF C5 47 uF R5 7.5 KΩ R3 301 Ω TYPEDET# R4 1.21 KΩ agp vddq generation vsd 2.7.8 VREF Generation for AGP 2.0 (2X and 4X) VREF generation for AGP 2.0 will be different depending on the AGP card type used. The 3.3V AGP cards generate VREF locally (i.e.
Layout/Routing Guidelines During 3.3V AGP 2.0 operation, VREF must be 0.4VDDQ. However, during 1.5V AGP 2.0 operation, Vref must be 0.5VDDQ. This requires a flexible voltage divider for VREF. Various methods of accomplishing this exist, and one such example is shown in Figure 2-32. Figure 2-32. AGP 2.0 VREF Generation & Distribution +12V O R7 1K 1.
Layout/Routing Guidelines 2.7.9 Compensation The MCH AGP interface supports resistive buffer compensation (RCOMP). Tie the GRCOMP pin to a 40 Ω 2% (or 39 Ω 1%) pull-down resistor (to ground) via a 10 mil wide, very short (<0.5”) trace. 2.7.10 AGP Pull-ups AGP control signals require pull-up resistors to VDDQ on the motherboard to ensure they contain stable values when no agent is actively driving the bus.
Layout/Routing Guidelines 2.7.10.1 AGP Signal Voltage Tolerance List The following signals on the AGP interface are 3.3V tolerant during 1.5V operation: • • • • • • • PME# INTA# INTB# GPERR# GSERR# CLK RST The following signals on the AGP interface are 5V tolerant (refer to the USB specification): • USB+ • USB• OVRCNT# The following signal is a special AGP signal. It is either Grounded or No Connected on an AGP card. • TYPEDET# Note: 2.7.
Layout/Routing Guidelines 2.8 Hub Interface The MCH and ICH ball assignments have been optimized to simplify hub interface routing. It is recommended that the hub interface signals be routed directly from the MCH to the ICH on the top signal layer (they do not need to be run through vias) (refer to Figure 2-4). The hub interface is broken into two signal groups: data signals and strobe signals.
Layout/Routing Guidelines 2.8.1 Data Signals The Hub interface data signals (HL[10:0]) should be routed 5 on 20. These signals can be routed 5 on 15 for navigation around components or mounting holes. In order to break-out of the MCH uBGA and the ICH uBGA, the hub interface data signals can be routed 5 on 5. The signals must be separated to 5 on 20 within 300 mil of the uBGA package. The maximum trace length for the hub interface data signals is 7”. These signals must each be matched within ±0.
Layout/Routing Guidelines Figure 2-35. Locally generated Hub Interface Reference Dividers 1.8V 1.8V 300Ω 300Ω HUBREF HUBREF ICH MCH 300Ω 300Ω 0.1uF 0.1uF HubRef2.vsd 2.8.4 Compensation There are two options for the ICH hub interface compensation (HLCOMP). HLCOMP is used by the ICH to adjust buffer characteristics to specific board characteristics. Refer to the ICH Datasheet for details on compensation. It can be used as either Impedance Compensation (ZCOMP) or Resistive Compensation (RCOMP).
Layout/Routing Guidelines 2.9 System Bus Design 2.9.1 100/133 MHz System Bus First, determine the approximate location of the processor and the chip set on the base board. An example topology is shown in Figure 2-36. This example “star” topology is valid for 133 MHz and 100 MHz 2-way processor/Intel® 820 chipset designs. The 82820 MCH should be placed electrically in the center of the bus. The SC242 connectors should be placed on either end of the bus to allow the processors to terminate each end.
Layout/Routing Guidelines 2.9.2 System Bus Ground Plane Reference All system bus signals must be referenced to GND to provide optimal current return path. The ground reference must be continuous from the MCH to the SC242 connector. This may require a GND reference island on the plane layers closest to the signals. Any split in the ground island will provide a sub-optimal return path. In a 4 layer board, this will require the VCCID island to be on an outer signal layer.
Layout/Routing Guidelines Motherboard Interfaces Figure 2-39 shows the Hole Locations and Keepout Zones For Support Components (from the motherboard surface to 0.100” above the motherboard surface.). Figure 2-39. Hole Locations and Keepout Zones For Support Components1,2 Primary Side 1.270 4x Thru ∅ 0.159 0.232 0.806 +0.002 -0.001 1.038 0.175 0.231 0.375 4x ∅ 0.300 Keepout 4.706 4.881 5.256 Secondary Side 1. All dimensions are in inches and all toler ances ±0.04, unless otherwise specified. 2.
Layout/Routing Guidelines 2.11 Processor CMOS Pullup Values Table 2-13 contains the pullup values for the Intel® Pentium® III processor with the Intel® 820 chipset. This table supports both single and dual processor configurations. Table 2-13. Processor and 82820 MCH Connection Checklist1,2 CPU Pin UP Pin Connection (CPU0) DP Pin Connection (CPU1) AGTL+ Signals A[35:3]# 1 Connect A[31:3]# to MCH. Leave A[35:32]# as N/C (not supported by chipset).
Layout/Routing Guidelines Table 2-13. Processor and 82820 MCH Connection Checklist1,2 (Continued) CPU Pin UP Pin Connection (CPU0) DP Pin Connection (CPU1) CMOS Signals A20M# 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2nd processor FERR# 150 Ω pull up to Vcc2.5, connect to ICH Connect to 2nd processor FLUSH# 150 Ω pull up to Vcc2.5 (not used by chipset). Connect to 2nd processor IERR# 150 Ω pull up to Vcc2.5 if tied to custom logic or leave as N/C (not used by chipset).
Layout/Routing Guidelines Table 2-13. Processor and 82820 MCH Connection Checklist1,2 (Continued) CPU Pin UP Pin Connection (CPU0) DP Pin Connection (CPU1) BCLK Connect to CK133. 22 – 33 Ω series resistor (Though OEM needs to simulate based on driver characteristics). To reduce pin-to-pin skew, tie host clock outputs together at the clock driver then route to the MCH and processor. Use separate BCLK from TAP and CPU0, or use ganged clock. Terminate as described. PICCLK Connect to CK133.
Layout/Routing Guidelines Figure 2-41. TCK/TMS Implementation Example for DP Designs Vcc2.5 RI 1 KΩ SC242 Connector A non-inverting buffer ITP Port TCK or TMS 100 nH motherboard trace 56 pF SC242 Connector B non-inverting buffer 100 nH motherboard trace 56 pF itp vsd Table 2-14. Bus Request Connection Scheme for DP Intel® 820 Chipset Designs 2.
Layout/Routing Guidelines DP Systems: For dual processor systems, BREQ0# (to one of the processors) needs to be driven for arbitration ID strapping. Refer to Figure 2-43 for an example of the BREQ connections in a DP system. It is a requirement that the on-board logic tri-state BREQ0# after the arbitration ID strapping is complete. Additionally, BREQ0# and BREQ1# are high-speed AGTL+ signals and the loading characteristics of the on-board logic must be considered even when the logic is tri-stated.
Layout/Routing Guidelines The recommendation for the layout and the schematic example are shown below. Layout guidelines are: • Place the transistor and stub as close as possible to MCH (or place the transistor pad on top of trace) • The max stub for transistor is less than 0.25” • The recommended loading of transistor is less than 5 pf. • For dual processor design, the stub is recommended to place on the stub of the MCH and as close as possible to the MCH, and is less than 0.
Layout/Routing Guidelines Minimizing Crosstalk on the AGTL+ Interface The following general rules will minimize the impact of crosstalk in the high speed AGTL+ bus design: • Maximize the space between traces. Maintain a minimum of 0.010” between traces wherever possible. It may be necessary to use tighter spacings when routing between component pins. • Avoid parallelism between signals on adjacent layers.
Layout/Routing Guidelines 2.13 Ultra ATA/66 This section contains guidelines for connecting and routing the ICH IDE interface. The ICH has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement, and signal termination for both IDE channels. The ICH has integrated the 33 Ω series resistors that have been typically required on the IDE data signals running to the two ATA connectors.
Layout/Routing Guidelines 2.13.2 Ultra ATA/66 Cable Detection The Intel® 820 chipset can use two methods to detect the cable type. Each mode requires a different motherboard layout. Host-Side Detection (BIOS Detects Cable Type Using GPIOs) Host side detection requires the use of two GPI pins (1 per IDE controller). The proper way to connect the PDIAG/CBLID signal of the IDE connector to the host is shown in Figure 2-46. All IDE devices have a 10 KΩ pull-up resistor to 5 volts.
Layout/Routing Guidelines Device-Side Detection (BIOS Queries IDE Drive for Cable Type) Device side detection requires only a 0.047 uF capacitor on the motherboard as shown in Figure 2-47. This mechanism creates a resistor-capacitor (RC) time constant. The ATA mode 3 or 4 drive will drive PDIAG/CBLID low and then release it (pulled up through a 10 KΩ resistor) The drive will sample the PDIAG signal after releasing it.
Layout/Routing Guidelines Figure 2-48. Layout for Host- or Drive-Side IDE Cable Detection ICH R1 R2 C1 id 1 d Figure 2-49.
Layout/Routing Guidelines 2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements • 22 Ω – 47 Ω series resistors are required on RESET#. The correct value should be determined for each unique motherboard design, based on signal quality. • An 8.2 KΩ to 10 KΩ pull-up resistor is required on IRQ14 and IRQ15 to VCC5. • A 10 KΩ pull-down resistor is required on PDD7 and SDD7 (as required by the ATA-4 specification). • A 5.
Layout/Routing Guidelines Figure 2-51. Resistor Requirements for Secondary IDE Connector 22 - 47 ohm Reset# PCIRST_BUF#* SDD[15:8] SDD[7] SDD[6:0] SDA[2:0] SDCS1# SDCS3# SDIOR# Secondary IDE Connector SDIOW# SDDREQ 5V 1k ohm 5V 8.2k-10k ohm 5.6k ohm 10k ohm SIORDY IRQ15 SDDACK# 470 ohm CSEL ICH N.C. Pin 32 N.C. Pin 34 *Due to ringing, PCIRST# must be buffered. 2.14 AC’97 The ICH implements an AC’97 2.1 compliant digital controller. Any codec attached to the ICH AC-link must be AC’97 2.
Layout/Routing Guidelines The AMR specification provides a mechanism for AC’97 codecs to be on a riser card. This is important for modem codecs as it helps ease international certification of the modem. For increased part placement flexibility, there are two routing methods for the AC’97 interface: the tee topology and the daisy-chain topology. The AC’97 interface can be routed using 5 mil traces with 5 mil space between the traces. Figure 2-52.
Layout/Routing Guidelines Clocking is provided from the primary codec on the link via BITCLK, and is derived from a 24.576 MHz crystal or oscillator. Refer to the primary codec vendor for crystal or oscillator requirements. BITCLK is a 12.288 MHz clock driven by the primary codec to the digital controller (ICH), and any other codec present. That clock is used as the timebase for latching and driving data.
Layout/Routing Guidelines • Codec Implementation • • • 2-64 — The motherboard can implement any valid combination of codecs on the motherboard and on the riser. For ease of homologation, it is recommended that a modem codec be implemented on the AMR module; however, nothing precludes a modem codec on the motherboard. — Only one primary codec can be present on the link. A maximum of two present codecs can be supported in an ICH0/ICH platform.
Layout/Routing Guidelines 2.15 USB The following are general guidelines for the USB interface: • Unused USB ports should be terminated with 15 KΩ pulldown resistors on both P+/P- data lines. • 15 Ω series resistors should be placed as close as possible to the ICH (<1 inch). These series resistors are required for source termination of the reflected signal. • 47 pF caps must be placed as close to the ICH as possible and on the ICH side of the series resistors on the USB data lines (P0+/-, P1+/-).
Layout/Routing Guidelines Recommended USB trace characteristics • • • • • Impedance ‘Z0’ = 45.4 Ω Line Delay = 160.2 ps Capacitance = 3.5 pF Inductance = 7.3 nH Res @ 20° C = 53.9 mOhm 2.16 ISA (82380AB) 2.16.1 ICH GPIO connected to 82380AB At reset, the ICH LPC Bridge defaults to subtractive decode. Since the LPC bridge logically sits on PCI there will be two subtractive decode bridges in systems with the 82380AB (which is also a subtractive decode device). A GPO that defaults high (i.e.
Layout/Routing Guidelines 2.18 SMBus/Alert Bus The Alert on LAN* signals can be used as: • Alert on LAN* signals: 4.7 KΩ pullup resistors to 3.3VSB are required. Pullup resistors to 3.3VSB and the signals must be allowed to • GPIOs: change states on powerup (e.g., on power-up, the ICH drives heartbeat messages until the BIOS programs these signals as GPIOs). The value of the pullup resistors depends on the loading on the GPIO signal. • Not Used: 4.7 KΩ pullup resistors to 3.3VSB are required.
Layout/Routing Guidelines 2.20.1 RTC Crystal The ICH RTC module requires an external oscillating source of 32.768 KHz connected on the RTCX1 and RTCX2 pins. Figure 2-56 documents the external circuitry that comprises the oscillator of the ICH RTC. Figure 2-56. External Circuitry for the ICH RTC2 VCCRTC 3 VCC3_3SBY 1 µF 1 kΩ RTCX2 4 1 kΩ Vbat_rtc 32768 Hz Xtal R1 10 M Ω RTCX1 5 C1 0.047 uF C3 1 R2 10 M Ω VBIAS 6 C2 1 VSS 7 NOTES: 1.
Layout/Routing Guidelines 2.20.3 RTC Layout Considerations • • • • Keep the RTC lead lengths as short as possible; around ¼ inch is sufficient. Minimize the capacitance between Xin and Xout in the routing. Put a ground plane under the XTAL components. Do not route switching signals under the external components (unless on the other side of the board). • The oscillator VCC should be clean; use a filter, such as an RC lowpass, or a ferrite inductor. 2.20.
Layout/Routing Guidelines 2.20.5 RTC External RTCRST Circuit The ICH RTC requires some additional external circuitry. The RTCRST# signal is used to reset the RTC well. The external capacitor and the external resistor between RTCRST# and the RTC battery (Vbat) were selected to create an RC time delay, such that RTCRST# will go high some time after the battery voltage is valid. The RC time delay should be in the range of 10-20 ms.
Layout/Routing Guidelines 2.20.7 VBIAS DC Voltage and Noise Measurements • Steady state VBIAS will be a DC voltage of about 0.38V ±0.06V. • VBIAS will be “kicked” when the battery is inserted to about 0.7–1.0V, but it will come back to its DC value within a few ms. • Noise on VBIAS must be kept to a minimum, 200 mV or less. • VBIAS is very sensitive and cannot be directly probed; it can be probed through a 0.01 uF capacitor.
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3 Advanced System Bus Design
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Advanced System Bus Design Advanced System Bus Design 3 Section 2.9, “System Bus Design” on page 2-46 describes the recommendations for designing Intel® 820 chipset based platforms. This chapter discusses more detail about the methodology used to develop the guidelines. Section 3.2, “AGTL+ Design Guidelines” on page 3-4 discusses specific system guidelines. This is a step-by-step methodology that Intel has successfully used to design high performance desktop systems. Section 3.
Advanced System Bus Design Term Definition Cross-talk The reception on a victim network of a signal imposed by aggressor network(s) through inductive and capacitive coupling between the networks. • Backward Cross-talk - coupling which creates a signal in a victim network that travels in the opposite direction as the aggressor’s signal. • Forward Cross-talk - coupling which creates a signal in a victim network that travels in the same direction as the aggressor’s signal.
Advanced System Bus Design Term Definition Network The trace of a Printed Circuit Board (PCB) that completes an electrical connection between two or more components. Network Length The distance between extreme bus agents on the network and does not include the distance connecting the end bus agents to the termination resistors. Overdrive Region Is the voltage range, at a receiver, located above and below VREF for signal integrity analysis.
Advanced System Bus Design 3.2 AGTL+ Design Guidelines The following step-by-step guideline was developed for systems based on two processor loads and one Intel 82820 MCH load. Systems using custom chipsets will require timing analysis and analog simulations specific to those components. The guideline recommended in this section is based on experience developed at Intel while developing many different Intel Pentium® Pro processor family and Intel Pentium III processorbased systems.
Advanced System Bus Design 3.2.1 Initial Timing Analysis Perform an initial timing analysis of the system using Equation 3-1 and Equation 3-2 shown below. These equations are the basis for timing analysis. To complete the initial timing analysis, values for clock skew and clock jitter are needed, along with the component specifications. These equations contain a multi-bit adjustment factor, MADJ, to account for multi-bit switching effects such as SSO pushout or pull-in that are often hard to simulate.
Advanced System Bus Design There are multiple cases to consider. Note that while the same trace connects two components, component A and component B, the minimum and maximum flight time requirements for component A driving component B as well as component B driving component A must be met.
Advanced System Bus Design of timing and signal quality margin. The magnitude of MADJ is highly dependent on baseboard design implementation (stackup, decoupling, layout, routing, reference planes, etc.) and needs to be characterized and budgeted appropriately for each design. Table 3-2 and Table 3-3 are derived assuming: • CLKSKEW = 0.
Advanced System Bus Design Table 3-3. Example TFLT_MIN Calculations (Frequency Independent) THOLD ClkSKEW TCO_MIN Recommended TFLT_MIN Processor2 0.8 0.2 -0.1 1.2 Processor2 82820 MCH 0.28 0.2 -0.1 .58 82820 MCH Processor2 0.8 0.2 0.5 .5 Driver Processor2 Receiver NOTES: 1. All times in nanoseconds. 2. Processor values specified in this table are examples only. Refer to the appropriate processor datasheet for specification values. 3.2.
Advanced System Bus Design 3.2.3.3 Monte Carlo Analysis Perform a Monte Carlo analysis to refine the passing solution space region. A Monte Carlo analysis involves randomly varying parameters (independent of one another) over their tolerance range. This analysis intends to ensure that no regions of failing flight time and signal quality exists between the extreme corner cases run in pre-layout simulations.
Advanced System Bus Design Intel has found wide variation in noise margins when varying the stub impedance and the PCB’s Z0 and S0. Intel therefore recommends that PCB parameters are controlled as tightly as possible, with a sampling of the allowable Z0 and S0 simulated. The Intel® Pentium® III processor nominal effective line impedance is 65 Ω ±15%. Future Intel® Pentium® III processor effective line impedance (ZEFF) may be 60 Ω ±15%.
Advanced System Bus Design interference from AGTL+ signals in a particular group to AGTL+ signals in a different group. An example of AGTL+ to non-AGTL+ cross-talk is when CMOS and AGTL+ signals interfere with each other. Table 3-4.
Advanced System Bus Design 3.2.4.3 Host Clock Routing Host clock nets should be routed as point-to-point connections through a series resistor placed as close to the output pins of the clock driver as possible. The value of the series resistor is dependent on the clock driver characteristic impedance. However, a value of 33 Ω is a good starting point. Table 3-5 provides the trace length recommendations for this topology.
Advanced System Bus Design 3.2.5 Post-Layout Simulation Following layout, extract the interconnect information for the board from the CAD layout tools. Run simulations to verify that the layout meets timing and noise requirements. A small amount of “tuning” may be required; experience at Intel has shown that sensitivity analysis dramatically reduces the amount of tuning required. The post layout simulations should take into account the expected variation for all interconnect parameters.
Advanced System Bus Design 3.2.6 Validation Build systems and validate the design and simulation assumptions. 3.2.6.1 Measurements Note that the AGTL+ specification for signal quality is at the pad of the component. The expected method of determining the signal quality is to run analog simulations for the pin and the pad. Then correlate the simulations at the pin against actual system measurements at the pin. Good correlation at the pin leads to confidence that the simulation at the pad is accurate.
Advanced System Bus Design double counting. TREF is defined as the time that it takes for the driver output pin to reach the measurement voltage, VREF, starting from the beginning of the driver transition at the pad. TREF must be generated using the same test load for TCO. Intel provides this timing value in the AGTL+ I/O buffer models. In this manner, the following valid delay equation is satisfied: Equation 3-5.
Advanced System Bus Design 3.3.2 Timing Requirements The system timing for AGTL+ is dependent on many things. Each of the following elements combine to determine the maximum and minimum frequency the AGTL+ bus can support: • The range of timings for each of the agents in the system. — Clock to output [TCO]. (Note that the system load is likely to be different from the “specification” load therefore the TCO observed in the system might not be the same as the TCO from the specification.
Advanced System Bus Design Figure 3-4. Aggressor and Victim Networks Zo Zo Victim Zo Zo Signal propagates in both directions on aggressor line. Aggressor Figure 3-5. Transmission Line Geometry: (A) Microstrip (B) Stripline Signal Lines Signal Lines W Dielectric, εr Dielectric, εr Sp t AC Ground Plane A. Microstrip B. Stripline li d Additional aggressors are possible in the z-direction, if adjacent signal layers are not routed in mutually perpendicular directions.
Advanced System Bus Design propagation time on the coupled network length exceeds one half of the rise time of the aggressor’s signal.
Advanced System Bus Design 3.4 More Details and Insight 3.4.1 Textbook Timing Equations The “textbook” equations used to calculate the propagation rate of a PCB are the basis for spreadsheet calculations for timing margin based on the component parameters. These equations are: Equation 3-6. Intrinsic Impedance Z0 = L0 C 0 (Ω) Equation 3-7. Stripline Intrinsic Propagation Speed S0_ STRIPLINE = 1017 . * εr (ns/ft) Equation 3-8. Microstrip Intrinsic Propagation Speed S0_ MICROSTRIP = 1017 . * 0.
Advanced System Bus Design Symbols for Equation 3-5 through Equation 3-12: • S0 is the speed of the signal on an unloaded PCB in ns/ft. This is referred to as the board propagation constant. • S0 MICROSTRIP and S0 STRIPLINE refer to the speed of the signal on an unloaded microstrip or stripline trace on the PCB in ns/ft. • Z0 is the intrinsic impedance of the line in Ω and is a function of the dielectric constant (εr), the line width, line height and line space from the plane(s).
Advanced System Bus Design change the impedance of adjacent trace layers. (For instance, the impedance calculations may have been done for microstrip geometry, and adding a partial plane on the other side of the trace layer may turn the microstrip into a stripline.) 3.4.3.2 Reference Planes and PCB Stackup It is strongly recommended that baseboard stackup be arranged such that AGTL+ signals are referenced to a ground (VSS) plane, and that the AGTL+ signals do not traverse multiple signal layers.
Advanced System Bus Design When routing and stackup constraints require that an AGTL+ signal reference VCC or multiple planes, special care must be given to minimize the SSO impact to timing and noise margin. The best method of reducing adverse effects is to add high-frequency decoupling wherever the transitions occur, as shown in Figure 3-9 and Figure 3-10.
Advanced System Bus Design 3.4.3.4 SC242 Connector Intel studies indicate that the use of thermal reliefs on the connector pin layout pattern (especially ground pins) should be minimized. Such reliefs (cartwheels or wagon-wheels) increase the net ground inductance and reduce the integrity of the ground plane to which many signals are referenced. Increased ground inductance has been shown to aggravate SSO effects.
Advanced System Bus Design and parallel ground trace for the total length of each clock ensures a low inductance ground return and produces the minimum current path loop area. (The parallel ground trace will have lower inductance than the ground plane because of the mutual inductance of the current in the clock trace.) 3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality Acceptable signal quality must be maintained over all operating conditions to ensure reliable operation.
Advanced System Bus Design should extrapolate back to the appropriate VREF Guardband boundary, and not VREF. So, for maximum rising edge correction, extrapolate back to VREF + ∆VREF. For maximum falling edge corrections, extrapolate back to VREF - ∆VREF. Figure 3-11. Overdrive Region and VREF Guardband VREF+ 200 mV VREF+ 100 mV ∆VREF VREFGuardband VREF ∆ V REF VREF- 100 mV VREF- 200 mV 3.5.
Advanced System Bus Design 3.6 Conclusion AGTL+ routing requires a significant amount of effort. Planning ahead and leaving the necessary time available for correctly designing a board layout will provide the designer with the best chance of avoiding the more difficult task of debugging inconsistent failures caused by poor signal integrity. Intel recommends planning a layout schedule that allows time for each of the tasks outlined in this document.
4 Clocking
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Clocking 4 Clocking 4.1 Clock Generation There are two clock generator components required in an Intel® 820 chipset based system. The Direct Rambus* Clock Generator (DRCG) generates clock for the Direct Rambus* interface while the CK133 component generates clocks for the rest of the system. Clock synthesizers that meet the Intel CK98 Clock Specification are suitable for an Intel® 820 chipset based system. The CK133 generates the clocks listed in Table 4-1. Table 4-1.
Clocking • The MCH hub interface/AGP clock and the ICH hub interface clock. The DRCG reference clock operates at one-half the CPU clock frequency. It is an input into the DRCG and is used to generate the Direct RDRAM “Clock to Master” differential pair (CTM, CTM#). The DRCG generates one pair of differential Direct RDRAM Clocks (CTM, CTM#) from the reference clock generated by the CK133.
Clocking Table 4-2.
Clocking Figure 4-2 shows the Intel® 820 chipset clock length routing guidelines. Figure 4-2. Intel® 820 Chipset Clock Routing Guidelines1,2 Y CPUCLK to SC242 Y 5.3" CPUCLK to MCH ±0" Note: Tie CPUCLK for the MCH to CPUCLK to the SC242 to eliminate pin-to-pin skew. 3V66 Clock for AGP Slot Z PCI Clock for PCI Slots Z 3V66 Clock for MCH and ICH Z 4" Z 4" Z 4" 1.5" ±TBD3 PCI Clock for ICH PCI Clock for On-Board Devices (excluding ICH) ±0" ±0" ±TBD3 Note: 1.
Clocking Table 4-3.
Clocking 4.2 Component Placement and Interconnection Layout Requirements Detailed explanation of layout requirements for each interconnections are provided in the following sections: • • • • 4.2.1 Crystal to CK133 CK133 to DRCG MCH to DRCG DRCG to RDRAM channel 14.318 MHz Crystal to CK133 The distance between the crystal and the CK133 should be minimized. The maximum trace length is 500 mils. 4.2.2 CK133 to DRCG • CPU_div2 • VDDIR – Used as a reference for 2.5V signaling Figure 4-3.
Clocking 4.2.3 MCH to DRCG • PclkM • PclkN • VddIPD Figure 4-4. MCH to DRCG Routing Diagram 6 mils 6 mils Ground 6 mils VddiPD 6 mils 6 mils Ground 6 mils Hclkout 6 mils 6 mils 6 mils Rclkout 6 mils Ground 6 mils 1.4 mils 4.5 mils 1.4 mils Ground/Power Plane The Hclkout, Rclkout and VddiPD should be routed as shown in Figure 4-4. Note that the VddiPD pin can be connected directly to 1.8V near the DRCG if the 1.8V plane extends near the DRCG. However, if a 1.
Clocking 4.2.4 DRCG to RDRAM Channel The Direct Rambus* clock signals (CTM/CTM# and CFM/CFM#) are high-speed, impedance matched transmission lines. The Direct Rambus* clocks begin at the end of the Direct Rambus* channel and propagate to the controller as CTM/CTM# (see Figure 4-5), where it loops back as CFM/CFM#. Table 4-4 lists the placement guidelines. Table 4-4.
Clocking For the line section labeled ‘D’ (DRCG to Last RIMM) the CTM/CTM# must be length matched within ±2 mils (exactly is recommended), and for the section labeled ‘C’, ±2 mil trace length matching is required for the CFM/CFM# signals. Note: Total trace length matching for the entire CTM/CTM# signal trace (Sections A+B+D) and for the CFM/CFM# signal trace (Sections A+B) is ±2 mils (exact length matching is recommended). Figure 4-6.
Clocking 4.3 DRCG Impedance Matching Circuit The external DRCG impedance matching circuit is shown in Figure 4-9. The values for the elements are listed in Table 4-5. Figure 4-9. DRCG Impedance Matching Network 3.3v To 3.3V DRCG Supply Connection CD2 C C D V DD IR V DD FBead CD2 D O Z CH V DD P C R R S C R D R T CMID2 P C D DRCG C MID F S R P Z CH R T V C DD V IPD DD C CBulk CD V O DD D Table 4-5. External DRCG Component Values1,2 Component Nominal Value CD 0.
Clocking 4.3.1 DRCG Layout Example Figure 4-10. DRCG Layout Example Cmid - 100pF EMI Cap - 4pF Do Not Stuff CTM/CTM# route on bottom layer Rs - 39 Ω (Keep trace from DRCG to Rs VERY short) Rp - 51 Ω (Keep trace from Rs to Rp short) Decoupling Cap - 0.1uF (Place VERY Near DRCG 3.3V Pin!) Decoupling Cap - 0.1uF (Place VERY Near DRCG 3.3V Pin!) 3.3V-DRCG Flood Flood 3.3V-DRCG on the top layer around DRCG. Flood MUST include: 4 DRCG Power Pins 4 0.
Clocking 4.6 Unused Outputs All unused clock outputs must be tied to ground through a series resistor approximately the impedance of the output buffer (shown below.) The intent of these resistors is to terminate the unused outputs to eliminate EMI. Table 4-6. Unused Output Termination VCC Range (V) Impedance (Ohms) If Unused Output Termination to VSS CPU, CPU_Div2, IOAPIC 2.375 - 2.625 13.5 - 45 30 Ohms 48 MHz, REF 3.135 - 3.465 20 - 60 40 Ohms PCI, 3V66 3.135 - 3.
Clocking 2. The Intel® 820 chipset supports the following ratios and can be supported by the DRCG and DRCG+ or derivative devices. Contact your DRCG vendor for information on DRCG, DRCG+, and derivative products. 100 MHz Host Bus 133 MHz Host Bus Frequency Multiplier Frequency Multiplier 100 / 300 6:1 133 / 266 4:1 100 / 400 8:1 133 / 356 16:3 133 / 400 6:1 3.
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5 System Manufacturing
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System Manufacturing System Manufacturing 5.1 5 In Circuit FWH Flash BIOS Programming All cycles destined for the FWH Flash BIOS appear on PCI. The ICH hub interface to PCI Bridge puts all processor boot cycles out on PCI (before sending them out on the FWH Flash BIOS interface to the FWH Flash BIOS). If the ICH is set for subtractive decode, these boot cycles can be accepted by a positive decode agent out on PCI.
System Manufacturing 5.3.2 PCB Materials PCB tolerances determine Z0 variation. Those tolerances include trace width, pre-preg thickness, plating thickness, and dielectric constant. Pre-preg type impacts H tolerance and εr including single ply, 2-ply, and resin content. To design to the correct Z0 variation, PCB’s typically need to meet the following (see Table 5-2): • Height tolerance ±10% (~ 0.4 mil) • Width tolerance ±2.5% (~ 0.4 mil) • εr tolerance ±5% (~0.2) Stackup Requirement: 28Ω ±10% Figure 5-1.
System Manufacturing 5.3.4 Test Coupon Design Guidelines Characterization and understanding of the trace impedance is critical for delivering reliable systems at the increased bus frequencies. Incorporating a test coupon design into the motherboard makes testing simpler and more accurate. The test coupon pattern must match the probe type being used.
System Manufacturing Figure 5-2. (a,b) Microstrip and Stripline Cross-section for 28 Ω Trace a) Microstrip Cross-Section for 28 Ohm trace 10 mils 18 mils 6 mils S G 2.1 mils G 4.5 mils b) Stripline Cross-Section for 28 Ohm trace 1.2 mils 6 mils 7 mils 13.5 mils 5 mils G S G 1.2 mils 5 mils 1.2 mils Note: 5.3.7 Don’t forget ground floods and stitching Impedance Calculation Tools The 3D Field Solvers (e.g.
System Manufacturing 5.3.9 Board Impedance/Stackup Summary 1. 7628 Cloth, 1 ply 0.007” when cured with 40% resin is the most popular and highest volume PCB in production today. This stackup will make routing impossible. • Fab Construction (4 Layers) • Zo = 70 Ω ± 15% Figure 5-3. 7 mil Stackup (Not Routable) Component Side Layer: 1/2 oz Cu 7 Mil Prepreg Ground Layer 2: 1 oz Cu Not Routable Total Thickness = 62 mils Ground Layer 3: 1 oz Cu 7 Mil Prepreg Solder Side Layer 4: 1/2 oz Cu 2.
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6 System Design Considerations
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System Design Considerations System Design Considerations 6.1 Power Delivery 6.1.1 Terminology and Definitions 6 Term Definition Suspend-ToRAM (STR) In the STR state, the system state is stored in main memory and all unnecessary system logic is turned off. Only main memory and logic required to wake the system remain powered.
System Design Considerations 6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery Figure 6-1 shows the power delivery architecture for the Intel® 820 Chipset Reference Board. This power delivery architecture supports the “Instantly Available PC Design Guidelines” via the suspend-to-RAM (STR) state. During STR, only the necessary devices are powered. These devices include: main memory, the ICH resume well, PCI wake devices (via 3.
System Design Considerations In addition to the power planes provided by the ATX power supply, an instantly available Intel® 820 chipset based system (using Suspend-to-RAM) requires 7 power planes to be generated on the board. The requirements for each power plane are documented in this section. In addition to onboard voltage regulators, the Intel® 820 Chipset Reference Board will have a 5V Dual Switch.
System Design Considerations The Intel® 820 Chipset Reference Board is using a switching regulator from 5V Dual. It may be possible to use a linear regulator to regulate from 3.3VSB, however the thermal characteristics must be considered. Additionally, a low drop out linear regulator would be necessary. If 2.5VSBYis regulated from 3.3VSB, it is important the 3.3VSB regulator can supply enough current for all the 3.3VSB device requirements as well as the 2.5VSBY requirements. Refer to the 1.
System Design Considerations System designers need to be aware of this requirement while designing the voltage regulators and selecting the power supply. For further details on the voltage sequencing requirements, refer to the latest Intel® 820 Chipset: 82820 Memory Controller Hub (MCH) datasheet. 3.3VSB The 3.3VSB plane powers the suspend well of the ICH and the PCI 3.3Vaux suspend power pins. The 3.
System Design Considerations 6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization Tie a single core well GPO with a default high state to both the S0 and S1 pins of the DRCG (i.e., tie S0 and S1 together and then connect to a GPO as shown in Figure 6-3). When the core power supply to the system is turned on, the DRCG enters a test mode and the output frequency will match the input REFCLK frequency. For details on this DRCG mode, refer to the latest DRCG specification.
System Design Considerations 6.2 Power Plane Splits Figure 6-4 shows an EXAMPLE of the power plane splits on an Intel® 820 chipset platform. Figure 6-4. Power Plane Split Example 6.3 Thermal Design Power The thermal design power is the estimated maximum possible expected power generated in a component by a realistic application. It is based on extrapolations in both hardware and software technology over the life of the product. It does not represent the expected power generated by a power virus.
System Design Considerations 6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip) To reduce the component count and BOM cost of the Intel® 820 chipset platform, Intel has developed an ASIC component that integrates miscellaneous platform logic into a single chip. The Glue Chip 3 is designed to integrate some or all of the following functions into a single device. By integrating much of the required glue logic into a single device, overall board cost can be reduced.
A Reference Board Schematics: Uni-Processor
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Reference Design Schematics: Uni-Processor Reference Design Schematics: Uni-Processor A.
8 7 6 5 4 3 2 1 INTEL(R) 820 CHIPSET UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS REV F (2 RIMM) D Title Cover Sheet 1 Block Diagram 2 Processor Connector 3, 4 Clock Synthesizer C 5 MCH 6, 7 ICH 8, 9 FWH 10 RIMM Sockets 11 Super I/O 12 Audio 13,14 Audio/Modem Riser 15 LAN 16,17 System B 18 Note that these schematics are preliminary and are subject to change.
8 7 6 5 4 3 2 1 Block Diagram Device Table VRM D Processor Clock DATA CTRL ADDR REFERENCE DESIGNATOR DATA CTRL ADDR AGP Bus AGP Rambus 2 RIMM Modules MCH C IDE Primary UltraDMA/66 PCI CNTRL USB Port 2 AC’97 Link LPC Bus AC’97 Audio Modem 82559 LAN SIO B FWH Keyboard Floppy Parallel PCI CONN 4 PCI CONN 3 PCI ADDR/DATA USB PCI CONN 2 ICH USB Port 1 PCI CONN 1 IDE Secondary U20 U14 U19 U3 U15 U18 U13 U10 U5 U8 U2 U11 U12 U16 U4, U6 U1 U17 U9 U7 DEVICE TYPE 74LVC06A 74
8 7 6 5 4 3 2 1 Processor Connector HA#[31:0] HD#[63:0] 6 J14 B A 8 7 D SC242 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#32 HA#33 HA#34 HA#35 B98 A100 A97 B99 B96 B95 A99 A96 B92 B94 A93 A95 B90 A92 B91 A91 A89 B86 B87 A85 A87 B83 B88 B82 A84 B84 B80 A81 A83 B79 A79 A80 B78 VID0 VID1 VID2 VID3 VID4 B120 A120 A119 B119 A121 VID0 VID1 VID2 VID3 VID4 VID[4:0] RS
8 7 6 5 4 3 2 1 Processor Connector VTT1_5 VCCVID VCC5 VCC3_3 D ITP D VCC3_3 VCC2_5 VTT1_5 VCC2_5 R19 150 330 R142 330 R139 R145 1K 1K R171 1K R167 R157 240 TDI TDO TRST# 680 R140 ITPREQ# ITPRDY#_R 240 47 R152 ITPCLK 5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 4 PICD0 PICD1 PICCLK 8,32 8,32 5 ITPPRDY# 47 R163 0K 0K R100 0K R93 0K R103 R104 0K R101 5 31 4,6 0.
8 7 6 5 4 3 2 1 VCC2_5 Clock Synthesizer VCC3_3 1 L20 1 2 L21 2 FBHS01L Provide at least one 0.1uF decoupling cap per power pin. FBHS01L VCC2_5_CK133_FB VCC_3_3_CK133_FB 10UF 0.1UF 0.1UF 0.1UF 0.1UF R164 ICHPCLK 8 PCLK1 20 PCLK2 20 PCLK3 21 PCLK4 21 PCLK5 16 FWHPCLK 10 SIO_PCLK7 12 AGPCLK_CONN 19 MCH_CLK66 7 ICH_CLK66 9 TEST_CLK6637 ICH_48MHZ 9 ICH_14MHZ 9 SIO_14MHZ 12 33 33 R183 33 33 R187 33 33 R194 33 R201 R195 R211 R147 33 33 22 22 No stuff R106 for debug.
3 RAMREF 2 VTT1_5 VTT1_5 75-1% R143 0.001UF 150-1% R144 C187 80.6-1% R160 C MCH_AGPREF 470PF VCC1_8 B RS#[2:0] 3 RAMREF 6,11 HREQ#[4:0] 3 VCC1_8 MCHCLK V2 RSTIN# HLCOMP F20 A18 PCIRST# MCH_HLCOMP TEST/GRCOMP T15 GRCOMP 5 MCH_AGPREF_CG Place MCH_AGPREF circuit near the MCH. 4 4 4 4 4 4 4 4 4 4 4 HCLKIN 80.
8 7 6 5 4 3 2 1 MCH U10 MCH_096 B 5 VCC1_8 C361 C359 0.1UF C360 0.1UF C362 A 19,32 19,32 GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GPAR GREQ# GGNT# PIPE# 19,32 19,32 19,32 0.1UF 19,32 G_FRAME# G_DEVSEL# G_IRDY# G_TRDY# G_STOP# G_PAR G_REQ# G_GNT# PIPE# W18 CLK66 RBF# WBF# V16 RBF# V15 WBF# ST0 ST1 ST2 ST[2:0] 0.
8 7 6 5 4 3 2 1 ICH U13 ICH_096 5 CBE0# CBE#1 CBE#2 CBE#3 DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PCIRST# PLOCK# SERR# PERR# PCI_PME# REQ#A GNT#A D9 B3 A2 C4 D5 A9 J5 B9 A1 E9 K1 N6 DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PCIRST# PLOCK# SERR# PERR#/GPIO7 PME# GPIO0/REQ#A P5 GPIO16/GNT#A ICHPCLK C14 PCICLK HUB AD22 AD23 AD24 AD25 AD26 AD27 AD28 HL0 D17 HL1 HL2 HL3 HL4 HL5 E17 F17 G16 J15 K16 HL6 HL7 HL8 HL9 K17 L17 H15 J17 HL10 HL11 J14 F16 G17 H17 M17 J13 HL_STB HL_STB# HLCOMP HUBREF
6 5 4 C246 + 1UF R317 R254 8.2K 1K R233 C247 + 1K VBAT_RTC 3,11,32 3,11,32 32 2 2.2UF R250 VBAT_RC 12 12 C249 + 2 1 C 3 1 8.2K 8.2K R232 8.2K R247 BAT1 10M 5 5 5 R249 10M Y4 XTAL Use CR2032 battery. S tra p S afe M ode ICH s trap* JP 5 IN O UT 12PF JP 26 IN O UT 12PF C250 S tra p No W D Reboot Reboot on W D* 15 13,15 13,15 9,13,15 13,15 15 9,18 2 1 32.768KHZ C251 R212 8.2K R215 B CM O S Norm al* Clear 8.
8 7 6 5 4 3 2 1 FWH VCC3_3 D C301 C298 C297 C308 0.1UF VCC3_3 0.1UF Do not tie Vpp to 12V. Vpp should be tied to VCC3_3 for onboard programming. 0.1UF VCC3_3 0.1UF D U16 C305 C300 0.1UF 0.1UF 1 FWH_IC 2 8.2K 3 4 5 6 R298 FGPI4 7 8.2K 8 FWHPCLK 9 10 VPP_R 11 PCIRST# 12 13 14 R300 15 FGPI3 8.2K FGPI2 16 FGPI1 17 FGPI0 18 R296 C 5 R299 0K 6,8,11,12,16,19,20,21,22 R303 22 22 S66DETECT P66DETECT R305 R306 8.
8 7 6 5 4 2 As shown, RIMMs are 184-pin connectors.
8 7 6 5 4 VCC5 3 2 1 VCC3_3 9 8,12,21,32 SIO_PCLK7 5,12 KBDAT 26 KBCLK MDAT MCLK 26 26 26 KBRST# A20GATE 8,32 8,32 IRRX IRTX 18 18 C C320 C317 470PF 470PF 25 25 25 25 25 25 25 25 25 25 LPC header. For debug only.
8 7 6 5 4 3 2 1 AC’97 Audio VCC3_3 VCC12 VR2 MC78M05CDT 1 10UF 0.1UF 2 C49 C21 AGND AGND C77 C48 + C62 0.1UF 1 GND 4 C83 10UF 2 13,14 VCC3_3 L17 13,14 D No stuff C358. C358 0.1UF 0.1UF 2 C57 + 1 VCC5_AUDIO 0.1UF 3 +5V 1 VIN 0.1UF VCC5_AUDIO D AGND AGND 0.1UF R67 AC97_SPKR_R C76 0.1UF VCC3_3 10PF R29 No stuff C84. 100K No stuff R28 14 100K No stuff 14 AC_XTAL_IN Y1 XTAL AC_XTAL_OUT C94 C95 2 24.576MHZ 2 22PF 1 22PF C16 EAPD 0.
8 7 6 5 4 3 2 AC’97 Audio Stereo HP/Spkr out HP_OUTA D C8 AGND + 1UF-TANT C25 1 2 + 1UF-TANT 1 1 2 L3 AGND OUTA VDD INA OUTB BYPASS INB GND SHUTDN VCC5_AUDIO HP_OUTB 8 7 6 5 EAPD 13 C4 13 1 AGND 2 AGND + 1 R3 20K 1 2 3 4 C14 LNLVL_L_C + C13 1 2 + 1UF-TANT 20K U1 LM4880 LNLVL_R_R AC_BYPASS 2 C AGND LNLVL_L_R AGND 1 2 + 1UF-TANT R1 LNLVL_R_C C26 2 + 10PF-NPO C22 + 10PF-NPO 1 2 J5 LINE_IN_R_FB LI25 LI24 LI23 LI22 LINE_IN_L_FB LI21 DB15_AUD_STK 2 L2 LINE_
8 7 6 5 4 3 2 1 AC’97 Audio/Modem Riser D D VCC3_3SBY VCC3_3 VCC5 VCC12 VCC12- R68 VCC3_3SBY J8 4.7K U3 14 6 PRI_DWN_RST# C 13 13 4 PRI_DWN_U 5 7 SN74LVC08A B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 MONO_OUT PRI_DWN# 3 1 JP2 2 B12 B13 B14 B15 B16 9,13 9 AC_SDATAOUT AC_RST# Au d io Do w n E nable* Dis able JP 2 1-2 2-3 KEY KEY GND[3] RESV[3] RESV[4] +3.
8 7 6 5 4 3 2 1 VCC3_3SBY PWROK LAN_RSMRST# 7,9,29,31 17 2 25MHZ Y2 XTAL A 9,32 9,32 1 C101 22PF 8 B9 A9 ALERTCLK_SBY A10 ALERTDATA_SBY C9 C96 22PF 7 E12 G5 G6 H5 H6 H7 H8 J5 J6 J7 J8 J9 J10 J11 K4 K5 K6 K7 K8 K9 K10 K11 L4 L5 L9 L10 VCC[0] VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] LAN_X1 N11 X1 LAN_X2 P11 X2 C13 C14 E13 E14 TDP TDN
8 7 6 5 4 3 2 1 LAN 0.1UF RDN 0.1UF RXC_J 75 R10 75 R8 75 R5 75 SPEED_J R73 330 R78 330 R60 330 LI_J ACT_J 330 ACTLED ACTLED C 16,17 9,31 16 RDC_J C31 SPEEDLED 16 For debug only. Hold LAN in reset. J17 1 2 3 RSMRST# LAN_RSMRST# C78 0.1UF XC_R 82559 L A N E n a b le * D is a b le C5 No stuff C5. C5 must be rated at 1500V. LILED 16,17 16,17 0.
6 5 4 VCC3_3SBY 1M 470 14 7 SN74LVC07A VCC3_3 IDE_ACTIVE GND VCC3_3 C354 C355 470PF U19 R355 470PF 14 VCC 8 9 220 R354 10K C VCC5 7 SN74LVC07A GND KEYLOCK# 12 SPKR_FP JP25 AC97_SPKR 3 Speaker Circuit 13 2 PC_BEEP R350 O n b o a rd S p k r E n a b le * D is a b le P_BEEP B 1 3 2 2.2K JP 25 2 -3 1 -2 R352 SPKR_Q C Q15 E INFRARED VCC3_3 C316 POWER SW.
7 6 5 4 AGP Connector 2 1 VCC12 SBA[7:0] D PIRQ#B 8,20,21,32 5 VCC3_3SBY C B A 7 GAD[31:0] 7 GC/BE#[3:0] 7 J13 AGP4XU_20 VCC5 B1 B2 B3 USBAGP+ B4 23 B5 B6 B7 AGPCLK_CONN GREQ# B8 7,32 B9 B10 ST0 B11 ST2 B12 RBF# 7,32 B13 B14 B15 SBA0 B16 B17 SBA2 SBSTB B18 7,32 B19 B20 SBA4 B21 SBA6 B22 B23 B24 B25 B26 GAD31 B27 GAD29 B28 B29 GAD27 B30 GAD25 B31 ADSTB1 B32 7,32 B33 GAD23 B34 B35 GAD21 B36 GAD19 B37 B38 GAD17 B39 GC/BE#2 B40 GIRDY# B41 7,32 B42 B43 B44 B45 B46 GDEVSEL# 7,32 B47 B48 GPERR#
8 7 6 5 4 3 2 1 VCC5 VCC5 VCC3_3 8,19,20,21,32 8,20,21,32 PIRQ#B PIRQ#D PRSNT#11 20 PRSNT#12 20 PREQ#0 8,32 AD31 AD29 C AD27 AD25 AD21 AD19 AD17 C_BE#2 8,16,20,21,32 8,20,21,32 8,16,20,21,32 B IRDY# A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 PLOCK# PERR# SERR# C_BE#1 AD14 AD12 AD10 PIRQ#A PIRQ#C A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 8,16,19,20,21,32 8,20,21,32 PIRQ#C PIRQ#A 8,20,21,32 8,16,19,20,21,32 PRSNT#21 20 VCC3_3SBY PCIRST#
8 7 PCI Connectors 2 and 3 6 VCC3_3 B3 B4 B5 B6 PIRQ#A PIRQ#C PRSNT#31 8,16,19,20,21,32 8,20,21,32 21 PRSNT#32 21 5 8,32 PCLK3 PREQ#2 AD31 AD29 C AD27 AD25 AD21 AD19 AD17 C_BE#2 8,16,20,21,32 8,20,21,32 8,16,20,21,32 B 8,16,20,21,32 IRDY# DEVSEL# SERR# C_BE#1 AD14 AD12 AD10 PCIRST# A40 A41 A42 A43 A44 A45 R255 0K 6,8,10,11,12,16,19,20,21,22 PCLK4 5 PGNT#2 8,32 PREQ#5 8,32 PCI_PME# AD30 8,16,19,20,21 AD31 AD29 AD28 AD26 AD27 AD25 AD24 R_AD23 C_BE#3 AD23 21 AD22 AD20 AD2
8 7 6 5 4 3 2 1 IDE Connectors Primary IDE Secondary IDE PDD[15:0] SDD[15:0] 9 J21 PIORDY 9 8,32 5.6K R335 9 PDIOW# PDIOR# 9 9 PDDACK# IRQ14 PDA1 PDA0 C 9 18 PDCS#1 IDEACTP# 1K R321 9 SDIOW# SDIOR# 9 9 SIORDY 9 8,32 SDDACK# IRQ15 SDA1 SDA0 9 9 18 C329 PDA2 SDCS#1 IDEACTS# D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 IDE_JS S66DETECT10 SDCS#3 9 SDA2 0.047UF PDA[2:0] C C318 SDA[2:0] 0.
8 7 4 3 2 1 VCC3_3 R83 D 5 330K USB Connectors 6 D L11 USBPWR1_F 2 1 AC97_OC# 15 C99 C44 68UF-TANT 0.1UF 0K R82 Do Not Stuff C98, C99 must have low ESR.
8 7 6 5 4 3 2 1 Parallel Port VCC5 CR1 1 D 3 VCC5_DB25_CR D MMBD914LT1 5 6 7 8 2.2K RP4 2.2K RP3 2.2K 4 3 2 1 4 3 2 1 5 6 7 8 5 6 7 8 RP2 RP1 2.2K 2.
8 7 6 5 4 3 2 1 Serial Ports VCC5 VCC12 D U4 1 2 3 4 5 6 7 8 9 10 J6 DB25_DB9_STK DCD DSR RXD RTS TXD CTS DTR RI GND A1 A6 A2 A7 A3 A8 A4 A9 A5 DCD0_C DSR0_C RXD0_C RTS0_C TXD0_C CTS0_C DTR0_C RI0_C 2 CP8 4 CP8 8 100PF 6 100PF 6 100PF CR2 BAT54C 3 1 RI_CR ICH_RI# 8 100PF 5 100PF 3 CP1 7 100PF 1 CP1 5 100PF 3 CP8 7 100PF 1 CP8 4 CP1 VCC12- R17 10K C 9 D COM1 GD75232 VCC12 VCC RY0 RA0 RY1 RA1 RY2 RA2 DA0 DY0 DA1 DY1 RY3 RA3 DA2 DY2 RY4 RA4 GND VCC-12 2 CP1 12 12 12 12 12 12 12
8 7 6 5 4 3 2 1 Keyboard/Mouse/Floppy VCC5 D D RP17 1 2 3 4 VCC5 8 7 6 5 Floppy Connector F1 1 VCC5_KBMS_F 2 1.
8 7 6 5 4 3 2 1 Game Port D D VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 12 12 12 12 C 12 J1BUTTON1 J2BUTTON1 JOY1X JOY2X 1K 1K R33 R32 1K R36 1K R37 4.7K R35 4.7K R39 VCC5 R21 R22 JOY1X_R JOY2X_R 2.2K 5% 2.2K 5% R34 MIDI_OUT MIDI_OUT_R 47 12 12 12 12 12 JOY2Y_R R23 JOY2Y JOY1Y J2BUTTON2 J1BUTTON2 MIDI_IN R24 2.2K JOY1Y_R 5% 2.2K 5% R38 MIDI_IN_R 47 J5 DB15_AUD_STK 31 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 32 C C69 0.01UF 25V 10% C68 1 1 470PF C67 0.
8 7 6 5 4 3 2 VCC3_3 VCC12 VRM 1 VCC5 R71 5.6K 220 R332 5.1-5% VCC5 D R53 VRM requirements are based on VRM8.4 spec . D VRM_PWRGD PVCC_R 4,31 C97 + 1UF-X7R L19 1UH 1 2 DO3316P-102 Place caps next to output FETs. C82,C87,C107,C111 must support >6A of RMS current. 1 1 1 + 1200UF C107 + 1200UF C82 1 C118, C119 must be next to FETs. 5 6 7 8 5 6 7 8 C118 1.
7 6 5 4 3 Voltage Regulators VCC 5V DUAL VOLTAGE SWITCHER VCC5SBY The VCC5DUAL plane should not drive any logic components requiring 5V. It should be used only for further regulation of lower voltage power planes because the true voltage of VCC5DUAL will not remain constant Rdson of the FET is not negligible for large currents VCC12 VCC12 D VCC5DUAL + 10UF B 1 2 10K 1 1 + + + 2 2 2 2 2 22UF 1 Route VR6 GND to VDDQ output caps and then via to ground.
8 7 6 5 4 3 2 1 Voltage Regulators VCC5DUAL D D C315 1UF-X7R 1 + 2 VCC 2.5 Standby Voltage Regulator C314 100UF 1 + 2 VCC2_5SBY_TG VCC2_5SBY_SW R295 D3 D4 S2 G2 + 11K + R302 1 C326 2 R294 VCC2_5SBY_BG 100-1% R301 + 1 C325 2 T510 10K A 100-1% C- R297 D1 D2 S1 G1 8 7 1 2 0.1UF CR10 C307 C312 MBRS130LT3 -C CMDSH-3 + 0.1UF 4.7UF 330PF C306 2 C299 1000PF C292 + 2 C C304 100PF 100PF SBY_ITH_R 68PF 0.1UF 100-1% R258 1 1 A 0.
8 7 6 5 4 3 2 1 Power Connector ITP Reset circuit. For debug only. VCC3_3 U15 14 1 VCC5SBY C U20 14VCC 5 6 SLP_S3# GND SN74LVC06A7 VCC5 SLP_S3 SN74LVC06A has 5V output tolerance. 11 12 13 14 15 16 17 18 19 20 U15 14 3 POK_U1 4 POK_U2 1 2 74LVC14A7 3_3V11 -12V GND13 PS_0N GND15 GND16 GND17 -5V 5V19 5V20 3_3V1 3_3V2 GND3 5V4 ATX GND5 5V6 GND7 PW_OK 5VSB 12V 1 2 3 4 5 6 7 8 9 10 4 U3 3 POK_U3 14 7 SN74LVC08A VCC12 J24 4.
8 7 6 5 4 3 2 1 PCI/AGP Pullups/Pulldowns VCC5 PCI D 8,20,21 8,20,21 AGP PIRQ#C PIRQ#D 8 7 6 5 FRAME# IRDY# TRDY# DEVSEL# 8 7 6 5 RP6 1 2 3 4 2.7K 8,16,20,21 8,16,20,21 8,16,20,21 8,16,20,21 RP10 19 19 1 2 3 4 PROCESSOR RP11 8 7 6 5 STOP# PLOCK# PERR# SERR# 4,8 4,8 4 2.7K 8,20 C 8,20 8,21 8,16 8 8,21 R112 4,8 R111 2.7K 4,8 2.7K R115 R216 2.7K 2.7K R213 R109 2.
8 7 6 5 4 3 2 1 Rambus Termination D D VCC1_8 C280 TERM_DQB3 TERM_DQB4 TERM_DQB5 TERM_DQB6 TERM_DQB7 TERM_DQB8 TERM_ROW0 TERM_ROW1 TERM_ROW[2:0] 11 TERM_ROW2 TERM_COL0 TERM_COL1 TERM_COL2 TERM_COL[4:0] 11 TERM_COL3 TERM_COL4 B C283 R284 R268 R267 R266 28 28 28 28 0.1UF C275 R265 R264 R263 R262 28 28 28 28 0.1UF C276 R261 R260 R275 R274 28 28 28 28 0.1UF C271 R276 R269 R271 R270 28 28 28 28 0.1UF C277 R273 R272 28 28 C282 0.1UF C273 0.
8 7 6 5 4 3 2 1 Decoupling MCH Decoupling 0.01UF 0.01UF 0.01UF 0.01UF C288 C226 C284 C264 C289 C235 C302 0.1UF Place a VCMOS1_8SBY 0.1uF cap at each RIMM. VCC3_3SBY U15 14 U3 8 14 11 U15 14 12 13 13 U3 11 14 10 74LVC14A7 VCC3_3 U19 12 3 74LVC14A7 VCC 4 14 C344 0.1UF Un-used Gates VCC3_3SBY Place these caps on solder side 9 10 C343 0.1UF C 7 SN74LVC08A 0.01UF 100UF Place 100uF caps, 0.1 ohm ESR, among RIMM connectors. VDDQ B 0.1UF 100UF 100UF C365 4.
8 7 6 5 4 3 2 1 Decoupling C339 C331 C36 C346 1 2 + 22UF C342 1 2 + 22UF 0.1UF 0.1UF C89 0.1UF 0.1UF 0.1UF D C Termination Decoupling VTT1_5 VCC3_3SBY C127 C129 C150 C133 10UF 0.1UF 0.1UF 0.1UF C128 C149 10UF 0.1UF B 0.1UF 0.01UF C130 C138 10UF 0.1UF 0.01UF C115 10UF 0.1UF 0.01UF C148 C132 10UF C357 C131 10UF C65 C141 10UF 0.1UF C259 C136 10UF 0.1UF C64 C135 10UF C240 C137 10UF C139 VCCVID C134 B 0.1UF 0.
8 7 6 5 4 3 2 1 Revision History Revision 1.01 D D Pg 6 Modified MCH_AGPREF circuit, changed 432 ohm to 1K ohm and 62 ohm to 80.6 ohm. Changed value of capacitor C194 from 0.1uF to 0.01uF. Pg 8 Modified HUBREF circuit, deleted R222, R223 & C217, changed C218 from 470pF to 0.1uF. Pg 11 Modified RIMM connectors to eliminate 3.3V, added 0.1uF decoup caps to SVDDA & SVDDB on each RIMM. Pg 33 Modified CMD and SCK termination values. Removed 470pF capacitors, Changed 93 ohm to 90.
8 7 6 5 4 3 2 1 Hub Link Connector For debug only. D D 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 B 7,8 HL0 HL1 HL2 HL3 HL9 HL_STB HL_STB# HL10 HL8 HL4 HL5 HL6 HL7 HUBREF 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 C TEST_CLK66 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 5 7,8 PROBE CONNECTOR 4 2 J26 6,8 C VCC1_8 B P08-050-SL-A-G A A REV: 1.
B Reference Board Schematics: Dual-Processor
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Reference Design Schematics: Dual-Processor Reference Design Schematics: Dual-Processor B.
8 7 6 5 4 3 2 1 INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE SCHEMATICS D Title Pa g e Co v e r S h e e t B lo c k Dia g r a m 2 Pr o c e s s o r Co n n e c to r 3, 4, 5, 6 Clo c k S y n th e s iz e r 7 MCH 8, 9 ICH 10, 11 FW H C 12 RIMM S o c ke ts 13 S u p e r I/O 14 A u d io 15, 16 A u d io /Mo d e m Ris e r 17 LA N B 18, 19 S y s te m 20 A G P Co n n e c to r 21 PCI Co n n e c to r s 22, 23 IDE Co n n e c to r s 24 US B Co n n e c to r s 25 Pa r a ll
8 7 6 5 4 3 2 1 Block Diagram Clock Device Table VRM D Processor Processor VRM DATA CTRL ADDR DATA CTRL ADDR REFERENCE DESIGNATOR DATA CTRL ADDR AGP Bus Rambus AGP 3 RIMM Modules MCH C IDE Primary UltraDMA/66 IDE Secondary PCI CNTRL ICH AC’97 Link LPC Bus AC’97 Audio Modem 82559 LAN SIO B FWH Keyboard Floppy Parallel Game Conn Mouse Serial 1 Serial 2 A PCI CONN 4 PCI ADDR/DATA USB Port 2 PCI CONN 3 USB PCI CONN 2 PCI CONN 1 USB Port 1 U20 U14 U19 U3 U9 U26
8 7 6 5 4 3 2 1 Processor Connector 0 HA#[31:0] HD#[63:0] 5,8 J15 B A 8 7 D SC242 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#32 HA#33 HA#34 HA#35 B98 A100 A97 B99 B96 B95 A99 A96 B92 B94 A93 A95 B90 A92 B91 A91 A89 B86 B87 A85 A87 B83 B88 B82 A84 B84 B80 A81 A83 B79 A79 A80 B78 VID0 VID1 VID2 VID3 VID4 B120 A120 A119 B119 A121 VID0 VID1 VID2 VID3 VID4 VID[4:0]
8 7 6 5 4 3 2 1 Processor Connector 0 VTT1_5 VCCVID VCC5 VCC3_3 D ITP D VCC3_3 VCC2_5 VTT1_5 VCC2_5 VTT1_5 150 R218 BINIT# B19 A21 A23 B24 A24 BP2# BP3# BPM0# BPM1# BINIT# PICD0 PICD1 PICCLK A19 B22 B18 PICD0 PICD1 PICCLK 150 330 R380 330 R76 R387 1K 1K R18 1K R63 240 R159 R17 4 4 R376 TRST# 6 ITPREQ# 4 ITPRDY#_R ITPREQ1# ITPRDY1#_R 8.
8 7 6 5 4 3 2 1 Processor Connector 1 HA#[31:0] HD#[63:0] 3,8 J120 B A 8 7 D SC242 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#32 HA#33 HA#34 HA#35 B98 A100 A97 B99 B96 B95 A99 A96 B92 B94 A93 A95 B90 A92 B91 A91 A89 B86 B87 A85 A87 B83 B88 B82 A84 B84 B80 A81 A83 B79 A79 A80 B78 VID0 VID1 VID2 VID3 VID4 B120 A120 A119 B119 A121 VID1[0] VID1[1] VID1[2] VID1[3] V
8 7 6 5 4 3 2 1 Processor Connector 1 VTT1_5 D VCC5 VCC5 C BREQ#0 14 5 6 9 8 1K B A25 A27 B26 A28 B27 A29 A31 B28 DEP#0 DEP#1 DEP#2 DEP#3 DEP#4 DEP#5 DEP#6 DEP#7 BINIT# B19 A21 A23 B24 A24 BP2# BP3# BPM0# BPM1# BINIT# PICD0 PICD1 PICCLK1 A19 B22 B18 PICD0 PICD1 PICCLK C Q16 R392 1 3 2 E 7 VCC3_3 R390 C Q17 4.7K B 1 3 2N3904 CPURST# R103 2 8.
8 7 6 5 4 3 2 1 VCC2_5 Clock Synthesizer VCC3_3 1 L20 1 2 L21 2 FBHS01L Provide at least one 0.1uF decoupling cap per power pin. FBHS01L VCC_3_3_CK133_FB VCC2_5_CK133_FB 10UF 0.1UF 0.1UF 0.1UF 0.1UF 10 6 ITPCLK R189 MCHCLK 22 R184 CPUHCLK 22 CPUHCLK1 R170 R164 33 33 R183 33 33 R187 33 33 R194 33 R201 R195 R211 R147 33 33 22 SIO_14MHZ 22 No stuff R106 for debug. VCC1_8 10 22 22 23 23 C 18 12 14 21 9 11 VDDIR pin on DRCG should be decoupled at the component with a 0.
3 RAMREF 2 VTT1_5 VTT1_5 75-1% R143 0.001UF 150-1% R144 C187 80.6-1% R160 C MCH_AGPREF 470PF VCC1_8 B RS#[2:0] 3,5 RAMREF 8,13 HREQ#[4:0] 3,5 VCC1_8 MCHCLK V2 RSTIN# HLCOMP F20 A18 PCIRST# MCH_HLCOMP TEST/GRCOMP T15 GRCOMP 7 MCH_AGPREF_CG Place MCH_AGPREF circuit near the MCH. 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 4,6 HCLKIN 80.
8 7 6 5 4 3 2 1 MCH U10 MCH_096 B 7 VCC1_8 C361 C359 0.1UF C360 0.1UF C362 A 21,34 21,34 GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GPAR GREQ# GGNT# PIPE# 21,34 21,34 21,34 0.1UF 21,34 G_FRAME# G_DEVSEL# G_IRDY# G_TRDY# G_STOP# G_PAR G_REQ# G_GNT# PIPE# W18 CLK66 RBF# WBF# V16 RBF# V15 WBF# ST0 ST1 ST2 ST[2:0] 0.
8 7 6 5 4 3 2 1 ICH U13 ICH_096 7 CBE0# CBE#1 CBE#2 CBE#3 DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PCIRST# PLOCK# SERR# PERR# PCI_PME# REQ#A GNT#A D9 B3 A2 C4 D5 A9 J5 B9 A1 E9 K1 N6 DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PCIRST# PLOCK# SERR# PERR#/GPIO7 PME# GPIO0/REQ#A P5 GPIO16/GNT#A ICHPCLK C14 PCICLK HUB AD22 AD23 AD24 AD25 AD26 AD27 AD28 HL0 D17 HL1 HL2 HL3 HL4 HL5 E17 F17 G16 J15 K16 HL6 HL7 HL8 HL9 K17 L17 H15 J17 HL10 HL11 J14 F16 G17 H17 M17 J13 HL_STB HL_STB# HLCOMP HUBREF
6 5 4 C246 1 + 2 1UF 2 1 + 1K VBAT_RTC 3 C VBAT_RC R317 8.2K R254 8.2K 1K 2 2.2UF R250 R233 C247 1 + 8.2K 3,5,13,34 3,5,13,34 34 14 14 C249 R232 8.2K R247 BAT1 10M 7 7 7 R249 Use CR2032 battery. 10M Y4 XTAL 12PF 12PF C250 17 15,17 15,17 11,15,17 15,17 17 11,20 2 1 32.768KHZ C251 R212 R215 B S tra p No W D Reboot Reboot on W D* S tra p S afe M ode ICH s trap* JP 26 IN O UT JP 5 IN O UT 8.2K 8.
8 7 6 5 4 3 2 1 FWH VCC3_3 D C301 C298 C297 C308 0.1UF VCC3_3 0.1UF Do not tie Vpp to 12V. Vpp should be tied to VCC3_3 for onboard programming. 0.1UF VCC3_3 0.1UF D U16 C305 C300 0.1UF 0.1UF 1 FWH_IC 2 8.2K 3 4 5 6 R298 FGPI4 7 8.2K 8 FWHPCLK 9 10 VPP_R 11 PCIRST# 12 13 14 R300 15 FGPI3 8.2K FGPI2 16 FGPI1 17 FGPI0 18 R296 C 7 R299 0K 8,10,13,14,18,21,22,23,24 R303 24 24 S66DETECT P66DETECT R305 R306 8.
8 7 6 5 4 3 1 J17 RIMM LDQA[8:0] D 9 C LCOL[4:0] 9 9 9 9 9 9 9 9 8,13 LROW2 LROW1 LROW0 LCOL4 LCOL3 LCOL2 LCOL1 LCOL0 B16 A18 B18 A20 B20 A22 B22 A24 LCLKFM LCLKFM# LCLKTM LCLKTM# B10 LCFM B12 LCFM# A14 LCTM A12 LCTM# LCMD LSCK LSIO B34 A34 B36 RAMREF LCMD LSCK SIO/SIN A51 VREFA B51 VREFB 3,5,11,13,34 SMBCLK_CORE SMBDATA_CORE A53 A55 A57 B56 A56 3,5,11,13,34 C228 0.
8 7 6 5 4 VCC5 3 2 1 VCC3_3 11,12,14 11,12,14 11,14 8,10,12,13,14,18,21,22,23,24 11 10,14,23,34 SIO_PCLK7 7,14 KBDAT 28 KBCLK MDAT MCLK 28 28 28 KBRST# A20GATE 10,34 10,34 IRRX IRTX 20 20 C C320 C317 470PF 470PF 27 27 27 27 27 27 27 27 24 23 22 21 20 25 26 27 17 30 29 LFRAME# LAD3 LAD2 LAD1 LAD0 LDRQ# LRESET# LPCPD# PME# SERIRQ PCI_CLK 56 57 58 59 63 64 KDAT KCLK MDAT MCLK KBDRST A20GATE 61 62 IRRX2/GP34 IRTX2/GP35 RXD0 TXD0 DSR#0 RTS#0 CTS#0 DTR#0 RI#0 DCD#0 84 85 86 87 88 8
8 7 6 5 4 3 2 1 AC’97 Audio VCC3_3 VCC12 VR2 MC78M05CDT 1 C48 + C62 0.1UF 1 2 C49 C21 AGND AGND C77 VCC3_3 L17 D 15,16 No stuff C358. C358 0.1UF 0.1UF 10UF 2 C57 10UF 2 C83 + 1 GND 4 0.1UF 15,16 1 VIN 0.1UF VCC5_AUDIO 3 +5V 0.1UF VCC5_AUDIO D AGND AGND 0.1UF R67 AC97_SPKR_R C76 0.1UF 46 45 48 47 17 11,17 11,17 11,17 11,17 VCC3_3 C84 10PF No stuff C84 R29 CS1 CS0 CHAIN_CLK EAPD Series resistors are for test purposes only.
8 7 6 5 4 3 2 AC’97 Audio Stereo HP/Spkr out HP_OUTA D AGND 2 LINE_IN_R_C + 1UF-TANT C25 1 2 + 1UF-TANT 1 20K J5 LINE_IN_R_FB LI25 LI24 LI23 LINE_IN_L_FB LI22 LI21 DB15_AUD_STK 2 L2 LINE_IN_L_C 1 2 L3 C26 1 2 + 10PF-NPO C22 1 2 + 10PF-NPO AGND VCC5_AUDIO HP_OUTB 8 7 6 5 C4 15 1 EAPD 15 AGND + R361 OUTA VDD INA OUTB BYPASS INB GND SHUTDN C14 LNLVL_L_C 1 2 3 4 2 C13 1 2 + 1UF-TANT 20K U1 LM4880 LNLVL_R_R AC_BYPASS 1 + 1UF-TANT R171 LNLVL_R_C + 2 C2 C6 1UF LNLV
8 7 6 5 4 3 2 1 AC’97 Audio/Modem Riser D D VCC3_3SBY VCC3_3 VCC5 VCC12 VCC12- R68 VCC3_3SBY J8 4.7K U3 14 6 PRI_DWN_RST# C 15 15 4 PRI_DWN_U 5 7 SN74LVC08A B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 MONO_OUT PRI_DWN# 3 1 JP2 2 B12 B13 B14 B15 B16 11,15 11 Audio Down Enable* Disable B17 B18 B19 B20 B21 B22 B23 JP2 1-2 2-3 KEY KEY GND[3] RESV[3] RESV[4] +3.
8 7 6 5 4 3 2 1 VCC3_3SBY PWROK LAN_RSMRST# 9,11,31,33 19 2 25MHZ Y2 XTAL A 11,34 11,34 1 C101 22PF 8 B9 A9 ALERTCLK_SBY A10 ALERTDATA_SBY C9 C96 22PF 7 E12 G5 G6 H5 H6 H7 H8 J5 J6 J7 J8 J9 J10 J11 K4 K5 K6 K7 K8 K9 K10 K11 L4 L5 L9 L10 VCC[0] VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] LAN_X1 N11 X1 LAN_X2 P11 X2 C13 C14 E13 E14 TDP
8 7 6 5 4 3 2 1 LAN 0.1UF RDN 0.1UF RXC_J 75 R10 75 R8 75 R365 75 SPEED_J R73 330 R78 330 R60 330 LI_J ACT_J 330 18,19 LILED 18,19 ACTLED 18,19 16 ACTLED 0.1UF C 18,19 11,33 18 RDC_J C31 SPEEDLED 18 15 TXC_J R6 LILED 13 RJ-4 RJ-5 RJ-7 RJ-8 2 1 RJ4_J 14 TDC RDC 18 3 4 5 6 RJMAG RJ-45 C79 TD+ TDRD+ RD- TDC_J 11 8 C61 R364 49.9-1% 10 12 9 7 TXC RXC No stuff C61, C79. RD_C R62 49.
6 5 4 VCC3_3SBY 1M 10K 10K R344 470 14 7 SN74LVC07A VCC3_3 IDE_ACTIVE GND VCC3_3 C354 C355 470PF U19 14 R354 VCC 8 9 IDEACTS# 470PF 10K C VCC5 7 SN74LVC07A GND KEYLOCK# 14 SPKR_FP JP25 AC97_SPKR 3 Speaker Circuit 15 2 PC_BEEP R350 Onboa rd S pkr E nable* Dis able JP 25 2-3 1-2 P_BEEP B 1 3 2 2.2K R352 SPKR_Q C Q15 E INFRARED VCC3_3 C316 POWER SW.
7 6 5 4 AGP Connector 2 1 VCC12 SBA[7:0] VCC5 D PIRQ#B 10,22,23,34 7 VCC3_3SBY C B A 9 GAD[31:0] 9 GC/BE#[3:0] 7 J13 B1 B2 B3 USBAGP+ B4 25 B5 B6 B7 AGPCLK_CONN GREQ# B8 9,34 B9 B10 ST0 B11 ST2 B12 RBF# 9,34 B13 B14 B15 SBA0 B16 B17 SBA2 SBSTB B18 9,34 B19 B20 SBA4 B21 SBA6 B22 B23 B24 B25 B26 GAD31 B27 GAD29 B28 B29 GAD27 B30 GAD25 B31 ADSTB1 B32 9,34 B33 GAD23 B34 B35 GAD21 B36 GAD19 B37 B38 GAD17 B39 GC/BE#2 B40 GIRDY# B41 9,34 B42 B43 B44 B45 B46 GDEVSEL# 9,34 B47 B48 GPERR# 34 B49 B
8 7 6 5 4 3 2 1 VCC5 VCC5 VCC3_3 10,21,22,23,34 10,22,23,34 PIRQ#B PIRQ#D PRSNT#11 22 PRSNT#12 22 PREQ#0 10,34 AD31 AD29 C AD27 AD25 C_BE#3 AD23 AD17 C_BE#2 10,18,22,23,34 10,22,23,34 10,18,22,23,34 B IRDY# DEVSEL# A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 PERR# SERR# C_BE#1 AD14 AD12 AD10 PIRQ#A PIRQ#C A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 10,18,21,22,23,34 10,22,23,34 10,22,23,34 10,18,21,22,23,34 22 VCC3_3SBY PCIRST# PIRQ#C PIRQ#
8 7 PCI Connectors 2 and 3 6 VCC3_3 B3 B4 B5 B6 PIRQ#A PIRQ#C PRSNT#31 10,18,21,22,23,34 10,22,23,34 23 PRSNT#32 23 7 10,34 PCLK3 PREQ#2 AD31 AD29 C AD27 AD25 AD21 AD19 AD17 C_BE#2 10,18,22,23,34 10,22,23,34 10,18,22,23,34 B 10,18,22,23,34 IRDY# DEVSEL# SERR# C_BE#1 AD14 AD12 AD10 PCIRST# A40 A41 A42 A43 A44 A45 R255 0K 8,10,12,13,14,18,21,22,23,24 7 PGNT#2 PCLK4 10,34 PREQ#5 10,34 PCI_PME# AD30 10,18,21,22,23 AD31 AD29 AD28 AD26 AD27 AD25 AD24 C_BE#3 AD23 AD22 AD20 AD21
8 7 6 5 4 3 2 1 IDE Connectors Primary IDE Secondary IDE PDD[15:0] SDD[15:0] 11 J21 PIORDY 11 10,34 5.6K R335 11 11 11 PDIOW# PDIOR# PDDACK# IRQ14 PDA1 PDA0 C 11 20 PDCS#1 IDEACTP# 1K R321 11 SDIOW# SDIOR# 11 11 SIORDY 11 10,34 SDDACK# IRQ15 SDA1 SDA0 11 11 20 C329 PDA2 SDCS#1 IDEACTS# D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 IDE_JS S66DETECT12 SDCS#3 11 SDA2 0.047UF PDA[2:0] C C318 SDA[2:0] 0.
8 7 4 3 2 1 VCC3_3 R83 D 5 330K USB Connectors 6 D L11 USBPWR1_F 2 1 AC97_OC# 17 C99 C44 68UF-TANT 0.1UF 0K R82 Do Not Stuff C98, C99 must have low ESR.
8 7 6 5 4 3 2 1 Parallel Port VCC5 CR1 1 D 3 VCC5_DB25_CR D MMBD914LT1 5 6 7 8 2.2K RP4 2.2K RP3 2.2K 4 3 2 1 4 3 2 1 5 6 7 8 5 6 7 8 RP2 RP1 2.2K 2.
8 7 6 5 4 3 2 1 Serial Ports VCC5 VCC12 D U4 1 2 3 4 5 6 7 8 9 10 J6 DB25_DB9_STK DCD DSR RXD RTS TXD CTS DTR RI GND A1 A6 A2 A7 A3 A8 A4 A9 A5 DCD0_C DSR0_C RXD0_C RTS0_C TXD0_C CTS0_C DTR0_C RI0_C 2 CP8 4 CP8 8 100PF 6 100PF 6 100PF CR2 BAT54C 3 1 RI_CR ICH_RI# 8 100PF 5 100PF 3 CP1 7 100PF 1 CP1 5 100PF 3 CP8 7 100PF 1 CP8 4 CP1 VCC12- R369 10K C 11 D COM1 GD75232 VCC12 VCC RY0 RA0 RY1 RA1 RY2 RA2 DA0 DY0 DA1 DY1 RY3 RA3 DA2 DY2 RY4 RA4 GND VCC-12 2 CP1 14 14 14 14 14 14
8 7 6 5 4 3 2 1 Keyboard/Mouse/Floppy VCC5 D D RP17 1 2 3 4 VCC5 8 7 6 5 Floppy Connector F1 1 VCC5_KBMS_F 2 1.
8 7 6 5 4 3 2 1 Game Port D D VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 14 14 14 14 C 14 J1BUTTON1 J2BUTTON1 JOY1X JOY2X 1K 1K R33 R32 1K R36 1K R37 4.7K R35 4.7K R39 VCC5 R21 R22 JOY1X_R JOY2X_R 2.2K 5% 2.2K 5% R34 MIDI_OUT MIDI_OUT_R 47 14 14 14 14 14 JOY2Y_R R23 JOY2Y JOY1Y J2BUTTON2 J1BUTTON2 MIDI_IN R24 2.2K JOY1Y_R 5% 2.2K 5% R38 MIDI_IN_R 47 J5 DB15_AUD_STK 31 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 32 C C69 0.01UF 25V 10% C68 1 1 470PF C67 0.
8 7 6 5 4 3 2 VCC3_3 VCC12 VRM 1 VCC5 R71 5.6K 220 R332 5.1-5% VCC5 D R53 VRM requirements are based on VRM8.4 spec . D VRM_PWRGD PVCC_R 33 C97 + 1UF-X7R L19 1UH 1 2 DO3316P-102 Place caps next to output FETs. C82,C87,C107,C111 must support >6A of RMS current. 1 1 1 + 1200UF C107 + 1200UF C82 1 C118, C119 must be next to FETs.
7 6 5 4 3 Voltage Regulators 1 AGP VDDQ VOLTAGE REGULATOR VCC 5V DUAL VOLTAGE SWITCHER VCC5SBY The VCC5DUAL plane should not drive any logic components requiring 5V.
8 7 6 5 4 3 2 1 Voltage Regulators VCC5DUAL D D C315 1UF-X7R + 1 2 C314 100UF + 1 2 VCC 2.5 Standby Voltage Regulator VCC2_5SBY_TG VCC2_5SBY_SW VCC2_5SBY 100PF C326 + 2 + C325 1 11K R302 1 2 R294 VCC2_5SBY_BG 100-1% R301 + AVX 330uF TPS x2 10K A 100-1% C- R297 0.1UF CR10 MBRS140T3 C312 Q11 SI4966DY 8 D1 7 D2 1 S1 2 G1 CMDSH-3 1 + 0.1UF 1 4.7UF + 2 C306 330PF SBY_ITH_R 10K -C C C304 330UF R295 + A 0.01 330UF 100PF Do not stuff C304.
8 7 6 5 4 3 2 1 Power Connector ITP Reset circuit. For debug only. VCC3_3 U15 14 1 VCC5SBY U20 14VCC 11,31 SLP_S3# 5 6 GND SN74LVC06A7 C 4.7K R347 VCC3_3SBY VCC5M 11 12 13 14 15 16 17 18 19 20 SLP_S3 SN74LVC06A has 5V output tolerance.
8 7 6 5 4 3 2 1 PCI/AGP Pullups/Pulldowns VCC5 PCI D 10,22,23 10,22,23 AGP PIRQ#C PIRQ#D 8 7 6 5 FRAME# IRDY# TRDY# DEVSEL# 8 7 6 5 RP6 1 2 3 4 9,21 9,21 2.7K 10,18,22,23 10,18,22,23 10,18,22,23 10,18,22,23 RP10 21 21 1 2 3 4 PROCESSOR RP11 8 7 6 5 STOP# PLOCK# PERR# SERR# 4,6,10 4,6,10 10,22 C 10,22 10,23 10,18 10 10,23 R112 4,6,10 2.7K 4,6,10 2.7K R115 R216 2.7K 2.7K R213 R109 2.7K PREQ#2 PREQ#3 PREQ#4 PREQ#5 4,6,10 R111 PREQ#0 PREQ#1 FLUSH# 4,6 2.
8 7 6 5 4 3 2 1 Rambus Termination D D VCC1_8 C280 TERM_DQB3 TERM_DQB4 TERM_DQB5 TERM_DQB6 TERM_DQB7 TERM_DQB8 TERM_ROW0 TERM_ROW1 TERM_ROW[2:0] 13 TERM_ROW2 TERM_COL0 TERM_COL1 TERM_COL2 TERM_COL[4:0] 13 TERM_COL3 TERM_COL4 B 0.1UF C283 R284 R268 R267 R266 28 28 28 28 0.1UF C275 R265 R264 R263 R262 28 28 28 28 0.1UF C276 R261 R260 R275 R274 28 28 28 28 0.1UF C271 R276 R269 R271 R270 28 28 28 28 0.1UF C277 R273 R272 28 28 C282 0.1UF C273 0.
8 7 6 5 4 3 2 1 Decoupling ICH Decoupling VCC2_5SBY VDDQ 0.01UF 0.1UF 0.1UF C272 C197 C144 0.01UF C143 0.
8 7 6 5 4 3 2 1 Bulk Decoupling VCC2_5 Decoupling C136 C135 0.1UF C134 0.1UF C131 0.1UF C371 1 2 + 22UF 0.01UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF VCC120.1UF 0.1UF C130 + 22UF 2 C132 C133 C369 C129 VCC12 1 C146 0.1UF + 22UF 2 C145 0.1UF C370 0.1UF 0.1UF C138 0.1UF 0.1UF D VTT1_5 0.1UF C137 0.1UF 0.1UF C148 0.1UF 0.1UF 1 C147 0.1UF 0.1UF 0.1UF C141 0.1UF 0.1UF Termination Decoupling VCC5 C139 0.1UF C176 0.1UF C175 0.1UF 0.1UF C172 0.
8 7 6 5 4 3 2 1 Revision History D D Pg 8 Modified MCH_AGPREF circuit, changed 432 ohm to 1K ohm and 62 ohm to 80.6 ohm. Changed value of capacitor C194 from 0.1uF to 0.01uF. Pg 10 Modified HUBREF circuit, deleted R222, R223 & C217, changed C218 from 470pF to 0.1uF. Pg 13 Modified RIMM connectors to eliminate 3.3V, added 0.1uF decoup caps to SVDDA & SVDDB on each RIMM. Pg 35 Modified CMD and SCK termination values. Removed 470pF capacitors, Changed 93 ohm to 90.
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