Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Sequence Specification Update — on 65 nm Process in the 775-land LGA Package supporting Intel® 64Φ Architecture, Intel® Virtualization Technology± and Intel® Trusted Execution Technologyŧ December 2010 Notice: The Intel® CoreTM2 Extreme and Intel® CoreTM2 Duo desktop processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
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Contents Contents .............................................................................................................................3 Revision History ...................................................................................................................4 Preface ...............................................................................................................................6 Summary Tables of Changes ......................................................................
Revision History Revision -001 -002 -003 Description • Initial release of the Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 Sequence Specification Update • Updated Erratum AI19, AI29 and AI40 • Added Erratum AI58-AI67 • Updated Erratum AI20, AI38 Date July 2006 Out of Cycle Aug 2006 Sept 2006 • Added Erratum AI68-AI77 • Updated Erratum AI72 -004 • Updated Status for Erratum AI55 in Errata table • Added Erratum AI78-AI82 Oct 2006 • Added Specification change AI1
Revision -013 Description • Added Erratum AI105 • Added Specification Clarification AI1 -014 • Updated Erratum AI14, AI25 and AI26 -015 • Included M0 stepping and G0 stepping information (updated summary tables of change and updated processor identification information) -016 • Added Errata AI106 to AI111 -017 -018 -019 • Added processor number E4400 on M0 stepping information • Updated Plan Status for AI33 and AI43 • Added Erratum AI112 • Added Erratum AI113 and AI114 Date Apr 2007 Out Of Cycle Ma
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number QDF Number is a several digit code that is used to distinguish between engineering samples. These processors are used for qualification and early design validation.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Item Numbering Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor specification updates: A= C= D= E= F= I= J= K= L= M= N= O= P= Q= R= S= T= U= V= W= X= Y= Z= AA = AB = AC = AD = AE = AF = AG = AH = AI = AJ = Dual-Core Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes AK = AL = AM = AN = AO = AP = AQ = AR = AS = AV = AW = AX = AY= AZ = AAA = AAB = AAC = AAD = AAE = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor Q6 00 sequence Dual-Core Intel® Xeon® processor 7100 series Intel® Celeron® processor 400 sequence Intel® Pentium® dual-core processor Quad-Core Intel® Xeon® processor 3200 series Dual-Core Intel® Xeon® processor 3000 series Intel® Pentium® dual-core desktop processor E2000 sequence Intel® Cel
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI10 X X X X X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled AI11 X X X X X No Fix A Write to an APIC Register Sometimes May Appear to Have Not Occurred AI12 X X X X X No Fix Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unexpected Thermal Interrupts AI13 X X X X X No Fix Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May be Incorrect AI14
Summary Tables of Changes NO B1 B2 L2 M0 AI31 X X X X AI32 X X X X AI33 X X X AI34 X X X X AI35 X X X AI36 X X X AI37 X X G0 Plan ERRATA Fixed Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect Fixed Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results X No Fix MSRs Actual Freque
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan AI52 X X X X X No Fix Last Branch Records (LBR) Updates May be Incorrect after a Task Switch AI53 X X X X X No Fix IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly AI54 X X X X X No Fix INIT Does Not Clear Global Entries in the TLB AI55 X X X X Fixed Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable Behavior AI56 X X X X Fixed Update of Read/Write (R/W) or User/Supervisor
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan AI74 X X X X X No Fix An Asynchronous MCE During a Far Transfer May Corrupt ESP AI75 X X X X Fixed In Single-Stepping on Branches Mode, the BS Bit in the Pending-Debug-Exceptions Field of the Guest State Area will be Incorrectly Set by VM-Exit on a MOV to CR8 Instruction AI76 X X X X X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint AI77 X X X X X No Fix BTM/BTS Branch-From Instruction Address M
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan AI96 X X X X X No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC.
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI117 X X X X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations AI118 X X X X X No Fix VM Exit with Exit Reason “TPR Below Threshold” Can Cause the Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field AI119 X X X X X No Fix Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations AI
Identification Information Identification Information Figure 1. Intel® Core™2 Duo Desktop Processor 2M SKU Package with 800 MHz FSB INTEL M ©'05 E4500 INTEL® CORE™2 DUO SLxxx [COO] 2.20GHZ/2M/800/06 [FPO] e4 ATPO S/N Figure 2. Intel® Core™2 Duo Desktop Processor 2M SKU Package with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6400 SLxxx [COO] 2.
Identification Information Figure 3. Intel® Core™2 Duo Desktop Processor 4M SKU Package with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6700 SLxxx [COO] 2.66GHZ/4M/1066/06 [FPO] e4 ATPO S/N Figure 4. Intel® Core™2 Duo Desktop Processor 4M SKU Package with 1333 MHz FSB INTEL M ©'05 E6850 INTEL® CORE™2 DUO SLxxx [COO] 3.
Identification Information Figure 5. Intel® Core™2 Extreme Processor Package INTEL M ©'05 INTEL® CORE™2 EXTREME 6800 SLxxx [COO] 2.
Component Identification Information Component Identification Information The Intel® Core™2 Extreme processor and Intel® Core™2 Duo desktop processor can be identified by the following values: Family1 Model2 0110b 1111b NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
Component Identification Information Table 1. Intel® Core™2 Duo Desktop Processor 2M SKU Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number Speed Core/Bus Package Notes SL9SA B2 2M 06F6h E6300 1.86 GHz / 1066 MHz 775-land LGA 1, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 15 SL9S9 B2 2M 06F6h E6400 2.13 GHz / 1066 MHz 775-land LGA 1, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 15 SL9TB L2 2M 06F2h E4300 1.
Component Identification Information Table 2. Intel® Core™2 Duo Desktop Processor 4M SKU Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number Speed Core/Bus Package Notes SLAA5 G0 4M 06FBh E6540 2.33 GHz / 1333 MHz 775-land LGA 1, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17 SLA9X G0 4M 06FBh E6550 2.33 GHz / 1333 MHz 775-land LGA 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17 SLA9V G0 4M 06FBh E6750 2.
Errata Errata AI1. Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI4.
Errata Workaround: Use the IRET instruction to return from a system call, if RF flag has to be set after the return. Status: For the steppings affected, see the Summary Tables of Changes. AI7. General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted Problem: When the processor encounters an instruction that is greater than 15 bytes in length, a #GP is signaled when the instruction is decoded.
Errata AI10. Single Step Interrupts with Floating Point Exception Pending May Be Mishandled Problem: In certain circumstances, when a floating point exception (#MF) is pending during single-step execution, processing of the single-step debug exception (#DB) may be mishandled.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AI13. Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May be Incorrect Problem: Performance-Monitoring Counter PMH_PAGE_WALK is used to count the number of page walks resulting from Data Translation Look-Aside Buffer (DTLB) and Instruction Translation Look-Aside (ITLB) misses. Under certain conditions, this counter may be incorrect. Implication: There may be small errors in the accuracy of the counter.
Errata Implication: There may be a smaller than expected value in the INST_RETIRED performance monitoring counter. The extent to which this value is smaller than expected is determined by the frequency of the above cases. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. AI16.
Errata ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system.
Errata Note that even if this combination of instructions is encountered, there is also a dependency on the internal pipelining and execution state of both instructions in the processor. Implication: Inexact-result exceptions are commonly masked or ignored by applications, as it happens frequently, and produces a rounded result acceptable to most applications. The PE bit of the FPU status word may not always be set upon receiving an inexact-result exception.
Errata Workaround: If the last page of the positive canonical address space is not allocated for code (4K page at 00007ffffffff000 or 2M page at 00007fffffe00000) then the problem cannot occur. Status: For the steppings affected, see the Summary Tables of Changes. AI23.
Errata The following Bus Performance Monitoring events will not count power management related events for local core-specificity: • BUS_TRANS_ IO (Event: 6CH) – Will not count I/O level reads resulting from package-resolved C-state • BUS_TRANS_ANY (Event: 70H) – Will not count Stop-Grants Implication: The count values for the affected events may be lower than expected. The degree of undercount depends on the occurrence of erratum conditions while the affected events are active.
Errata Workaround: Software should ensure that memory accesses in 32-bit mode do not occur above the 4G limit (0ffffffffh). Status: For the steppings affected, see the Summary Tables of Changes. AI28. EIP May be Incorrect after Shutdown in IA-32e Mode Problem: When the processor is going into shutdown state the upper 32 bits of the instruction pointer may be incorrect. This may be observed if the processor is taken out of shutdown state by NMI#.
Errata AI31.
Errata Implication: In this case, the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, including a General Protection Fault (GPF) or other unexpected behaviors. In the event that unpredictable execution causes a GPF the application executing the unsynchronized XMC operation would be terminated by the operating system.
Errata Due to this erratum, a logical processor may not resume execution until the next targeted interrupt event or O/S timer tick following a locked store that spans across cache lines within the monitored address range. Implication: The logical processor that executed the MWAIT instruction may not resume execution until the next targeted interrupt event or O/S timer tick in the case where the monitored address is written by a locked store which is split across cache lines.
Errata AI39. Cache Data Access Request from One Core Hitting a Modified Line in the L1 Data Cache of the Other Core May Cause Unpredictable System Behavior Problem: When request for data from Core 1 results in a L1 cache miss, the request is sent to the L2 cache. If this request hits a modified line in the L1 data cache of Core 2, certain internal conditions may cause incorrect data to be returned to the Core 1. Implication: This erratum may cause unpredictable system behavior.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI43. Concurrent Multi-processor Writes to Non-dirty Page May Result in Unpredictable Behavior Problem: When a logical processor writes to a non-dirty page, and another logicalprocessor either writes to the same non-dirty page or explicitly sets the dirty bit in the corresponding page table entry, complex interaction with internal processor activity may cause unpredictable system behavior.
Errata Implication: Non-bootstrap logical processors in the package that have not observed the error condition may be disabled and may not respond to INIT#, SMI#, NMI#, SIPI or other events. Workaround: When this erratum occurs, RESET# must be asserted to restore multi-core functionality. Status: For the steppings affected, see the Summary Tables of Changes. AI47. SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to the New EFLAGS.
Errata Implication: When the OS recovers from the second fault handler, the processor will no longer be in VM86 mode. Normally, operating systems should prevent interrupt task switches from faulting, thus the scenario should not occur under normal circumstances. Workaround: None Identified Status: For the steppings affected, see the Summary Tables of Changes. AI50. IA32_FMASK is Reset during an INIT Problem: IA32_FMASK MSR (0xC0000084) is reset during INIT.
Errata AI52. Last Branch Records (LBR) Updates May be Incorrect after a Task Switch Problem: A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value to the LBR_TO value. Implication: The LBR_FROM will have the incorrect address of the Branch Instruction. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. AI53.
Errata AI55. Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable Behavior Problem: Memory type aliasing occurs when a single physical page is mapped to two or more different linear addresses, each with different memory type. Memory type aliasing with the memory types WB and WT may cause the processor to perform incorrect operations leading to unpredictable behavior. Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable behavior.
Errata AI58. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early Problem: In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and count greater than or equal to 248 may terminate early. Early termination may result in one of the following.
Errata Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to execute a MOV on debug registers in V86 mode, a debug exception will be generated instead of the expected general-protection fault. Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The GD bit is generally set and used by debuggers. The debug exception handler should check that the exception did not occur in V86 mode before continuing.
Errata Implication: This scenario may only occur on a multiprocessor platform running an operating system that performs “lazy” TLB shootdowns. The memory image of the EFLAGS register on the page fault handler’s stack prematurely contains the final arithmetic flag values although the instruction has not yet completed.
Errata AI65. A Thermal Interrupt is Not Generated when the Current Temperature is Invalid Problem: When the DTS (Digital Thermal Sensor) crosses one of its programmed thresholds it generates an interrupt and logs the event (IA32_THERM_STATUS MSR (019Ch) bits [9,7]). Due to this erratum, if the DTS reaches an invalid temperature (as indicated IA32_THERM_STATUS MSR bit[31]) it does not generate an interrupt even if one of the programmed thresholds is crossed and the corresponding log bits become set.
Errata AI68.
Errata AI71. PMI May Be Delayed to Next PEBS Event Problem: After a PEBS (Precise Event-Based Sampling) event, the PEBS index is compared with the PEBS threshold, and the index is incremented with every event. If PEBS index is equal to the PEBS threshold, a PMI (Performance Monitoring Interrupt) should be issued. Due to this erratum, the PMI may be delayed by one PEBS event. Implication: Debug Store Interrupt Service Routines may observe delay of PMI occurrence by one PEBS event.
Errata Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a triple fault will occur due to the corrupted stack pointer, resulting in a processor shutdown. If the MCE is called with a stack switch, e.g. when the CPL (Current Privilege Level) was changed or when going through an interrupt task gate, then the corrupted ESP will be saved on the stack or in the TSS (Task State Segment), and will not be used.
Errata instruction address by the LBR (Last Branch Record) branch-from instruction address. Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI78. Last Branch Records (LBR) Updates May be Incorrect After a Task Switch Problem: A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value to the LBR_TO value.
Errata AI81. Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads Problem: When data of Store to WT memory is used by two subsequent loads of one thread and another thread performs cacheable write to the same address the first load may get the data from external memory or L2 written by another core, while the second load will get the data straight from the WT Store. Implication: Software that uses WB to WT memory aliasing may violate proper store ordering.
Errata inaccurately also count certain other types of instructions resulting in higher than expected values. Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count higher than expected. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI85. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: The ENTER instruction is used to create a procedure stack frame.
Errata Implication: When this erratum occurs, the processor may live lock causing a system hang. Workaround: Do not perform unaligned accesses on paging structure entries. Status: For the steppings affected, see the Summary Tables of Changes. AI88. Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior Problem: When Intel® Virtualization Technology is enabled, microcode updates are allowed only during VMX root operations.
Errata Implication: When this erratum occurs, a non-accessed page which is present in memory and follows a page that contains the code segment limit may be tagged as accessed. Workaround: Erratum can be avoided by placing a guard page (non-present or nonexecutable page) as the last page of the segment or after the page that includes the code segment limit. Status: For the steppings affected, see the Summary Tables of Changes. AI91.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI94. Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some Decoded Instructions Problem: MACRO_INSTS.DECODED performance monitoring counter (Event 0AAH, Umask 01H) counts the number of macro instructions decoded, but not necessarily retired.
Errata undercount depends on actual occurrences of PMULUDQ instructions, while the counter is active. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI97. Storage of PEBS Record Delayed Following Execution of MOV SS or STI Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based Sampling), overflow of the counter results in storage of a PEBS record in the PEBS buffer.
Errata • One of the following simultaneous exception conditions is present following the code transition o Code #DB and code #PF o Code Segment Limit Violation #GP and code #PF Implication: Software may observe either incorrect processing of code #PF before code Segment Limit Violation #GP or processing of code #PF in lieu of code #DB. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI100. Performance Monitoring Event CPU_CLK_UNHALTED.
Errata corresponds to 64K bytes for 16 bit address size and 4G bytes for 32 bit address size. Implication: (E)CX may contain an incorrect count which may cause some of the STOS operations to re-execute. Intel has not observed this erratum with any commercially available software. Workaround: Do not use values in (E)CX that when multiplied by the data size give values larger than the address space size (64K for 16-bit address size and 4G for 32-bit address size).
Errata range may prevent the actual triggering store to be propagated to the monitoring hardware. Implication: A logical processor executing an MWAIT instruction may not immediately continue program execution if a REP STOS/MOVS targets the monitored address range. Workaround: Software can avoid this erratum by not using REP STOS/MOVS store operations within the monitored address range. Status: For the steppings affected, see the Summary Tables of Changes. AI105.
Errata the occurrence of a hardware PMI request. Due to this erratum, the LBR freeze may occur too soon (i.e. before the hardware PMI request). Implication: Following a PMI occurrence, the PMI handler may observe old/out-of-date LBR information that does not describe the last few branches before the PEBS sample that triggered the PMI. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI108.
Errata AI110. VTPR Write Access During Event Delivery May Cause an APIC-Access VM Exit Problem: VTPR write accesses should not cause APIC-access VM exits but instead should cause data to be written to the virtual-APIC page. Due to this erratum, a VTPR write access during event delivery may cause an APICaccess VM exit with no data being written to the virtual-APIC page. Implication: VTPR accesses are accesses to offset 80H on the APIC-access page.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AI113.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AI116. Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception Problem: Software that implements memory aliasing by having more than one linear addresses mapped to the same physical page with different cache types may cause the system to hang or to report a machine check exception (MCE).
Errata AI118.
Errata AI120. VM Exit due to Virtual APIC-Access May Clear RF Problem: RF (Resume Flag), bit 16 of the EFLAGS/RFLAGS register, is used to restart instruction execution without getting an instruction breakpoint on the instruction following a debug breakpoint exception.
Errata erratum, IA32_MC1_STATUS MSR bit[60] instead reports the current value of the IA32_MC1_CTL MSR enable bit. Implication: IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the enable bit in the IA32_MC1_CTL MSR at the time of the last update. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI124.
Errata Contributory Exceptions and Page Faults will cause a triple fault shutdown, whereas a benign exception may not. Implication: If a benign exception occurs while attempting to call the double-fault handler, the processor may hang or may handle the benign exception. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI127.
Errata exit. If this guideline is followed, that value will be 1 only if the “host address-space size” VM-exit control is 1 in the executive VMCS. Status: For the steppings affected, see the Summary Tables of Changes. AI129. A 64-bit Register IP-relative Instruction May Return Unexpected Results Problem: Under an unlikely and complex sequence of conditions in 64-bit mode, a register IP-relative instruction result may be incorrect.
Specification Changes Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Datasheet • Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes 1,2A, 2B, 3A, and 3B All Specification Changes will be incorporated into a future version of the appropriate Intel® Core™2 Extreme and Intel® Core™2 Duo desktop processor documentation.
Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Datasheet • Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes 1, 2A, 2B, 3A, and 3B All Specification Clarifications will be incorporated into a future version of the appropriate Intel® Core™2 Extreme and Intel® Core™2 Duo desktop process
Documentation Changes Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Datasheet All Documentation Changes will be incorporated into a future version of the appropriate Intel® Core™2 Extreme and Intel® Core™2 Duo desktop processor documentation.
