ASUS NUC 13 Rugged Board / Kit Technical Product Specification Regulatory Models: NUC13BRK (Slim Kit) NUC13BRF (Tall Kit) NUC13BRB (Board) Mar 2024 Revision 5.0 ASUS NUC Boards NUC13BR may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata, if any, are documented in ASUS NUC Board NUC13BR Specification Update.
Revision History Table 1. Revision History Revision Revision History Date 1.0 Draft release of the ASUS NUC 13 Rugged Board/Kit Technical Product Specification May 2023 2.0 Rebranding Logo and Labels update Oct. 2023 3.0 Summary feature update Nov. 2023 4.0 Board Layout Update & rebranding updates Dec. 2023 5.0 Product Identification Info and CPU operating temp update Mar.
LIMITATION OF LIABILITY Circumstances may arise where because of a default on ASUS’ part or other liability, you are entitled to recover damages from ASUS.
Preface This Technical Product Specification (TPS) specifies the board layout, components, connectors, power and environmental requirements, and the BIOS for ASUS NUC Rugged NUC13BR Board/Kits. Some features are only available on certain SKUs. Intended Audience The TPS is intended to provide detailed, technical information about ASUS NUC Rugged NUC13BR Board and Kit, and its components to the vendors, system integrators, and other engineers and technicians who need this level of information.
Other Common Notation Table 3.
Board Identification Information Basic ASUS NUC Board NUC13BRK Identification Information Table 4. Board/BIOS Identification AA Revision BIOS Revision Notes BRADL0036.00XX 1 BRADL0036.00XX 1 Notes: 1. viii The AA number is found on a small label on the component side of the board.
Production Identification Information Table 5.
Specification Changes or Clarifications The table below indicates the Specification Changes or Specification Clarifications that apply to the ASUS NUC Rugged NUC13BR Board and Kit. Specification Changes or Clarifications Table 6. Specification Changes Date Type of Change Description of Changes or Clarifications Errata Current characterized errata, if any, are documented in a separate Specification Update. See for the latest documentation.
Table of Contents 1 Product Description .............................................................................................. 15 1.1 Overview ................................................................................................................................... 15 1.1.1 Summary of Standard Kit and Board SKUs .......................................................... 15 1.1.2 Feature Summary Kits ...........................................................................................
4.5 4.6 xii BIOS Security Features........................................................................................................... 46 BIOS Error Messages ..............................................................................................................
Contents List of Figures Figure 1. Tall Chassis Layout ................................................................................................................... 18 Figure 2. Slim Chassis Layout ................................................................................................................. 19 Figure 3. Major Board Components (Top) ........................................................................................... 20 Figure 4. Block Diagram ................................
Table 24. Environmental Specifications ................................................................................................ 41 Table 25. Acceptable Drives/Media Type for BIOS Recovery ........................................................... 43 Table 26. Power Button Menu Options ................................................................................................ 44 Table 27. Master Key and User Hard Disk Drive Password Functions ..............................................
1 Product Description 1.1 Overview 1.1.1 Summary of Standard Kit and Board SKUs Product Codes and MM#s for the SKUs below can be found at https://www.asus.com/support/ Table 7.
1.1.2 Feature Summary Kits Table 8 Summarizes the major features of the ASUS NUC Rugged NUC13BR Boards and Kits Table 8. Feature Summary Board Dimensions 146mm x 101.7mm Max Chassis Dimensions Slim chassis: 174mm x 108mm x 25.9mm (+3.4mm rubber feet) Processor ASUS NUC 13 Rugged Boards and Kits have a soldered-down Alder-Lake-N processor from the list below. Tall chassis: 174mm x 108mm x 35.8mm (+3.
Technical Reference USB Ports and Headers 2 x USB 3.2 Gen2 port (rear panel) 2 x USB 2.0 port (rear panel) 2 x USB 2.0 Headers (internal) More information about the location of the USB ports and headers can be found in Section 3.6.3 later in this document. More information about the pinout of the USB ports and headers can be found in Section 3.4 later in this document Power Power Adapter • 65W adapter ADP 20V, 3.25A 3P DT VI • 90W adapter ADP 20V, 4.
2 Product Layout 2.1 Board Layout 2.1.1 Board Layout (BACK/FRONT PLANES) Figure 1 and 2 shows the location of the major components on the bottom of ASUS NUC Board NUC13BRK/ NUC13BRF/NUC13BRB Figure 1. Tall Chassis Layout Table 10. Components Shown in Figure 1. Tall Chassis Layout 18 Item from Figure 1 Description A 12-20 V DC Input Jack B HDMI 2.1 TMDS Port 1 with Built-In CEC Support C LAN Connectors D Back Panel 2 USB 3.2 Gen 2 E Back Panel 2 USB 2.
Technical Reference Figure 2. Slim Chassis Layout Table 11. Components Shown in Figure 2. Slim Chassis Layout Item from Figure 2 Description A 12-20 V DC Input Jack B HDMI 2.1 TMDS Port 1 with Built-In CEC Support C LAN Connector D Back Panel 2 USB 3.2 Gen 2 E Back Panel 2 USB 2.
2.1.2 Board Layout (Top) Error! Reference source not found.3 shows the location of the major components on the bottom-s ide of ASUS NUC Board NUC13BRK/ NUC13BRF/NUC13BRB Figure 3. Major Board Components (Top) Table 12. Components Shown in Figure 3. 20 Item from Description A Power Connector (12VDC to 20VDC +/- 5% with DC voltage protection) B MIPI Header 3 C USB Internal Header D M.
Technical Reference 2.1.3 E Internal Power Header F M.2 Key-M 2280 G SIM Card Socket H M.2 Key E 2230 I TGPIO Header J CMOS Battery Holder K DDR5 SODIMM Socket L HDMI Connectors M USB Type-A Connectors N RJ-45 LAN Ports O Front Panel Header P MIPI CSI Block Diagram Figure 4.
2.1.4 Chassis Expandability Options The chassis side panel of the ASUS NUC Rugged NUC13BR Boards and Kits Canyon supports an opening for 3rd party / customer expandability option. This expandability bay usage is not limited to, Camera connections, etc. The chassis provides a plastic face plate for covering the side panel opening when no expansion is installed. The Face plate matches the chassis color and texture. Some 3rd party expandability dongles are available from https://gorite.
Technical Reference • • Support Headless, 2nd Virtual Display and Persistent Display Mode Operation Accelerate Video Processing for Visual Experiences, Video Walls, and Graphics- Intensive Apps Integrated graphics create new opportunities for visually rich experiences and graphics-enhanced controls while reducing dependency on discrete graphics hardware.
3.1.1 Display Emulation Display emulation is supported using the HDMI ports so that the system may be remotely accessed in a headless configuration or be capable of tolerating display connectivity interruptions without the operating system redetecting and rearranging the overall display layout.
Technical Reference 3.2 NVMe/SATA Interfaces The PCH provides three Internal M.2 interface slots with a theoretical maximum transfer rate and provides the following interfaces: • M.2 #1 22x80 supports up to 3.5 Gb/s with one PCIe M.2 slot for SSD and AI accelerator use. The M.2 SSD slot is required to support NVMe drives. • M.2 #2 22x30 support up to 2.4 Gb/s with one M.2 slot for wireless card expandability. L10 SKU is equipped with a wireless card pre-installed.
3.4 LAN Subsystem 3.4.1 RJ-45 LAN Connector with Integrated LEDs Two LEDs are built into the RJ-45 LAN connector (shown in Figure 6. LAN Connectors Location 6). Item Description A LAN Connector 2 B LAN Connector 3 Figure 6. LAN Connectors Location Table 13 describes the LED states when the board is powered up and the LAN subsystem is operating. Table 13.
Technical Reference 3.5 3.5.1 MIPI CSI Interfaces The pin out of the multiple MIPI headers Figure 7.
3.5.2 Enable the MIPI CSI Interfaces in BIOS Menu To enable the MIPI CSI Interfaces, users need to modify BIOS configurations in BIOS setup menu following below instructions. 28 1. Enable IPU Device and 1181 Dash Camera in BIOS menu -> Advanced -> MIPI Camera. 2. Configure camera HID and GPIO settings in BIOS menu -> Advanced -> MIPI Camera -> Slot1 or Slot2. Default camera settings are for INTC10C0 and IMX415 cameras. 3.
Technical Reference 3.6 Hardware Management Subsystem 3.6.1 Fanless Thermal Solution The chassis is required to be fanless, thermally and environmentally robust in lower air-quality environments (i.e., dust, 40°C ambience, etc.). Bravo will not be used outdoors. Fan-less thermal solution meets these requirements: • The chassis and thermal solution need to be designed so all system configurations do not exceed 70C skin temp at 35C ambient. We can exceed 70C skin temperature at higher ambience.
3.6.3 Signal Tables for the Connectors and Headers Figure 8. USB Header PIN Layout Table 15. Internal USB 2.0 Headers (1.25 mm pitch) 1 Pin Signal Name 1 5 V1 2 D- 3 D+ 4 GND The two USB 2.0 headers on the board can deliver 1A per port. Connector is Molex part number 53398-0471, 1.25mm Pitch PicoBlade* Header, Surface Mount, Vertical, Lead-Free, 4 Circuits. Table 16. M.
Technical Reference 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 8 iRST PCIe Remapping support Connector Key Connector Key Connector Key N/C N/C PEWAKE# (I/O)(0/3.3V) or N/C CLKREQ# (I/O)(0/3.3V) or N/C PERST# (O)(0/3.3V) or N/C N/C N/C N/C N/C N/C DEVSLP (O) N/C N/C N/C N/C N/C N/C N/C N/C N/C 3.3V 3.3V 3.3V 3.3V DAS/DSS# (I/O)/LED1# (I)(0/3.3V) PLN N/C 3.3V 3.
52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 PERST0# (O)(0/3.3V) SUSCLK(32kHz) (O)(0/3.3V) COEX1 (I/O)(0/1.8V) COEX2(I/O)(0/1.8V) COEX3(I/O)(0/1.8V) CLink_CLK (I/O); NC for SR project CLink_DATA (I/O); NC for SR project C-Link RESET* (I) (0/3.3V); NC for SR project UART RTS/BRI_DT (I) (0/1.8V) UART CTS (O) (0/1.8V) UART TXD/RGI_DT (I) (0/1.8V) Connector Key Connector Key Connector Key Connector Key UART RXD/BRI_RSP (O) (0/1.8V) UART WAKE# (O) (0/3.
Technical Reference 40 GPIO_0 (I/O)(0/1.8V*) 38 DEVSLP (O) 36 UIM-PWR (I) 34 UIM-DATA (I/O) 32 UIM-CLK (I) 30 UIM-RESET (I) 28 GPIO_8 (I/O) (0/1.8V) 26 GPIO_10 (I/O) (0/1.8V) 24 GPIO_7 (I/O) (0/1.8V) 22 GPIO_6 (I/O)(0/1.8V) 20 GPIO_5 (I/O)(0/1.8V) Connector Key Connector Key Connector Key Connector Key 10 GPIO_9/DAS/DSS# (I/O)/LED1#(I)(0/3.3V) 8 W_DISABLE1# (O)(0/3.3V) 6 4 2 3.6.3.1 PERn0/SATA-B+ 41 GND 39 PETp1/USB3.0-Tx+/SSIC-TxP 37 PETn1/USB3.
• The FULL_CARD_POWER_OFF# and the RESET# pins are unique and intended to be used when the WWAN solution is plugged into platforms that provide a direct connection to VBATT (and not a regulated 3.3 V) such as Tablet platforms. They are not used in NB and Very thin notebooks type platforms that provide a regulated 3.3 V power rail. But the FULL_CARD_POWER_OFF# signals should be tied to the 3.3V power rail on the NB/very thin platform. • The SSD can make use of the PCIe two Lanes or overlaid SATA host I/F.
Technical Reference Figure 9. Connection Diagram for Front Panel Header (2.0 mm Pitch) 3.6.3.2.1 Hard Drive Activity LED Header Pins 1 and 3 can be connected to an LED to provide a visual indicator that data is being read from or written to a hard drive. Proper LED function requires a SATA hard drive or optical drive connected to an onboard SATA connector. 3.6.3.2.2 Reset Switch Header Pins 5 and 7 can be connected to a momentary single pole, single throw (SPST) type switch that is normally open.
NOTE The LED behavior shown in is default – other patterns may be set via BIOS setup. 3.6.3.2.4 Power Switch Header Pins 6 and 8 can be connected to a front panel momentary-contact power switch. The switch must pull the SW_ON# pin to ground for at least 50 ms to signal the power supply to switch on or off (the time requirement is due to internal debounce circuitry on the board). At least two seconds must pass before the power supply recognizes another on/off signal. 3.6.3.
Technical Reference Lockdown 2-3 Configuration None The BIOS uses current configuration information and passwords for booting, except: • All POST Hotkeys are suppressed (prompts are not displayed and keys are not accepted. For example, F2 for Setup, F10 for the Boot Menu). • Power Button Menu is not available (see Section 3.6.3.2 Power Button Menu). BIOS updates are not available except for automatic Recovery due to flash corruption. BIOS Recovery Update process if a matching *.bio file is found.
Table 23. Internal Power Supply Connector Pins Pins 1,2 3,4 Signal Name +12-20V GND Figure 11. Connection Diagram for the Internal Power Supply Connector 3.7 3.7.1 Mechanical Considerations Chassis Images Figure 12.
Technical Reference Figure 13. Tall Chassis Image Back Figure 14. Short Chassis Image Front Figure 15. Short Chassis Image Back 3.8 Thermal Considerations CAUTION Failure to ensure appropriate airflow may result in reduced performance of both the processor and/or voltage regulator or, in some instances, damage to the board. All responsibility for determining the adequacy of any thermal or system design remains solely with the system integrator.
CAUTION Ensure that proper airflow is maintained in the processor voltage regulator circuit. Failure to do so may result in a shorter than expected product lifetime. 3.9 Reliability The demonstrated Mean Time Between Failures (MTBF) is done through 24/7 testing. Full ASUS NUC systems in chassis with memory, SSD or HDD, and a fan are run at 100% on time for 90 days continuously while running system wide stress inducing software in a 40 °C ambient air temperature chamber.
Technical Reference 3.10 Environmental Table 24 lists the environmental specifications for the board. CAUTION If the external ambient temperature exceeds 50 oC, further thermal testing is required to ensure components do not exceed their maximum operating temperature. Table 24. Environmental Specifications Parameter Specification Temperature Sustained Storage Limits (i.e., warehouse) -20 C to +40 C Short Duration Limits (i.e.
Vibration (Board) Unpackaged Random profile 5 Hz @ 0.01 g^2/Hz to 20 Hz @ 0.02 g^2/Hz (slope up) 20 Hz to 500 Hz @ 0.02 g^2/Hz (flat) Input acceleration is 3.13g RMS Vibration (System) Unpackaged Random profile 5 Hz @ 0.001 g^2/Hz to 20 Hz @ 0.01 g^2/Hz (slope up) 20 Hz to 500 Hz @ 0.01 g^2/Hz (flat) Input acceleration is 2.20g RMS Packaged Random Profile: 0.001 g^2/Hz to 20 Hz @ 0.01 g^2/Hz (slope up) 20 Hz to 500 Hz @ 0.01 g@/Hz (flat) Input acceleration is 2.
Technical Reference 4.2.1 BIOS Recovery It is unlikely that anything will interrupt a BIOS update; however, if an interruption occurs the BIOS could be unstable. Error! Reference source not found. lists the drives and media types that can be u sed for BIOS recovery. The BIOS recovery media does not need to be made bootable. More information about BIOS recovery methods and instructions can be found at BIOS Update and Recovery Instructions. Table 25.
4.3 Boot Options In the BIOS Setup program, the user can choose to boot from a hard drive, removeable driver, or the network. The default setting is for the hard drive to be the first boot device, the removeable drive second, and the network third. NOTE The network can be selected as a boot device. This selection allows booting from the onboard LAN or a network add-in card with a remote boot ROM installed. Pressing the key during POST automatically forces booting from the LAN.
Technical Reference Recovery proceeds if not cancelled via the ESC key within 20 seconds. The BIOS displays the recovery progress. If a BIOS .CAP file was not detected (or the BIOS Recovery was cancelled) then the BIOS resets the system and continues normally to POST. [F5] 4.4 Restore BIOS Settings The BIOS restores the current setup settings and the current defaults to the build time defaults in the case of a boot issue caused by setup variable changes.
4.5 BIOS Security Features BIOS includes security features that restrict access to the BIOS Setup program and who can boot the computer. A Supervisor and User password can be set for the BIOS Setup program and for botting the computer, with the following restrictions: • • • • • • • • The Supervisor password gives unrestricted access to view and change all the Setup options in the BIOS Setup program. This is Supervisor Mode.
Technical Reference 4.6 BIOS Error Messages Table 29 lists the error messages and provides a brief description of each. Table 29. BIOS Error Messages Error Message Explanation CMOS Battery Failure The battery may be losing power. Replace the battery soon. CMOS Checksum Error The CMOS checksum is incorrect. CMOS memory may have been corrupted. Run Setup to reset values. Memory Size Decreased Memory size has decreased since the last boot. If no memory was removed, then the memory may be bad.
