Datasheet

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Matched Monolithic

Dual Transistor

Data Sheet

MAT01

FEATURES

Low V

match): 40 µV typical, 100 µV maximum

Low TCV

: 0.5 µV/°C maximum

High h

: 500 minimum

Excellent h

linearity from 10 nA to 10 mA

Low noise voltage: 0.23 µV p-p from 0.1 Hz to 10 Hz

High breakdown: 45 V min

APPLICATIONS

Weigh scales

Low noise, op amp, front end

Current mirror and current sink/source

Low noise instrumentation amplifiers

Voltage controlled attenuators

Log amplifiers

PIN CONNECTION DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The MAT01 is a monolithic dual NPN transistor. An exclusive

silicon nitride triple passivation process provides excellent

stability of critical parameters over both temperature and time.

Matching characteristics include offset voltage of 40 µV,

temperature drift of 0.15 µV/°C, and h

matching of 0.7%.

High h

is provided over a six decade range of collector

current, including an exceptional h

of 590 at a collector

current of only 10 nA. The high gain at low collector current

makes the MAT01 ideal for use in low power, low level input

stages.

MAT01

TOP VIEW

(Not to Scale)

NOTES

1. SUBSTRATE IS CONNECTED TO CASE.

00282-001

2 5

Rev. D Document Feedback

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Summary of content (12 pages)

PAGE 1
Matched Monolithic Dual Transistor MAT01 Data Sheet PIN CONNECTION DIAGRAM Low VOS (VBE match): 40 µV typical, 100 µV maximum Low TCVOS: 0.5 µV/°C maximum High hFE: 500 minimum Excellent hFE linearity from 10 nA to 10 mA Low noise voltage: 0.23 µV p-p from 0.
PAGE 2
MAT01 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 Pin Connection Diagram ...........................................................
PAGE 3
Data Sheet MAT01 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCB = 15 V, IC = 10 µA, TA = 25°C, unless otherwise noted. Table 1.
PAGE 4
MAT01 Data Sheet VCB = 15 V, IC = 10 µA, −55°C ≤ TA ≤ +125°C, unless otherwise noted. Table 2.
PAGE 5
Data Sheet MAT01 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3.
PAGE 6
MAT01 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS OFFSET VOLTAGE (µV) OV < VCB < 30V 150 MAT01G 100 MAT01A 0 –75 00282-002 50 0 –25 50 25 75 100 125 10 8 6 DEVICE B 2 0 DEVICE C –2 DEVICE D –4 –6 –8 –10 150 DEVICE A 4 00282-005 ABSOLUTE CHANGE IN OFFSET VOLTAGE (µV) 200 0 1 3 2 5 4 TEMPERATURE (°C) 7 6 9 8 10 11 12 13 TIME (Months) Figure 2. Offset Voltage vs. Temperature Figure 5. Offset Voltage vs.
PAGE 7
Data Sheet MAT01 1000 10µA 1µA Δ < 0.1mV 100nA 10nA 1nA Δ < 0.3mV 100pA 10pA 0 100 Δ ≈ DEVIATION FROM STRAIGHT LINE 200 300 400 500 600 700 00282-008 COLLECTOR CURRENT (IC) Δ < 0.3mV 100µA 800 BASE TO EMITTER VOLTAGE (mV) Figure 8. Collector Current vs. Base to Emitter Voltage 10 TA = +125°C TA = +25°C TA = –55°C 0.1 00282-009 SATURATION VOLTAGE (V) MAT01 IC = 10 × IB 0.01 0.01 0.
PAGE 8
MAT01 Data Sheet TEST CIRCUITS +16.5V +16.5V 50kΩ* 20kΩ 50kΩ* 50kΩ* VOUT OP1177 100kΩ 1% S1B 1MΩ 100pF UNITS CLOSED CLOSED IOS 1MΩ* MAT01 VOS S1B S1A TEST –15V S1A OPEN OPEN VOUT1 1V PER mV VOUT2 – VOUT1 1V PER nA 100kΩ 1% 100pF 00282-011 20µA V– *MATCHED TO 0.01% Figure 11. Matching Measurement Circuit +15V 50kΩ* 50kΩ* +15V 50kΩ* S3 A S2 S1A S1B 4MΩ –15V 3.3kΩ 2.
PAGE 9
Data Sheet MAT01 APPLICATIONS INFORMATION Application of reverse bias voltages to the emitter to base junctions in excess of ratings (5 V) may result in degradation of hFE and hFE matching characteristics. Check circuit designs to ensure that reverse bias voltages above 5 V cannot be applied during transient conditions, such as at circuit turn-on and turn-off.
PAGE 10
MAT01 Data Sheet TYPICAL APPLICATIONS 1mA VREF Q1 Q2 R1 1.5kΩ NOTES 1. R1 MAY BE ADJUSTED TO MINIMIZE TCVREF . INCREASING R1 CAUSES A POSITIVE CHANGE IN TCVREF. 2. hFE OF Q1 IS REDUCED BY OPERATION OF BREAKDOWN MODE. 00282-013 VREF ≈ 7.0V TCVREF ≈ 100ppm/°C RO ≈ 40Ω Figure 13. Precision Reference UP TO 100 FEET CABLE +15V –15V DIFFERENTIAL AMPLIFIER AND CURRENT SOURCES °C K EO –55°C = 218K = 2.18V +25°C = 298K = 2.98V +125°C = 398K = 3.
PAGE 11
Data Sheet MAT01 OUTLINE DIMENSIONS 0.185 (4.70) 0.165 (4.19) REFERENCE PLANE 0.750 (19.05) 0.500 (12.70) 0.250 (6.35) MIN 0.100 (2.54) BSC 0.050 (1.27) MAX 0.160 (4.06) 0.110 (2.79) 5 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 4 0.200 (5.08) BSC 3 6 0.045 (1.14) 0.027 (0.69) 2 0.019 (0.48) 0.016 (0.41) 0.040 (1.02) MAX 0.045 (1.14) 0.010 (0.25) 1 0.100 (2.54) BSC 0.034 (0.86) 0.027 (0.69) 0.021 (0.53) 0.016 (0.