ADSP-BF538F EZ-KIT Lite® Evaluation System Manual Revision 1.2, April 2008 Part Number 82-000945-01 Analog Devices, Inc. One Technology Way Norwood, Mass.
Copyright Information ©2008 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Limited Warranty The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice.
Regulatory Compliance The ADSP-BF538F EZ-KIT Lite is designed to be used solely in a laboratory environment. The board is not intended for use as a consumer end product or as a portion of a consumer end product. The board is an open system design which does not include a shielded enclosure and therefore may cause interference to other electrical devices in close proximity. This board should not be used in or near any medical equipment or RF devices.
CONTENTS PREFACE Purpose of This Manual ................................................................ xiii Intended Audience ........................................................................ xiii Manual Contents ........................................................................... xiv What’s New in This Manual ........................................................... xiv Technical or Customer Support ....................................................... xv Supported Processors .........
CONTENTS Evaluation License Restrictions ..................................................... 1-7 Memory Map ............................................................................... 1-7 SDRAM Interface ......................................................................... 1-8 Flash Memory ............................................................................ 1-10 CAN Interface ............................................................................ 1-11 ELVIS Interface ................
CONTENTS Flash Enable Switch (SW6) .................................................... 2-11 FCE Enable Switch (SW14) ................................................... 2-12 Audio Enable Switch (SW7) .................................................. 2-12 Boot Mode Select Switch (SW3) ............................................ 2-13 PPI Direction Control (JP1) .................................................. 2-13 UART Loop Jumper (JP9) .....................................................
CONTENTS SPORT0 and SPORT1 Connectors (P6 and P7) .................... 2-23 PPI Connector (P8) .............................................................. 2-23 SPI Connector (P9) ............................................................... 2-24 2-Wire Interface Connector (P10) ......................................... 2-24 TIMERS Connector (P11) .................................................... 2-24 UART1 Connector (P12) ......................................................
PREFACE Thank you for purchasing the ADSP-BF538F EZ-KIT Lite®, Analog Devices, Inc. evaluation system for Blackfin® processors. Blackfin processors embody a new type of embedded processor designed specifically to meet the computational demands and power constraints of today’s embedded audio, video, and communications applications. They deliver breakthrough signal-processing performance and power efficiency within a reduced instruction set computing (RISC) programming model.
The evaluation board is designed to be used in conjunction with the VisualDSP++® development environment to test the capabilities of the ADSP-BF538F Blackfin processors.
Preface The board features: • Analog Devices ADSP-BF538F processor D D D D Core performance up to 600 MHz External bus performance to 133 MHz 182-pin mini-BGA package 25 MHz crystal • Synchronous dynamic random access memory (SDRAM) D MT48LC32M8 – 64 MB (8M x 8-bits x 4 banks) x 2 chips • Flash memory D 4MB (2M x 16-bits) • Analog audio interface D D D D AD1871 96 kHz analog-to-digital codec (ADC) AD1854 96 kHz digital-to-audio codec (DAC) 1 input stereo jack 1 output stereo jack • Controller Area
• Universal asynchronous receiver/transmitter (UART) D D ADM3202 RS-232 line driver/receiver DB9 female connector • LEDs D 10 LEDs: 1 power (green), 1 board reset (red), 1 USB (red), 5 general-purpose (amber), and 1 USB monitor (amber) • Push buttons D 5 push buttons: 1 reset, 4 programmable flags with debounce logic • Expansion interface D All processor signals • Other features D JTAG ICE 14-pin header The EZ-KIT Lite board has flash memory with a total of 4 MB.
Preface Additionally, the EZ-KIT Lite board provides access to all of the processor’s peripheral ports. Access is provided in the form of a three-connector expansion interface. For more information, see “Expansion Interface” on page 2-8. Purpose of This Manual The ADSP-BF538F EZ-KIT Lite Evaluation System Manual provides instructions for installing the product hardware (board).
Manual Contents Manual Contents The manual consists of: • Chapter 1, “Using ADSP-BF538F EZ-KIT Lite” on page 1-1. Describes EZ-KIT Lite functionality from a programmer’s perspective and provides an easy-to-access memory map. • Chapter 2, “ADSP-BF538F EZ-KIT Lite Hardware Reference” on page 2-1. Provides information on the EZ-KIT Lite hardware components. • Appendix A, “ADSP-BF538F EZ-KIT Lite Bill Of Materials” on page A-1. Provides a list of components used to manufacture the EZ-KIT Lite board.
Preface Technical or Customer Support You can reach Analog Devices, Inc. Customer Support in the following ways: • Visit the Embedded Processing and DSP products Web site at http://www.analog.com/processors/technicalSupport • E-mail tools questions to processor.tools.support@analog.com • E-mail processor questions to processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.
Product Information Product Information You can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from printed publications (manuals). Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors. MyAnalog.com MyAnalog.
Preface You may also obtain additional information about Analog Devices and its products in any of the following ways. • E-mail questions or requests for information to processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.
Product Information Table 2. Related VisualDSP++ Publications Title Description ADSP-BF538F EZ-KIT Lite Evaluation System Manual Description of the hardware capabilities of the evaluation system; description of how to access these capabilities in the VisualDSP++ environment. VisualDSP++ User’s Guide Description of the VisualDSP++ features and usage. VisualDSP++ Assembler and Preprocessor Manuals Description of the assembler function and commands.
Preface File Description .chm Help system files and manuals in Help format .htm or .html Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the .html files requires a browser, such as Internet Explorer 6.0 (or higher). .pdf VisualDSP++ and processor manuals in Portable Documentation Format (PDF). Viewing and printing the .pdf files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).
Product Information Accessing Documentation From Web Download manuals at the following Web site: http://www.analog.com/processors/technicalSupport/technicalLibrary/. Select a processor family and book title. Download archive (.zip) files, one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files. Printed Manuals For general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
Preface Notation Conventions Text conventions used in this manual are identified and described as follows. Additional conventions, which apply only to specific chapters, may appear throughout this document. Example Description Close command (File menu) Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu).
Notation Conventions xxii ADSP-BF538F EZ-KIT Lite Evaluation System Manual
1 USING ADSP-BF538F EZ-KIT LITE This chapter provides specific information to assist you with development of programs for the ADSP-BF538F EZ-KIT Lite evaluation system. The information appears in the following sections. • “Package Contents” on page 1-3 Lists the items contained in the ADSP-BF538F EZ-KIT Lite package. • “Default Configuration” on page 1-3 Shows the default configuration of the ADSP-BF538F EZ-KIT Lite.
• “CAN Interface” on page 1-11 Describes the on-board Controller Area Network (CAN) interface. • “ELVIS Interface” on page 1-12 Describes the on-board National Instruments Educational Laboratory Virtual Instrumentation Suite (NI ELVIS) interface. • “Audio Interface” on page 1-12 Describes the on-board audio circuit. • “LEDs and Push Buttons” on page 1-13 Describes the board’s general-purpose IO pins and buttons.
Using ADSP-BF538F EZ-KIT Lite Package Contents Your ADSP-BF538F EZ-KIT Lite evaluation system package contains the following items. • ADSP-BF538F EZ-KIT Lite board • VisualDSP++ Installation Quick Reference Card • CD containing: D VisualDSP++ software D ADSP-BF538F EZ-KIT Lite debug software D USB driver files D Example programs D ADSP-BF538F EZ-KIT Lite Evaluation System Manual (this document) • Universal 7V DC power supply • 6-foot 3.5 mm male-to-male audio cable • 3.
Default Configuration The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package.
Using ADSP-BF538F EZ-KIT Lite Installation and Session Startup correct operation, install the software and hardware in the L For order presented in the VisualDSP++ Installation Quick Reference Card. 1. Verify that the yellow USB monitor LED (ZLED3, located near the USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++. 2.
Installation and Session Startup 5. The Select Connection Type page of the wizard appears on the screen. Select EZ-KIT Lite and click Next. 6. The Select Platform page of the wizard appears on the screen. In the Select your platform list, select ADSP-BF538F EZ-KIT Lite via Debug Agent. In Session name, highlight or specify the session name. The session name can be a string of any length; although, the box displays approximately 32 characters. The session name can include space characters.
Using ADSP-BF538F EZ-KIT Lite Evaluation License Restrictions The ADSP-BF538F EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires: • VisualDSP++ allows a connection to the ADSP-BF538F EZ-KIT Lite via the USB debug agent interface only. Connections to simulators and emulation products are no longer allowed.
SDRAM Interface Table 1-1. EZ-KIT Lite Evaluation Board Memory Map Start Address External Memory End Address Content 0x0000 0000 0x03FF FFFF SDRAM bank 0 (SDRAM). See “SDRAM Interface” on page 1-8. 0x2000 0000 0x200F FFFF ASYNC memory bank 0. See “Flash Memory” on page 1-10. 0x2010 0000 0x201F FFFF ASYNC memory bank 1. See “Flash Memory” on page 1-10. 0x2020 0000 0x202F FFFF ASYNC memory bank 2. See “Flash Memory” on page 1-10. 0x2030 0000 0x203F FFFF ASYNC memory bank 3.
Using ADSP-BF538F EZ-KIT Lite SDRAM registers are configured automatically through the debugger each time the processor is reset. The values in Table 1-2 are used whenever SDRAM bank 0 is accessed through the debugger (for example, when viewing memory windows or loading a program). The numbers were derived for maximum flexibility and work for a system clock frequency between 54 MHz and 133 MHz. Table 1-2.
Flash Memory Automatic configuration of SDRAM is not optimized for any SCLK frequency. Table 1-3 shows optimized configuration for the SDRAM registers using a 125 MHz and 133 MHz SCLK. Only the EBIU_SDRRC register needs to be modified in the user code to achieve maximum performance. Table 1-3.
Using ADSP-BF538F EZ-KIT Lite Example code is provided in the EZ-KIT Lite installation directory to demonstrate how to program flash memory. Table 1-4 shows a sample value for the asynchronous memory configuration register, EBIU_AMBCTL0. Table 1-4. Asynchronous Memory Control Register Setting Example Register Value Function EBIU_AMBCTL0 0x7BB07BB0 Timing control for banks 1 and 0 CAN Interface The Controller Area Network interface contains a Philips TJA1041 high-speed CAN transceiver.
ELVIS Interface ELVIS Interface This EZ-KIT Lite board contains the National Instruments ELVIS interface. The interface features the DC voltage and current measurement modules, oscilloscope and bode analyzer modules, function generator, arbitrary waveform generator, and digital IO. The ELVIS interface is a NI LabVIEW-based design and prototype environment for university science and engineering laboratories.
Using ADSP-BF538F EZ-KIT Lite The frame sync and bit clocks are generated from the ADC and feed to the processor because the ADC is operating in master mode. The audio interface samples data at a 48 kHz sample rate. The serial data interface operates in 2-wire interface (TWI) mode and connects to SPORT0 of the processor. The audio interface can be disconnected from the SPORT0 by turning positions 1 and 5 of the SW7 switch OFF.
Example Programs Example Programs Example programs are provided with the ADSP-BF538F EZ-KIT Lite to demonstrate various capabilities of the evaluation board. These programs are installed with the EZ-KIT Lite software and can be found in the \Blackfin\Examples\ADSP-BF538F EZ-KIT Lite VisualDSP++ directory. Please refer to the readme file provided with each example for more information.
2 ADSP-BF538F EZ-KIT LITE HARDWARE REFERENCE This chapter describes the hardware design of the ADSP-BF538F EZ-KIT Lite board. The following topics are covered. • “System Architecture” on page 2-2 Describes the ADSP-BF538F EZ-KIT Lite board configuration and explains how the board components interface with the processor. • “Jumper and Switch Settings” on page 2-9 Shows the locations and describes the configuration jumpers and switches.
System Architecture System Architecture This section describes the processor’s configuration on the EZ-KIT Lite board. RS-232 Female RS-232 Interface UARTs 64 MB SDRAM 4 MB Flash (32M x 16) (2M x 16 ) RTC EBUI ADSP-BF538F DSP SPORTs Expansion Connectors (3) SPIs PPI GPIO Timer Conn TWI JTAG Port Debug Agent CAN Transceiver CAN (2) RJ10 (2) TWI Conn USB Conn 32.768 KHz Oscillator Timers 25 MHz Oscillator JTAG Conn PBs (4) LEDs (6) ADC/ DAC +7.
ADSP-BF538F EZ-KIT Lite Hardware Reference The core voltage and the core clock rate can be set on the fly by the processor. The input clock is 25 MHz. A 32.768 kHz crystal supplies the real-time clock (RTC) inputs of the processor. The default boot mode for the processor is flash boot. See “Boot Mode Select Switch (SW3)” on page 2-13 for information about changing the default boot mode.
System Architecture SPORT0 Interface connects to the audio circuit, SPORT0 connector (P6), and expansion interface. The audio circuit uses the primary data transmit and receive pins to input and output data from the audio input and outputs. SPORT0 and SPORT2 of the processor connect to the SPORT connectors (P3 and P4) and expansion interface. SPORT1 The pinout of the SPORT interface and expansion interface connectors can be found in “ADSP-BF538F EZ-KIT Lite Schematic” on page B-1.
ADSP-BF538F EZ-KIT Lite Hardware Reference Table 2-1. Programmable Flag Connections (Cont’d) Processor Pin Other Processor Function EZ-KIT Lite Function PC5 LED (LED2) or ELVIS_PF1. See “LED and Push Button Locations” on page 2-17 and “Push Button Enable Switch (SW5)” on page 2-11 for information on how to disable the push button. PC6 LED (LED3) or ELVIS_PF2.
System Architecture Table 2-1.
ADSP-BF538F EZ-KIT Lite Hardware Reference Table 2-1. Programmable Flag Connections (Cont’d) Processor Pin Other Processor Function EZ-KIT Lite Function PF0 SPISS Push button (SW13). See “Programmable Flag Push Buttons (SW10–13)” on page 2-18. PF1 SPI0SEL1/TMRCLK Push button (SW12). See “Programmable Flag Push Buttons (SW10–13)” on page 2-18. PF2 SPI0SEL2 Push button (SW11). See “Programmable Flag Push Buttons (SW10–13)” on page 2-18. PF3 PPI_FS3/SPI0SEL3 Push button (SW10).
System Architecture UART Port The universal asynchronous receiver/transmitter (UART) port of the processor connects to the ADM3202 RS-232 line driver as well as to the expansion interface. The RS-232 line driver connects to the DB9 female connector, providing an interface to a PC and other serial devices. Expansion Interface The expansion interface consists of three 90-pin connectors. Table 2-2 shows the interfaces each connector provides.
ADSP-BF538F EZ-KIT Lite Hardware Reference JTAG Emulation Port The JTAG emulation port allows an emulator to access the processor’s internal and external memory through a 6-pin interface. The JTAG emulation port of the processor connects also to the USB debugging interface. When an emulator connects to the board at ZP4, the USB debugging interface is disabled. See “JTAG Connector (ZP4)” on page 2-23 for more information about the connector.
Jumper and Switch Settings CAN Enable Switch (SW2) The Controller Area Network (CAN) enable switch (SW2) disconnects CAN signals from the GPIO pins of the processor. When the SW2 switch is in the OFF position, the associated GPIO signals (see Table 2-3) can be used on the expansion interface. Table 2-3.
ADSP-BF538F EZ-KIT Lite Hardware Reference Push Button Enable Switch (SW5) The push button enable switch (SW5) disconnects the associated signal and the push button circuit drivers from the GPIO pins of the processor. When the SW5 switch is in the OFF position, the GPIO signal (see Table 2-5) can be used on the expansion interface. Table 2-5.
Jumper and Switch Settings FCE Enable Switch (SW14) The flash chip enable (FCE) switch (SW14) selects which ~AMS signals connect to the internal flash memory. Since the internal memory is 1 MB, only one ~AMS signal must be connected at a time. For each switch listed in Table 2-7 that is turned ON, the size of available flash memory is reduced by 1 MB. Table 2-7.
ADSP-BF538F EZ-KIT Lite Hardware Reference Table 2-8. Audio Enable Switch (SW7) (Cont’d) EZ-KIT Lite Signal SW7 Switch Position (Default) Processor Signal TSCLK0 4 (ON) TSCLK0 TFS0 5 (ON) TFS0 Clock loopback 6 (ON) NU FS loopback 7 (ON) NU ADC master/slave 8 (ON) NU Boot Mode Select Switch (SW3) The rotary switch (SW3) determines the boot mode of the processor. Table 2-9 shows the available boot mode settings. By default, the ADSP-BF538F processor boots from the on-board flash memory.
Jumper and Switch Settings UART Loop Jumper (JP9) The UART loop jumper (JP9) is for looping the transmit and receive signals. The default is OFF. ELVIS Oscilloscope Configuration Switch (SW1) The oscilloscope configuration switch (SW1) determines which audio circuit signals connect to channels A and B of the oscilloscope. The switch is used when the board connects to the Educational Laboratory Virtual Instrumentation Suite (ELVIS) station (see “ELVIS Interface” on page 1-12).
ADSP-BF538F EZ-KIT Lite Hardware Reference ELVIS Function Generator Configuration Switch (SW8) The function generator configuration switch (SW8) controls signals connecting to the left and right input signals of the audio interface. The SW8 switch is used when the board connects to the ELVIS station (see “ELVIS Interface” on page 1-12). Each channel must have only one signal selected at a time, as described in Table 2-11. Table 2-11.
Jumper and Switch Settings ELVIS Voltage Selection Jumper (JP6) The ELVIS voltage selection jumper (JP6) is used to select the power source for the EZ-KIT Lite. In a standard mode of operation, the board receives its power from an external power supply. When JP6 is installed, the board is powered from an ELVIS station, and no external power supply is required. The jumper setting is shown in Table 2-12. Table 2-12.
ADSP-BF538F EZ-KIT Lite Hardware Reference LEDs and Push Buttons This section describes functionality of the LEDs and push buttons. Figure 2-3 shows the locations of the LEDs and push buttons. MONITOR Figure 2-3. LED and Push Button Locations Reset Push Button (SW9) The RESET push button resets all of the ICs on the board. One exception is the USB interface chip.
LEDs and Push Buttons Programmable Flag Push Buttons (SW10–13) Four push buttons, SW10–13, are provided for general-purpose user input. The buttons connect to the PF0-3 programmable flag pins of the processor. The push buttons are active high and, when pressed, send a high (1) to the processor. Refer to “LEDs and Push Buttons” on page 1-13 for more information on how to use the flags to program the processor.
ADSP-BF538F EZ-KIT Lite Hardware Reference User LEDs (LED2–6) Five LEDs connect to five general-purpose IO pins of the processor (see Table 2-15). The LEDs are active high and are lit by writing a 1 to the correct PC signal. Refer to “LEDs and Push Buttons” on page 1-13 for more information about how to use flash memory when programming the LEDs. Table 2-15.
Connectors Connectors This section describes the connector functionality and provides information about mating connectors. The connector locations are shown in Figure 2-4. Figure 2-4.
ADSP-BF538F EZ-KIT Lite Hardware Reference Audio Connectors (J9 and J10) Part Description Manufacturer Part Number 3.5 mm stereo jack A/D ELECTRONICS ST323-5 Mating Cable (shipped with EZ-KIT Lite) 3.5 mm stereo interconnect cable RANDOM 10A3-01106 3.
Connectors Power Connector (J7) The power connector provides all of the power necessary to operate the EZ-KIT Lite board. Part Description Manufacturer Part Number 2.5 mm power jack SWITCHCRAFT RAPC712X Mating Power Supply (shipped with EZ-KIT Lite) 7V power supply CUI INC. DMS070214-P6P-SZ Expansion Interface Connectors (J1–3) Three board-to-board connector footprints provide signals for most of the processor’s peripheral interfaces. The connectors are located at the bottom of the board.
ADSP-BF538F EZ-KIT Lite Hardware Reference JTAG Connector (ZP4) The JTAG header is the connecting point for a JTAG in-circuit emulator pod. When an emulator connects to the JTAG header, the USB debug interface is disabled. 3 is missing to provide keying. Pin 3 in the mating connector L Pin should have a plug. using an emulator with the EZ-KIT Lite board, follow the L When connection instructions provided with the emulator.
Connectors SPI Connector (P9) The pinout of the P9 connector can be found in “ADSP-BF538F EZ-KIT Lite Schematic” on page B-1. Part Description Manufacturer Part Number IDC header FCI 68737-420HLF Mating Connector IDC socket DIGI-KEY S4210-ND 2-Wire Interface Connector (P10) The pinout of the P10 connector can be found in “ADSP-BF538F EZ-KIT Lite Schematic” on page B-1.
ADSP-BF538F EZ-KIT Lite Hardware Reference UART1 Connector (P12) The pinout of the P12 connector can be found in “ADSP-BF538F EZ-KIT Lite Schematic” on page B-1.
Connectors 2-26 ADSP-BF538F EZ-KIT Lite Evaluation System Manual
A ADSP-BF538F EZ-KIT LITE BILL OF MATERIALS The bill of materials corresponds to “ADSP-BF538F EZ-KIT Lite Schematic” on page B-1. Ref. Qty. Description Reference Designator Manufacturer Part Number 1 1 74LVC14A SOIC14 U37 TI 74LVC14AD 2 1 IDT74FCT3244AP Y SSOP20 U36 IDT IDT74FCT3244APYG 3 1 SN74AHC1G00 SOT23-5 U39 TI SN74AHC1G00DBVR 4 1 12.288MHZ OSC003 U4 DIGI-KEY SG-8002CA-PCC-ND (12.288M) 5 1 32.768KHZ OSC008 Y2 EPSON MC-156-32.
Ref. Qty.
ADSP-BF538F EZ-KIT Lite Bill Of Materials Ref. Qty.
Ref. Qty.
ADSP-BF538F EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 61 71 0.01UF 16V 10% 0402 C1-27,C30-46, C91-93,C95-97, C103-104, C107-109,C132, C137,C141, C143-147, C202-205,C211, C225-227 AVX 0402YC103KAT2A 62 28 10K 1/16W 5% 0402 R2-3,R5,R7,R9, R12-16,R24-25, R77,R79-80, R84-85,R87-90, R162,R169, R171-172,R176, R179,R182,R216 VISHAY CRCW040210K0FKED 63 1 4.
Ref. Qty. Description Reference Designator Manufacturer Part Number 73 4 0.01UF 16V 10% 0603 C50-51,C62-63 AVX 0603YC103KAT2A 74 1 4.
ADSP-BF538F EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 88 4 5.49K 1/10W 1% 0603 R42-43,R46-47 DIGI-KEY 311-5.49KHRTR-ND 89 2 3.32K 1/10W 1% 0603 R44,R48 DIGI-KEY 311-3.32KHRTR-ND 90 2 1.65K 1/10W 1% 0603 R45,R49 DIGI-KEY 311-1.65KHRTR-ND 91 2 49.9K 1/10W 1% 0603 R38,R41 DIGI-KEY 311-49.9KHRTR-ND 92 2 604.0 1/10W 1% 0603 R50-51 DIGI-KEY 311-604HRTR-ND 93 2 90.9K 1/10W 1% 0603 R58,R63 DIGI-KEY 311-90.
Ref. Qty. Description Reference Designator Manufacturer Part Number 103 2 2200PF 50V 5% 0603 C76,C78 PANASONIC ECJ-1VB1H222K 104 2 2.74K 1/10W 1% 0603 R36,R52 DIGI-KEY 311-2.74KHRTR-ND 105 2 15.0K 1/16W 1% 0603 R106-107 DIGI-KEY 311-15.0KHRTR-ND 106 2 27PF 50V 5% 0402 C121,C129 AVX 04025A270JAT2A 107 1 10UF 10V 10% 0805 C98 PANASONIC ECJ-2FB1A106K 108 1 61.9K 1/16W 1% 0603 R111 PANASONIC ERJ-3EKF6192V 109 1 105.
A B C D 1 1 2 2 ADSP-BF538F EZ-KIT LITE SCHEMATIC 3 3 ANALOG DEVICES 4 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF538F EZ-KIT LITE TITLE Title Size 20 Cotton Road Rev A0203-2006 1.
A B C D U1 U1 A[1:19] 1 A1 N19 A2 N20 A3 P19 A4 P20 A5 R19 A6 R20 A7 T19 A8 T20 A9 U19 A10 U20 A11 V19 A12 V20 A13 W18 A14 W20 A15 W17 A16 Y19 A17 Y18 A18 W16 A19 Y17 U1 A1 Y10 D0 W10 D1 Y9 D2 W9 D3 Y8 D4 W8 D5 Y7 D6 W7 D7 Y6 D8 W6 D9 Y5 D10 W5 D11 Y4 D12 W4 D13 Y3 D14 W3 D15 D0 A2 D1 A3 D2 A4 D3 A5 D4 A6 D5 A7 D6 A8 D7 A9 D8 A10 D9 A11 D10 A12 D11 A13 D12 A14 D13 A15 D14 A16 D15 RFS0 DR0PRI DR0SEC
A B C D VDDEXT VDDEXT 1 U1 A1 GND1 A12 GND2 A15 GND3/ A17 GND4 A20 GND5 B2 GND6 B16 GND7 B18 GND8 B19 GND9 C3 GND10 C4 GND11 C18 GND12 D7 GND13 D8 GND14 D9 GND15 D10 GND16 D11 GND17 D12 GND18 D13 GND19 D14 GND20 D18 GND21 E3 GND22 E7 GND23 E8 GND24 E9 GND25 E10 GND26 E11 GND27 E12 GND28 E13 GND29 E14 GND30 E18 GND31 F3 GND32 F7 GND33 F8 GND34 F9 GND35 F10 GND36 F11 GND37 F12 GND38 F13 GND39 F14 GND40 1 B15 VDDEXT1 GND41 VDDEXT2 GND42 K3 M7 VDDEXT3 GND43 N7 VDDEXT4 GND44 VDDEXT5 GND45 P7
A B C D 3.
A B C D 3.3V R169 10K 0402 C216 10UF 0805 FER3 600 0603 1 R20 100K 0603 R21 5.76K 0603 1 SPI1SEL/PD4_AUDIO_RESET R28 5.76K 0603 U47 4 AUDIO_RESET 2 RESET 1 SN74LVC1G08 SOT23-5 C71 120PF 0603 C53 100PF 0603 3.3V R23 237.0 0603 U29 2 1 AGND 3 LMV722M SOIC8 R17 5.76K 0603 C70 1000PF 0603 R35 5.76K 0603 C68 100PF 0603 LABEL "LINE IN" J9 ADC LEFT ADC C47 120PF 0603 1 5 LEFT_IN AGND AMP_LEFT_IN 4 R32 750.
A B C D 1 1 C81 100PF 0603 R43 5.49K 0603 R40 11.0K 0603 R44 3.32K 0603 3.3V DAC LEFT DAC R54 33 0402 U4 1 OE OUT 96/48~ 3 6 384/256~ 12.288MHZ OSC003 CT2 68UF CAP003 U31 R50 604.0 0603 1 3 U38 10 2 C77 100PF 0603 MCLK R53 10K 0603 C79 330PF 0603 R42 5.49K 0603 16 OUTL17 OUTL+ C80 680PF 0603 LMV722M SOIC8 R45 1.65K 0603 R41 49.9K 0603 C78 2200PF 0603 7 X2MCLK 2 MCLK TSCLK0_S TFS0_S DT0PRI 2 3.3V 26 BCLK 13 OUTR12 OUTR+ R52 2.
A B C D 1 1 3.3V 5V R79 10K 0402 2 1 ON 1 2 7 3 6 4 5 2 3 SPI2SEL/PD9_CAN_ERR 4 CANRX/PC1_RTS 8 6 EN 14 STB 8 ERR R65 62.0 0603 R55 10 0603 R81 10K 0603 DNP J11 2 1 2 13 CANH 11 SPLIT 12 CANL CANTX/PC0_CTS SW2: CAN Enable Switch C106 100PF 0603 9 WAKE 1 TXD 4 RXD DIP4 SWT018 7 INH TJA1041 SOIC14 2 GND U21 SW2 5 VIO 3 VDD 10 VBAT R80 10K 0402 3.3V 3 4 CON039 C90 4700PF 0603 R66 62.0 0603 R62 10 0603 LABEL "CAN" J5 1 2 3 C94 100PF 0603 4 CON039 3.
A B C D 3.3V R87 10K 0402 U54 LABEL "PB1" R100 100 0805 U37 3 1 R6 10 0603 SW13 MOMENTARY SWT013 2 I0A 3 I1A 5 I0B 6 I1B 11 I0C 10 I1C 14 I0D 13 I1D WS_P0_1 4 3.
A B C D R163 0 0402 LEFT_IN A5V 3 14 6 7 4 13 5 12 6 11 V+ 7 10 8 6 9 ACH4+ ACH0+ SW8: Function Generator Switch 3 7 6 AD623ARMZ USOIC8 16 AMP_LEFT_IN AMP_RIGHT_IN 1 LEFT_OUT RIGHT_OUT DIP8 SWT016 R102 10.0K 0603 C205 0.01UF 0402 8 AD820ARZ SOIC8 5 REF DIP6 SWT017 R160 10.0K 0603 4 VOUT U11 2 ON 7 6 RG- 8 5 RG+ 1 5 4 8 15 SW1 1 ACH3+ 3 R61 0.
A B C D EXPANSION INTERFACE (TYPE B) 5V 3.3V 5V 3.
A B 5V C 3.3V 5V V_UNREG D 3.3V V_UNREG SPORT 0 SPORT 1 P6 2 1 P7 2 1 4 3 4 3 6 5 6 5 8 7 8 7 10 9 10 9 12 11 12 11 14 13 14 13 16 15 16 15 3.
A B R69 10K 0805 R70 10K 0805 C R71 10K 0805 R74 10K 0805 R73 10K 0805 D R72 10K 0805 1 1 P3 RFS2/PE1 RSCLK2/PE0 DR2PRI/PE2 DR2SEC/PE3 P4 1 2 3 4 5 6 7 8 10 9 10 11 12 11 12 13 14 13 14 15 16 15 16 17 18 17 18 19 20 19 20 1 2 3 4 5 6 7 8 9 TFS2/PE5 RFS3/PE9 TSCLK2/PE4 RSCLK3/PE8 DT2PRI/PE6 DR3PRI/PE10 DT2SEC/PE7 DR3SEC/PE11 TFS3/PE13 TSCLK3/PE12 DT3PRI/PE14 DT3SEC/PE15 IDC10X2 IDC10X2 SPORT2 SPORT3 2 2 P1 MOSI1/PD0 SPI1SS/PD3 SCK1/PD2 SPI1S
A B D4 S2A 2A DO-214AA F1 2.5A FUS001 FER7 190 FER002 4 3 1 2 C D V_UNREG LABEL "5V" 5V@5A J7 5V 1 C127 1000PF 0402 2 CT7 10UF C C130 0.1UF 0603 3 7.5V_POWER CON005 1 1 C128 1000PF 0402 L3 8UH IND008 FER1 600 0603 R116 0.015 0815 U12 C132 0.01UF 0402 1 R113 0 0603 DNP SHGND CT6 150UF D 8 2 U20 7 27 PGOOD C120 0.1UF 0402 28 RUN/SS1 30 SENSE1+ C129 27PF 0402 C119 1000PF 0805 RUBBER FOOT MSC009 M3 RUBBER FOOT MSC009 M4 RUBBER FOOT MSC009 M5 RUBBER FOOT MSC009 R107 15.
INDEX Numerics B 2-wire interface (TWI), 1-13, 2-24 background telemetry channel (BTC), 1-14 bill of materials, A-1 board schematic (ADSP-BF538F), B-1 boot mode select switch (SW3), 2-13 A AD1854 digital-to-analog converter (DAC), 1-12 AD1871 analog-to-digital converter (ADC), 1-12, 2-12 ADC master/slave modes, 2-13 AMP_LEFT_IN signal, 2-14, 2-15 AMP_RIGHT_IN signal, 2-14, 2-15 ~AMS3-0 (flash select) pins, 1-7, 2-3, 2-11, 2-12 analog audio, See audio architecture, of this EZ-KIT Lite, 2-2 ASYNC (asynch
INDEX connectors diagram of locations, 2-20 J1-3 (expansion), 2-3, 2-8, 2-22 J5 and J11 (CAN), 2-21 J6 (RS-232), 2-21 J7 (power), 2-22 J9-10 (audio), 2-21 P10 (TWI), 2-24 P11 (timers), 2-24 P12 (UART1), 2-25 P3 (SPORT1), 2-4 P4 (SPORT2), 2-4 P6 (SPORT0), 1-13, 2-4, 2-23 P8 (PPI), 2-23 P9 (SPI), 2-4, 2-24 SPORT0-1 (P6-7), 2-23 ZP4 (JTAG), 2-9, 2-23 contents, of this EZ-KIT Lite package, 1-3 Controller Area Network, See CAN core voltage, 2-2 CTS signals, 2-10 customer support, xv EBIU_SDBCTL register, 1-9,
INDEX H Help, online, xix I LEFT_IN signal, 2-15 LEFT_OUT signal, 2-14 license restrictions, x, 1-7 LOOPBACK signal, 2-10 installation, of this EZ-KIT Lite, 1-5 interfaces, See audio, CAN, ELVIS, expansion, SDRAM internal memory core/system MMRs, 1-8 data banks A, B SRAM, 1-8 data banks A, B SRAM/CACHE, 1-8 instruction banks A, B SRAM, 1-8 instruction SRAM/CACHE, 1-8 reserved, 1-8 scratch pad SRAM, 1-8 via JTAG, 2-9 internal regulator, 2-2 IO voltage, 2-2 M J O JTAG connector (ZP4), 2-23 emulation p
INDEX PPI_DIR_CTL signal, 2-6 PPI_FS3 signal, 2-7 programmable flags PC0 (UART transmit), 1-11, 2-4, 2-10 PC1 (UART receive), 1-11, 2-4, 2-10 PC5-9 (LED2-6), 1-13, 2-19 PD0-8 signals, 2-5 PD10-13, 2-6 PD7 (JP1), 2-13 PD9 (ERR), 1-11, 2-6, 2-10 PE0-15, 2-6 PF0-3 (SW13-10), 1-13, 2-7, 2-11, 2-18 PF4-15 (PPI), 2-7 push buttons See also switches by name (SWx) diagram of locations, 2-17 R real-time clock (RTC), 2-3 Reduced Instruction Set Computing (RISC), ix regulators, 2-2 reset LEDs (LED8), 2-18 processor,
INDEX SW6 (flash enable) switch, 1-10, 2-11 SW7 (audio enable) switch, 1-13, 2-12 SW8 (audio input) switch, 2-15 SW9 (reset) push button, 2-17 switches See also switches by name (SWx) diagram of locations, 2-9 synchronous dynamic random access memory, See SDRAM system architecture, of this EZ-KIT Lite, 2-2 clock frequency, 1-9 clock (SCLKx) signals, 1-10, 2-5, 2-6 T Target Options dialog box, 1-9 TFS0 signal, 2-13 TFS2 signal, 2-6 TFS3 signal, 2-6 timers connector (P11), 2-24 TMRCLK signal, 2-7 TSCLK0 sig
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