a MicroConverter ®, Multichannel 12-Bit ADC with Embedded FLASH MCU ADuC812 FEATURES ANALOG I/O 8-Channel, High Accuracy 12-Bit ADC On-Chip, 100 ppm/ C Voltage Reference High-Speed 200 kSPS DMA Controller for High-Speed ADC-to-RAM Capture Two 12-Bit Voltage Output DACs On-Chip Temperature Sensor Function MEMORY 8K Bytes On-Chip Flash/EE Program Memory 640 Bytes On-Chip Flash/EE Data Memory 256 Bytes On-Chip Data RAM 16M Bytes External Data Address Space 64K Bytes External Program Address Space 8051-COMPAT
ADuC812 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . 6 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN FUNCTION DISCRIPTIONS . . . . . . . . . . . . . . . . . . . . . .
ADuC812 1, 2 (AV SPECIFICATIONS DD = DVDD = 3.0 V or 5.0 V 10%, REFIN/REFOUT = 2.5 V Internal Reference, MCLKIN = 11.0592 MHz, fSAMPLE = 200 kHz, DAC VOUT Load to AGND; RL = 2 k , CL = 100 pF. All specifications TA = TMIN to TMAX, unless otherwise noted.
ADuC812–SPECIFICATIONS1, 2 (continued) Parameter ADuC812BS VDD = 5 V VDD = 3 V Unit Test Conditions/Comments DAC AC CHARACTERISTICS Voltage Output Settling Time 15 15 µs typ 10 10 nV sec typ Full-Scale Settling Time to Within 1/2 LSB of Final Value 1 LSB Change at Major Carry 2.3/VDD 150 2.5 ± 2.5% 2.5 100 2.
ADuC812 Parameter ADuC812BS VDD = 5 V VDD = 3 V Unit Test Conditions/Comments DIGITAL OUTPUTS Output High Voltage (VOH) 2.4 V min VDD = 4.5 V to 5.5 V ISOURCE = 80 µA VDD = 2.7 V to 3.3 V ISOURCE = 20 µA 4.0 Output Low Voltage (VOL) ALE, PSEN, Ports 0 and 2 Port 3 Floating State Leakage Current Floating State Output Capacitance POWER REQUIREMENTS14, 15, 16 IDD Normal Mode17 IDD Idle Mode IDD Power-Down Mode18 0.4 0.2 0.4 0.2 ± 10 ±5 10 43 32 26 8 25 18 15 7 50 5 2.6 V typ 0.2 0.
ADuC812 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS* PSEN EA P0.0/AD0 ALE P0.1/AD1 P0.3/AD3 P0.2/AD2 DVDD DGND P0.7/AD7 P0.6/AD6 AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V DVDD to DGND, AVDD to AGND . . . . . . . . . –0.3 V to +7 V Digital Input Voltage to DGND . . . . . –0.3 V, DVDD + 0.3 V Digital Output Voltage to DGND . . . . –0.3 V, DVDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . .
ADuC812 PIN FUNCTION DESCRIPTIONS Mnemonic Type Function DVDD AVDD CREF VREF P P I I/O AGND P1.0–P1.7 G I ADC0–ADC7 T2 I I T2EX I SS SDATA SCLOCK MOSI MISO DAC0 DAC1 RESET I I/O I/O I/O I/O O O I P3.0–P3.7 I/O RxD TxD INT0 I/O O I INT1 I T0 T1 CONVST I I I WR RD XTAL2 XTAL1 DGND P2.0–P2.7 (A8–A15) (A16–A23) O O O I G I/O REV. B Digital Positive Supply Voltage, 3 V or 5 V Nominal Analog Positive Supply Voltage, 3 V or 5 V Nominal Decoupling Input for On-Chip Reference. Connect 0.
ADuC812 PIN FUNCTION DESCRIPTION (continued) Mnemonic Type Function PSEN O ALE O EA I P0.7–P0.0 (A0–A7) I/O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution.
ADuC812 ARCHITECTURE, MAIN FEATURES 7FH The ADuC812 is a highly integrated true 12-bit data acquisition system. At its core, the ADuC812 incorporates a high- performance 8-bit (8052-Compatible) MCU with on-chip reprogrammable nonvolatile Flash program memory controlling a multichannel (8-input channels), 12-bit ADC. 2FH BANKS SELECTED VIA BITS IN PSW The chip incorporates all secondary functions to fully support the programmable data acquisition core.
ADuC812 OVERVIEW OF MCU-RELATED SFRs Accumulator SFR Power Control SFR ACC is the Accumulator register and is used for math operations including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions refer to the Accumulator as A. B SFR The Power Control (PCON) register contains bits for powersaving options and general-purpose status flags as shown in Table II.
ADuC812 SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general purpose register banks, reside in the special function register (SFR) area. The SFR registers include control, configuration and data registers that provide an interface between the CPU and other onchip peripherals. Figure 4 shows a full SFR memory map and SFR contents on Reset. Unoccupied SFR locations are shown dark-shaded in the figure below (NOT USED).
ADuC812 ADC CIRCUIT INFORMATION General Overview ADC Transfer Function The analog input range for the ADC is 0 V to VREF. For this range, the designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when VREF = 2.5 V. The ideal input/output transfer characteristic for the 0 to VREF range is shown in Figure 5.
ADuC812 ADCCON1 – (ADC Control SFR #1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below. SFR Address: EFH SFR Power-On Default Value: 20H MD1 MD0 CK1 CK0 AQ1 AQ0 T2C EXC Table III. ADCCON1 SFR Bit Designations Bit Name Description ADCCON1.7 ADCCON1.6 MD1 MD0 The mode bits (MD1, MD0) select the active operating mode of the ADC as follows: MD1 MD0 Active Mode 0 0 ADC powered down.
ADuC812 ADCCON2 – (ADC Control SFR #2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address: SFR Power On Default Value: ADCI DM A D8H 00H CCONV SCONV CS3 CS2 CS1 CS0 Table IV. ADCCON2 SFR Bit Designations Location Name ADCCON2.7 ADCI ADCCON2.6 DMA ADCCON2.5 CCONV ADCCON2.4 SCONV ADCCON2.3 ADCCON2.2 ADCCON2.1 ADCCON2.
ADuC812 Driving the A/D Converter The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. Figure 7 shows the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases as defined by the position of the switches in Figure 7. During the sampling phase (with SW1 and SW2 in the “track” position) a charge proportional to the voltage on the analog input is developed across the input sampling capacitor.
ADuC812 ground, no amplifier can deliver signals all the way to ground when powered by a single supply. Therefore, if a negative supply is available, you might consider using it to power the front-end amplifiers. If you do, however, be sure to include the Schottky diodes shown in Figure 8 (or at least the lower of the two diodes) to protect the analog input from undervoltage conditions. To summarize this section, use the circuit of Figure 8 to drive the analog input pins of the ADuC812.
ADuC812 core. This mode allows the ADuC812 to capture a contiguous sample stream at full ADC update rates (200 kHz). 00000AH A typical DMA Mode configuration example. To set the ADuC812 into DMA mode a number of steps must be followed. 1. The ADC must be powered down. This is done by ensuring MD1 and MD0 are both set to 0 in ADCCON1. 2. The DMA Address pointer must be set to the start address of where the ADC Results are to be written.
ADuC812 the gain calibration coefficient is divided into ADCGAINH (6 bits) and ADCGAINL (8 bits).The offset calibration coefficient compensates for dc offset errors in both the ADC and the input signal. Increasing the offset coefficient compensates for positive offset, and effectively pushes the ADC Transfer Function DOWN. Decreasing the offset coefficient compensates for negative offset, and effectively pushes the ADC Transfer Function UP.
ADuC812 Using the Flash/EE Data Memory The user Flash/EE data memory array consists of 640 bytes that are configured into 160 (Page 00H to Page 9FH), 4-byte pages as shown in Figure 16. Using the Flash/EE Program Memory This 8K Byte Flash/EE Program Memory array is mapped into the lower 8K bytes of the 64K bytes program space addressable by the ADuC812 and will be used to hold user code in typical applications.
ADuC812 ECON—Flash/EE Memory Control SFR Using the Flash/EE Memory Interface This SFR acts as a command interpreter and may be written with one of five command modes to enable various read, program and erase cycles as detailed in Table VII: As with all Flash/EE memory architectures, the array can be programmed in system at a byte level, although it must be erased first, the erasure being performed in page blocks (4-byte pages in this case). Table VII.
ADuC812 USER INTERFACE TO OTHER ON-CHIP ADuC812 PERIPHERALS The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC812 incorporates two 12-bit, voltage output DACs on-chip. Each has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to VREF (the internal bandgap 2.5 V reference) and 0 V to AVDD.
ADuC812 Using the D/A Converter VDD The on-chip D/A converter architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 18. Details of the actual DAC architecture can be found in U.S. Patent Number 5969657 (www.uspto.gov). Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity.
ADuC812 the DAC outputs will remain at ground potential whenever the DAC is disabled. However, each DAC output will still spike briefly when you first apply power to the chip, and again when each DAC is first enabled in software. Typical scope shots of these spikes are given in Figure 23 and Figure 24 respectively. OUTPUT VOLTAGE – V 3 2 200 s/DIV AVDD – 2V/DIV 1 0 0 5 10 SOURCE/SINK CURRENT – mA 15 Figure 21.
ADuC812 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset within a reasonable amount of time if the ADuC812 enters an erroneous state, possibly due to a programming error. The Watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR.
ADuC812 POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD and DVDD) on the ADuC812. It will indicate when either power supply drops below one of five user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the Power Supply Monitor function, AVDD must be equal to or greater than 2.7 V. The Power Supply Monitor function is controlled via the PSMCON SFR.
ADuC812 The ADuC812 integrates a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. It should be noted that the SPI pins are shared with the I2 C interface and therefore the user can only enable one or the other interface at any given time (see SPE in SPICON below).
ADuC812 Table XII. SPICON SFR Bit Designations (continued) Bit Name Description 1 0 SPR1 SPR0 SPI Bit-Rate Select Bits. These bits select the SCLOCK rate (bit-rate) in Master Mode as follows: SPR1 SPR0 Selected Bit Rate 0 0 fOSC/4 0 1 fOSC/8 1 0 fOSC/32 1 1 fosc/64 In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin #12) can be read via the SPR0 bit. NOTE The CPOL and CPHA bits should both contain the same values for master and slave devices.
ADuC812 I2C-COMPATIBLE INTERFACE previously). An Application Note describing the operation of this interface as implemented is available from the MicroConverter Website at www.analog.com/microconverter. This interface can be configured as a Software Master or Hardware Slave, and uses two pins in the interface. The ADuC812 supports a 2-wire serial interface mode which is I2C compatible.
ADuC812 Port 3 is a bidirectional port with internal pull-ups directly controlled via the P3 SFR (SFR address = B0 hex). Port 3 pins that have 1s written to them are pulled high by the internal pullups and in that state they can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-ups. Port 3 pins also have various secondary functions described in Table XV.
ADuC812 User configuration and control of all Timer operating modes is achieved via three SFRs, namely: TMOD Timer/Counter 0 and 1 Mode Register TMOD, TCON: SFR Address Power-On Default Value Bit Addressable 89H 00H No Control and configuration for Timers 0 and 1. Control and configuration for Timer 2. T2CON: Gate C/T M1 M0 Gate C/T M1 M0 Table XVI. TMOD SFR Bit Designations Bit Name Description 7 Gate 6 C/T 5 4 M1 M0 3 Gate 2 C/T 1 0 M1 M0 Timer 1 Gating Control.
ADuC812 TCON: Timer/Counter 0 and 1 Control Register SFR Address Power-On Default Value Bit Addressable TF1 TR1 88H 00H Yes TF0 1 TR0 IE1 IT1 1 IE0 1 IT0 1 NOTE 1 These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Table XVII. TCON SFR Bit Designations Bit Name Description 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Timer 1 Overflow Flag.
ADuC812 TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Auto Reload) The following paragraphs describe the operating modes for timer/ counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for timer 0 as for timer 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 28.
ADuC812 T2CON Timer/Counter 2 Control Register SFR Address Power-On Default Value Bit Addressable C8H 00H Yes TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 Table XVIII. T2CON SFR Bit Designations Bit Name Description 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 CNT2 0 CAP2 Timer 2 Overflow Flag. Set by hardware on a timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1. Cleared by user software. Timer 2 External Flag.
ADuC812 Timer/Counter Operation Modes 16-Bit Capture Mode The following paragraphs describe the operating modes for timer/ counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XIX. In the “Capture” mode, there are again two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt.
ADuC812 UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. The physical interface to the serial data network is via Pins RXD(P3.
ADuC812 Mode 0: 8-Bit Shift Register Mode Mode 2: 9-Bit UART with Fixed Baud Rate Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. The data is shifted out of the RXD line. The eight bits are transmitted with the least-significant bit (LSB) first, as shown in Figure 32.
ADuC812 Modes 1 and 3 Baud Rate = (1/16) × (Timer 2 Overflow Rate) Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles and not every core machine cycle as before. Hence, it increments six times faster than Timer 1, and therefore baud rates six times faster are possible.
ADuC812 INTERRUPT SYSTEM The ADuC812 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE: IP: IE2: Interrupt Enable Register. Interrupt Priority Register. Secondary Interrupt Enable Register. IE: Interrupt Enable Register SFR Address Power-On Default Value Bit Addressable A8H 00H Yes EA EADC ET2 ES ET1 EX1 ET0 EX0 Table XXIII.
ADuC812 IE2: Secondary Interrupt Enable Register SFR Address Power-On Default Value Bit Addressable A9H 00H No — — — — — — EPSMI ESI Table XXV. IE2 SFR Bit Designations Bit Name Description 7 6 5 4 3 2 1 0 — — — — — — EPSMI ESI Reserved for Future Use. Reserved for Future Use. Reserved for Future Use. Reserved for Future Use. Reserved for Future Use. Reserved for Future Use. Written by User to Enable “1” or Disable “0” Power Supply Monitor Interrupt.
ADuC812 ADuC812 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC812 into any hardware system. Clock Oscillator The clock source for the ADuC812 can come either from an external source or from the internal clock oscillator. To use the internal clock oscillator connect a parallel resonant crystal between Pins 32 and 33, and connect a capacitor from each pin to ground as shown below.
ADuC812 If access to more than 64K bytes of RAM is desired, a feature unique to the ADuC812 allows addressing up to 16M bytes of external RAM simply by adding an additional latch as illustrated in Figure 39. ADuC812 SRAM The best way to implement an external POR function to meet the above requirements involves the use of a dedicated POR chip, such as the ADM809/ADM810 SOT-23 packaged PORs from Analog Devices.
ADuC812 As an alternative to providing two separate power supplies, the user can help keep AVDD quiet by placing a small series resistor and/or ferrite bead between it and DVDD, and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 44. With this configuration other analog circuitry (such as op amps, voltage reference, etc.) can be powered from the AVDD supply line as well.
ADuC812 Grounding and Board Layout Recommendations As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC812-based designs in order to achieve optimum performance from the ADCs and DAC.
ADuC812 DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) DVDD DVDD 1k 49 48 47 46 45 44 43 42 41 40 EA 50 PSEN 51 ADC0 DVDD 52 51 ANALOG INPUT DGND 1k 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN) 39 38 37 AVDD 36 AVDD AGND VREF OUTPUT DVDD DGND 35 DVDD 34 ADuC812 CREF XTAL2 33 VREF XTAL1 32 DAC0 31 DAC1 30 11.
ADuC812 Note that the serial port debugger is fully contained on the ADuC812 device, (unlike “ROM monitor” type debuggers) and therefore no external memory is needed to enable in-system debug sessions. Single-Pin Emulation Mode Also built into the ADuC812 is a dedicated controller for single-pin in-circuit emulation (ICE) using standard production ADuC812 devices. In this mode, emulation access is gained by connection to a single pin, the EA pin.
ADuC812 TIMING SPECIFICATIONS1, 2, 3 (AV DD = DVDD = 3.0 V or 5.0 V 10%. All specifications TA = TMIN to TMAX unless otherwise noted.) Parameter Min CLOCK INPUT (External Clock Driven XTAL1) XTAL1 Period tCK XTAL1 Width Low tCKL XTAL1 Width High tCKH tCKR XTAL1 Rise Time XTAL1 Fall Time tCKF tCYC4 ADuC812 Machine Cycle Time 12 MHz Typ Max 83.33 Variable Clock Min Typ Max 62.
ADuC812 Parameter 12 MHz Min Max Variable Clock Min Max 127 43 53 2tCK – 40 tCK – 40 tCK – 30 Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns 52 52 52 52 52 52 52 52 52 52 52 52 EXTERNAL PROGRAM MEMORY tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tPHAX ALE Pulsewidth Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulsewidth PSEN Low to Valid Instruction In Input Instruction Hold after PSEN Input Instruction Float af
ADuC812 Parameter 12 MHz Min Max Variable Clock Min Max 400 43 48 6tCK – 100 tCK – 40 tCK – 35 Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns 53 53 53 53 53 53 53 53 53 53 53 53 EXTERNAL DATA MEMORY READ CYCLE tRLRH tAVLL tLLAX tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tRLAZ tWHLH RD Pulsewidth Address Valid after ALE Low Address Hold after ALE Low RD Low to Valid Data In Data and Address Hold after RD Data Float after RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low A
ADuC812 Parameter 12 MHz Min Max Variable Clock Min Max Unit Figure 400 43 48 200 203 33 433 33 43 6tCK – 100 tCK – 40 tCK – 35 3tCK – 50 4tCK – 130 tCK – 50 7tCK – 150 tCK – 50 tCK – 40 ns ns ns ns ns ns ns ns ns 54 54 54 54 54 54 54 54 54 EXTERNAL DATA MEMORY WRITE CYCLE tWLWH tAVLL tLLAX tLLWL tAVWL tQVWX tQVWH tWHQX tWHLH WR Pulsewidth Address Valid after ALE Low Address Hold after ALE Low ALE Low to RD or WR Low Address Valid to RD or WR Low Data Valid to WR Transition Data Setup Before WR Da
ADuC812 Parameter Min 12 MHz Typ Max Min Variable Clock Typ Max Unit Figure µs ns ns ns ns 55 55 55 55 55 UART TIMING (Shift Register Mode) tXLXL tQVXH tDVXH tXHDX tXHQX Serial Port Clock Cycle Time Output Data Setup to Clock Input Data Setup to Clock Input Data Hold after Clock Output Data Hold after Clock 1.
ADuC812 Parameter Min Max Unit Figure µs µs µs ns µs µs µs 56 56 56 56 56 56 56 µs ns ns ns 56 56 56 56 2 I C-COMPATIBLE INTERFACE TIMING tL tH tSHD tDSU tDHD tRSU tPSU tBUF SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Start Condition Hold Time Data Setup Time Data Hold Time Setup Time for Repeated Start Stop Condition Setup Time Bus Free Time between a STOP Condition and a START Condition Rise Time of Both SCLOCK and SDATA Fall Time of Both SCLOCK and SDATA Pulsewidth of Spike Suppressed tR tF
ADuC812 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns 57 57 57 57 57 57 57 57 57 SPI MASTER MODE TIMING (CPHA = 1) tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time 330 330 50 100 100 10 10 10 10 25 25 25 25 SCLOCK (CPOL=0) t SL t SH t SR t SF SCLOCK (
ADuC812 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns ns 58 58 58 58 58 58 58 58 58 58 SPI MASTER MODE TIMING (CPHA = 0) tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Output Setup before SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time 330 330 50 150 100 100 10 10 10 10 25 25 25
ADuC812 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns ns ns 59 59 59 59 59 59 59 59 59 59 59 SPI SLAVE MODE TIMING (CPHA = 1) tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS SS to SCLOCK Edge SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time SS High after SCLOCK Edge 0 330 330 50 100 100 10 10 10
ADuC812 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns 60 60 60 60 60 60 60 60 60 60 60 60 SPI SLAVE MODE TIMING (CPHA = 0) tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOSS tSFS SS to SCLOCK Edge SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time Data Output Valid after SS Edge SS High after
ADuC812 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.094 (2.39) 0.084 (2.13) 0.557 (14.15) SQ 0.537 (13.65) 0.037 (0.95) 0.026 (0.65) 52 40 1 39 PIN 1 SEATING PLANE 0.398 (10.11) SQ 0.390 (9.91) TOP VIEW (PINS DOWN) 0.012 (0.30) 0.006 (0.15) 13 27 14 0.008 (0.20) 0.006 (0.15) 0.082 (2.09) 0.078 (1.97) C00208–0–10/01(B) 52-Lead Plastic Quad Flatpack (S-52) 26 0.025 (0.65) BSC 0.014 (0.35) 0.010 (0.25) Revision History Location Page Data Sheet changed from REV. A to REV. B.