ADSP-21369 EZ-KIT Lite® Evaluation System Manual Revision 1.0, August 2005 Part Number 82-000196-01 Analog Devices, Inc. One Technology Way Norwood, Mass.
Copyright Information © 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Limited Warranty The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice.
Regulatory Compliance The ADSP-21369 EZ-KIT Lite evaluation system has been certified to comply with the essential requirements of the European EMC directive 89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE” mark. The ADSP-21369 EZ-KIT Lite evaluation system had been appended to Analog Devices Development Tools Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE Certification by an appointed European Competent Body and is on file.
CONTENTS PREFACE Purpose of This Manual ................................................................ xiii Intended Audience ........................................................................ xiii Manual Contents .......................................................................... xiii What’s New in This Manual ........................................................... xiv Technical or Customer Support ...................................................... xiv Supported Processors .........
CONTENTS Data Sheets ......................................................................... xxi Notation Conventions .................................................................. xxii USING EZ-KIT LITE Package Contents ......................................................................... 1-2 Default Configuration .................................................................. 1-3 Installation and Session Startup .....................................................
CONTENTS Boot Mode and Clock Ratio Select Switch (SW2) ..................... 2-8 Codec Setup Switch (SW3) .................................................... 2-10 Electret Microphone Select Switch (SW4) .............................. 2-11 UART Enable Switch (SW5) .................................................. 2-11 Loop-Back Test Switches (SW6 and SW14) ............................ 2-12 Push Button Enable Switch (SW7) .........................................
CONTENTS Headphone Out Jack (P7) ..................................................... 2-22 Power Jack (J4) ..................................................................... 2-22 RS-232 Connector (P1) ........................................................ 2-23 SPDIF Coax Connectors (P8 and P9) .................................... 2-23 DPI Header (P3) ................................................................... 2-24 DAI Header (P4) ...............................................................
PREFACE Thank you for purchasing the ADSP-21369 EZ-KIT Lite®, Analog Devices, Inc. evaluation system for ADSP-21369 SHARC® processors. The SHARC processors are based on a 32-bit super Harvard architecture that includes a unique memory architecture comprised of two large on-chip, dual-ported SRAM blocks coupled with a sophisticated IO processor, which gives a SHARC processor the bandwidth for sustained high-speed computations.
Access to the ADSP-21369 processor from a personal computer (PC) is achieved through a USB port or an optional JTAG emulator. The USB interface gives unrestricted access to the ADSP-21369 processor and the evaluation board peripherals. Analog Devices JTAG emulators offer faster communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products. To learn more about Analog Devices emulators and processor development tools, go to http://www.analog.
Preface • Serial peripheral interconnect (SPI) flash memory D 2 Mbit • Analog audio interface D D D D AD1835A codec 4x2 RCA phono jack for 4 channels of stereo output 2x1 RCA phono jack for 1 channel of stereo input 3.
• Expansion interface (Type A) D Parallel Port, FLAG pins, DPI, DAI • Other features D D D D JTAG ICE 14-pin header Test points for processor current measurement DPI header DAI header The EZ-KIT Lite board has a total of 1 MB of parallel flash memory and 2 Mbit of SPI flash memory. The flash memories can store user-specific boot code, allowing the board to run as a stand-alone unit. For more information, see “External Memory” on page 1-7 and “Boot Mode and Clock Ratio Select Switch (SW2)” on page 2-8.
Preface Purpose of This Manual The ADSP-21369 EZ-KIT Lite Evaluation System Manual provides instructions for installing the product hardware (board) and describes the operation and configuration of the board components. The product software component is detailed in the VisualDSP++ Installation Quick Reference Card. The manual provides guidelines for running your own code on the ADSP-21369 EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a reference for future designs.
What’s New in This Manual • Chapter 2, “EZ-KIT Lite Hardware Reference” on page 2-1 Provides information on the hardware aspects of the evaluation system. • Appendix A, “Bill Of Materials” on page A-1 Provides a list of components used to manufacture the EZ-KIT Lite board. • Appendix B, “Schematics” on page B-1 Provides the resources to allow modifications to the EZ-KIT Lite or to use as a reference design. appendix is not part of the online Help.
Preface • E-mail processor questions to processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.com (China support) • Phone questions to 1-800-ANALOGD • Contact your Analog Devices, Inc. local sales office or authorized distributor • Send questions by mail to: Analog Devices, Inc. One Technology Way P.O.
Product Information MyAnalog.com MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more. Registration: Visit http://www.myanalog.com to sign up.
Preface Related Documents For information on product related development software and hardware, see these publications: Table 1.
Product Information you plan to use the EZ-KIT Lite board in conjunction with a L IfJTAG emulator, also refer to the documentation that accompanies the emulator. All documentation is available online. Most documentation is available in printed form. Visit the Technical Library Web site to access all processor and tools manuals and data sheets: http://www.analog.com/processors/resources/technicalLibrary.
Preface If documentation is not installed on your system as part of the software installation, you can add it from the VisualDSP++ CD at any time by running the Tools installation. Access the online documentation from the VisualDSP++ environment, Windows® Explorer, or the Analog Devices Web site. Accessing Documentation From VisualDSP++ To view VisualDSP++ Help, click on the Help menu item or go to the Windows task bar and navigate to the VisualDSP++ documentation via the Start menu.
Product Information Select a processor family and book title. Download archive (.ZIP) files, one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files. Printed Manuals For general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts. VisualDSP++ Documentation Set To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit.
Preface Data Sheets All data sheets (preliminary and production) may be downloaded from the Analog Devices Web site. Only production (final) data sheets (Rev. 0, A, B, C, and so on) can be obtained from the Literature Center at 1-800-ANALOGD (1-800-262-5643); they also can be downloaded from the Web site. To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you.
Notation Conventions Notation Conventions Text conventions used in this manual are identified and described as follows. xxii Example Description Close command (File menu) Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu). {this | that} Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that.
Preface conventions, which apply only to specific chapters, may L Additional appear throughout this document.
Notation Conventions xxiv ADSP-21369 EZ-KIT Lite Evaluation System Manual
1 USING EZ-KIT LITE This chapter provides specific information to assist you with development of programs for the ADSP-21369 EZ-KIT Lite evaluation system. The information appears in the following sections. • “Package Contents” on page 1-2 Lists the items contained in your ADSP-21369 EZ-KIT Lite package. • “Default Configuration” on page 1-3 Shows the default configuration of the ADSP-21369 EZ-KIT Lite.
Package Contents • “Analog Audio” on page 1-9· Describes how to set up and communicate with the on-board audio codec. • “LEDs and Push Buttons” on page 1-10 Describes the board’s general-purpose IO pins and buttons. • “Example Programs” on page 1-12 Provides information about the example programs included in the ADSP-21369 EZ-KIT Lite evaluation system. • “Background Telemetry Channel” on page 1-12 Highlights the advantages of the Background Telemetry Channel feature of VisualDSP++.
Using EZ-KIT Lite D USB driver files D Example programs D ADSP-21369 EZ-KIT Lite Evaluation System Manual (this document) • Universal 7V DC power supply • USB 2.0 cable • 3.5 mm stereo headphones • 6-foot RCA audio cable • 6-foot 3.5 mm/RCA x 2 Y-cable • Registration card (please fill out and return) If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or contact Analog Devices, Inc.
Installation and Session Startup When removing the EZ-KIT Lite board from the package, handle the board carefully to avoid the discharge of static electricity, which may damage some components. To connect the EZ-KIT Lite board: 1. Remove the EZ-KIT Lite board from the package. Be careful when handling the board to avoid the discharge of static electricity, which may damage some components. 2. Figure 1-1 shows the default jumper settings, DIP switch, connector locations, and LEDs used in installation.
Using EZ-KIT Lite Figure 1-1. EZ-KIT Lite Hardware Setup To start up an EZ-KIT Lite session in VisualDSP++: 1. Verify that the yellow USB monitor LED (LED11, located near the USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++. 2. From the Start menu, navigate to the VisualDSP++ environment via the Programs menu.
Evaluation License Restrictions dialog box appears on the screen (skip the rest of the procedure and go to step 3). If you have run VisualDSP++ previously, the last opened session appears on the screen. To switch to another session, via the Session List dialog box, hold down the Ctrl key while starting VisualDSP++ (go to step 5). 3. In Debug target, select SHARC Emulators/EZKIT Lites. In Platform, select ADSP-21369 EZ-KIT Lite via Debug Agent. In Processor, choose the appropriate processor, ADSP-21369.
Using EZ-KIT Lite External Memory The EZ-KIT Lite contains four types of memory: parallel flash (1 MB), SPI flash (2 Mbit), SRAM (512 Kbit), and SDRAM (128 Mbit). The flash memories can store user-specific boot code, allowing the board run as a stand-alone unit. For more information about selecting the boot device for the processor, see “Boot Mode and Clock Ratio Select Switch (SW2)” on page 2-8. Table 1-1 provides start and end addresses of the board’s external memories. Table 1-1.
ELVIS Interface The SPI flash memory connects to the SPI port of the processor and designates: • DPI pin 5 (DPI5) as a chip select • DPI pin 3 (DPI3) as the SPI clock • DPI pin 1 (DPI1) as the MOSI • DPI pin 2 (DPI2) as the MISO. By default, the DPI is setup for the SPI flash, and any required changes to the SPI flash can be made by modifying the DPI of the processor.
Using EZ-KIT Lite The ELVIS interface is a LabVIEW-based design and prototype environment for university science and engineering laboratories. The ELVIS interface consists of LabVIEW-based virtual instruments, a multifunction data acquisition (DAQ) device, and a custom-designed bench-top workstation and prototype board. This combination provides a ready-to-use suite of instruments found in most educational laboratories.
LEDs and Push Buttons routing unit (SRU). It is also necessary to disable the on-board audio oscillator from driving the audio codec and the processor’s input pin. For instructions on how to configure the clock, refer to “Codec Setup Switch (SW3)” on page 2-10. The AD1835A codec can be configured as a master or as a slave, depending on the DIP switch settings. In master mode, the AD1835A drives the serial port clock and frame sync signals to the processor.
Using EZ-KIT Lite Two of the general-purpose push buttons are attached to the FLAG pins of the processor, while the other two are attached to the DAI pins. All of the push buttons connect to the processor through a DIP switch. The DIP switch allows processor pins, which connect to the push buttons, to be disconnected. See “Push Button Enable Switch (SW7)” on page 2-12 for instructions on how to disable the push buttons from driving the corresponding processor pin.
Example Programs Table 1-3. LED Connections LED Reference Designator Processor Pin LED1 DPI6 LED2 DPI7 LED3 DPI8 LED4 DPI13 LED5 DPI14 LED6 DAI15 LED7 DAI16 LED8 FLAG3/~MS3/~IRQ3 Example Programs Example programs are provided with the ADSP-21369 EZ-KIT Lite to demonstrate various capabilities of the evaluation board.
Using EZ-KIT Lite sors/resources/crosscore/emulators/index.html. For more information about the background telemetry channel, see the VisualDSP++ User’s Guide or online Help.
Background Telemetry Channel 1-14 ADSP-21369 EZ-KIT Lite Evaluation System Manual
2 EZ-KIT LITE HARDWARE REFERENCE This chapter describes the hardware design of the ADSP-21369 EZ-KIT Lite board. The following topics are covered. • “System Architecture” on page 2-2 Describes the configuration of the ADSP-21369 board and explains how the board components interface with the processor. • “Switch Settings” on page 2-8 Shows the location and describes the function of the board switches.
System Architecture System Architecture This section describes the processor’s configuration on the EZ-KIT Lite board (Figure 2-1). 4M x 32 SDRAM 1M x 8 Flash External Port JTAG Port JTAG Header 512k x 8 SRAM ADSP-21369 DSP 24.576 MHz Oscillator Expansion Connectors Type A Reset PB DPI Conn +7.0V Connector RS 232 Conn FLAGs 0,1, and 3 DPI DAI SPDIF In Phono ADM3202 SPDIF Out Phono AD1835 CODEC 5 DAI Conn 1 A5V 3.3V 1.
EZ-KIT Lite Hardware Reference The CLKIN pin of the processor connects to a 24.576 MHz oscillator. The core frequency of the processor is derived by multiplying the frequency at the CLKIN pin by a value determined by the state of the processor pins CLKCFG1 and CLKCFG0. The value at these pins is determined by the state of the SW2 switch (see “Boot Mode and Clock Ratio Select Switch (SW2)” on page 2-8). By default, the EZ-KIT Lite gives a core frequency of 393.216 MHz.
System Architecture DAI Interface The pins of the digital application interface (DAI) connect to the signal routing unit (SRU). The SRU is a flexible routing system, providing a large system of signal flows within the processor. In general, the SRU allows to route the DAI pins to different internal peripherals in various combinations.
EZ-KIT Lite Hardware Reference To use the DAI for a different purpose, disable any signal driving the DAI pins with a switch (see “Codec Setup Switch (SW3)” on page 2-10). In addition, the SW3 switch allows flexible routing of the 12.288 MHz audio oscillator’s output signal. By default, this signal is used as the master clock (MCLK) for the AD1835A codec. All of the DAI signals are available externally via the expansion interface connectors (J3–1), as well as the 0.1” spaced header P4.
System Architecture Figure 2-3 illustrates the EZ-KIT Lite’s connections to the DPI. The DPI pins connect to the SPI flash memory, the SPI interface of the AD1835A codec, a UART, a 20-pin header, and five LEDs. To use the DPI for a different purpose, disable any signal driving the DPI pins with a switch (see “UART Enable Switch (SW5)” on page 2-11). Any DPI pin connected to an LED can be used without having to disconnect the pin.
EZ-KIT Lite Hardware Reference External PLL The ADSP-21369 EZ-KIT Lite contains an external phase lock loop to help generate a faster and more stable master input clock MCLK. The PLL uses DAI pin 3 as an input clock from the ADSP-21369 processor. The new clock generated by PLL connects to the processor via DAI pin 2. Example programs are included in the EZ-KIT Lite installation directory to demonstrate how to configure and use the board’s external PLL.
Switch Settings JTAG Emulation Port The JTAG emulation port allows an emulator to access the internal and external memory of the processor through a 6-pin interface. The JTAG emulation port of the processor also connects to the USB debugging interface. When an emulator connects to the board at P2, the USB debugging interface is disabled. This is not the standard connection of the JTAG interface.
EZ-KIT Lite Hardware Reference Figure 2-4. Switch Locations and Default Settings Table 2-3. Boot Mode Configuration Switch (SW2) BOOTCFG1 Pin (Position 1) BOOTCFG0 Pin (Position 2) Boot Mode ON ON SPI Slave Boot ON OFF Flash Boot1 OFF ON SPI Master Boot OFF OFF Reserved 1 Bold typeface denotes the default setting.
Switch Settings Table 2-4. Core Clock Rate Configuration CLKCFG1 (Position 3) CLKCFG0 (Position 4) Core to CLKIN Ratio ON ON 6:1 ON OFF 16:11 OFF ON 32:1 OFF OFF Reserved 1 Bold typeface denotes the default ratio. The core clock frequency can be increased or decreased via software by writing to the PMCTL register. For more information on changing core clock frequency and other setup information, refer to the ADSP-2136x SHARC Processor Hardware Reference for ADSP-21367/8/9 Processors.
EZ-KIT Lite Hardware Reference ADSP-21369 Processor AD1835A Codec DAI_P6 MCLK DAI_P17 12.288MHz OSC SW3.1 SW3.2 Figure 2-5. Audio Clock Routing Position 4 of SW3 disconnects the AD1835A’s ADC_DATA pin from the DAI interface. This is useful when the DAI interface connects to another device. Electret Microphone Select Switch (SW4) To connect an electret microphone to the audio input, place all positions of the SW4 switch ON. The default position of the switch is all OFF.
Switch Settings Table 2-5. UART Enable Switch (SW5) Switch Position EZ-KIT Lite Signal Processor Signal 1 (OFF1) CTS DPI12 2 (ON) RX DPI10 3 (OFF) RTS DP11 4 (ON) T2IN 1 tied to R2OUT N/A Bold typeface denotes the default setting. Loop-Back Test Switches (SW6 and SW14) The loop-back test switch SW6 is located at the top left side of the board. The second loop-back test switch, SW14, is located at the top right side of the board.
EZ-KIT Lite Hardware Reference ELVIS Oscilloscope Configuration Switch (SW1) The oscilloscope configuration switch (SW1) determines which audio circuit signals connect to channels A and B of the oscilloscope. The switch is used only when the board connects to the Educational Laboratory Virtual Instrumentation Suite (ELVIS) station (see “ELVIS Interface” on page 1-8). Each channel must have only one signal selected at a time, as described in Table 2-7. Table 2-7.
LEDs and Push Buttons Table 2-8. ELVIS Function Generator Configuration Switch (SW13) Channel Switch Position Audio Signal AMP_LEFT_IN 1 (ON1) LEFT_IN AMP_RIGHT_IN 2 (ON) RIGHT_IN AMP_LEFT_IN 3 (OFF) DAC0 AMP_RIGHT_IN 4 (OFF) DAC1 AMP_LEFT_IN 5 (OFF) FUNCT_OUT AMP_RIGHT_IN 6 (OFF) FUNCT_OUT 1 Bold typeface denotes the default settings. LEDs and Push Buttons This section describes the functionality of the LEDs and push buttons. Figure 2-6 shows the LED and push button locations.
EZ-KIT Lite Hardware Reference Figure 2-6. LED and Push Button Locations Reset LEDs (LED10 and LED12) When LED10 is lit (red), the master reset of all the major ICs is active. When LED12 is lit (red), the USB interface chip (U4) is being reset. The USB chip is reset only on power-up, or if USB communication has not been initialized.
LEDs and Push Buttons USB Monitor LED (LED11) The USB monitor LED (LED11) indicates that USB communication has been initialized successfully, and you can connect to the processor using a VisualDSP++ EZ-KIT Lite session. Once the USB cable is plugged into the board, it takes approximately 15 seconds for the USB monitor LED to light. If the LED does not light, try cycling power on the board and/or reinstalling the USB driver (see the VisualDSP++ Installation Quick Reference Card).
EZ-KIT Lite Hardware Reference Table 2-9. Push Button Connections (Cont’d) Push Button Label Push Button Reference Designator Processor Pin PB3 SW10 DAI19 PB4 SW9 DAI20 Board Reset Push Button (SW12) The RESET push button (SW12) resets all of the ICs on the board. The only exception is the USB interface chip (U4). The chip is not being reset when the push button is pressed after the USB cable has been plugged in and communication correctly initialized with the PC.
Jumpers Figure 2-7. Jumper Locations Table 2-10. VCO Select Jumper (JP1) JP1 Setting Mode OFF VCO Output frequency x ½ (default) ON VCO output frequency x 1.
EZ-KIT Lite Hardware Reference ELVIS Select Jumper (JP2) The ELVIS select jumper (JP2) configures the EZ-KIT Lite’s connection to an ELVIS station (see “ELVIS Interface” on page 1-8). When JP2 is installed, the connections to the push buttons and LED are re-directed to the ELVIS station, instead of the processor. The jumper settings are shown in Table 2-11. Table 2-11.
Connectors ELVIS Programmable Flag Jumper (JP4) The ELVIS programmable flag jumper (JP4) connects the ADSP-21369 processor’s DAI4 pin to the ELVIS trigger pin. When JP4 is installed, DAI4 is directly connected to the ELVIS TRIG1_2 pin. Conversely, when JP4 is uninstalled, the DAIP4 pin is disconnected and can be used for other non-ELVIS functionality. The jumper settings are shown in Table 2-13. Table 2-13.
EZ-KIT Lite Hardware Reference Figure 2-8. Connector Locations Part Description Manufacturer Part Number 90 Position 0.05" Spacing, SMT Samtec SFC-145-T2-F-D-A Mating Connector 90 Position 0.
Connectors Part Description Manufacturer Part Number 90 Position 0.05” Spacing (Surface Mount) Samtec TFM-145-x2 Series 90 Position 0.
EZ-KIT Lite Hardware Reference Part Description Manufacturer Part Number 2.5 mm Power Jack Switchcraft Digi-Key RAPC712 SC1152-ND Mating Power Supply (shipped with EZ-KIT Lite) 7V Power Supply CUI Inc. DMS070214-P6P-SZ The power connector supplies DC power to the EZ-KIT Lite board. Table 2-14 shows the power supply specifications. Table 2-14. Power Supply Specifications Terminal Connection Center pin +7 VDC@2.
Connectors DPI Header (P3) The DPI connector (P3) provides access to all of the DPI signals in the from of a .1” spacing header. When using the header to access the DPI pins of the processor, ensure that signals, which normally drive the DPI pins, are disabled. For more information, see “DPI Interface” on page 2-5. Part Description Manufacturer Part Number 20-pin IDC Header Sullins S2012-10 DAI Header (P4) The DAI connector (P4) provides access to all of the DAI signals in the from of a .
EZ-KIT Lite Hardware Reference JTAG Header (P2) The JTAG header (P2) is the connecting point for a JTAG in-circuit emulator pod. When an emulator is connected to the JTAG header, the USB debug interface is disabled. 3 is missing to provide keying. Pin 3 in the mating connector L Pin should have a plug. using an emulator with the EZ-KIT Lite board, follow the L When connection instructions provided with the emulator.
Connectors 2-26 ADSP-21369 EZ-KIT Lite Evaluation System Manual
A BILL OF MATERIALS The bill of materials corresponds to the board schematics on page B-1. Please check the latest schematics on the Analog Devices website, http://www.analog.com/Processors/Processors/DevelopmentTools/tec hnicalLibrary/manuals/DevToolsIndex.html#Evaluation%20Kit%20Manuals.
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# 2 5 3 2 1 6 1 1 9 10 4 1 6 Ref. 38 39 40 41 42 43 44 45 46 47 48 ADSP-21369 EZ-KIT Lite Evaluation System Manual 49 50 600 100MHZ 200MA 603 0.50 BEAD 220PF 50V 10% 1206 NPO 0.1uF 50V 10% 805 CERM 0.22UF 25V 10% 805 CERM AMBER-SMT LED001 GULL-WING RCA RCA_1X2 CON031 RA DB9 9PIN DB9F RIGHT ANGLE FEMALE DIP4 SWT018 4PIN-SMT-SWT DIP6 SWT017 DIP8 SWT016 0.
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ADSP-21369 EZ-KIT Lite Evaluation System Manual 2 1 1 2 1 2 1 4 4 1 1 1 1 1 119 120 121 122 123 124 125 126 127 128 129 130 131 132 1 2 118 133 # Ref. 3.5MM STEREO_JACK CON001 2.5A RESETABLE FUS001 IDC 13X2 IDC13X2 IDC 10X2 IDC10X2 IDC 7X2 IDC7X2 HEADER IDC 2X2 IDC2X2 0.1x0.1 IDC 2X1 IDC2X1 2X1 TIN ADG774A QSOP16 QUICKSWITCH-257 GREEN-SMT LED001 GULL-WING RED-SMT LED001 GULL-WING 511 1/16W 1% 402 301 1/16W 1% 0603 232 1/16W 1% 0603 15K 1/16W 1% 0603 2.05K 1/16W 1% 402 0.
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A B C D 1 1 2 2 ADSP-21369 EZ-KIT Lite Schematic 3 3 DNP = Do Not Populate ANALOG DEVICES 4 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-21369 EZ-KIT Lite TITLE Title Size 20 Cotton Road Rev A0196-2005 1.
A B U44 ADDR[0:23] ADDR0 ADDR1 ADDR2 ADDR3 1 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 2 N2 SDCLK0 B2 SDCLK1 T1 SDCKE T2 SDCAS R2 SDRAS R1 SDWE P1 SDA10 SDCLK1 SDCKE SDCAS SDRAS SDWE SDA10 U19 DATA0 V19 DATA1 DATA0 U44 DATA1 U20 DATA2 V20 DATA3 T20 DATA4 T19 DATA5 R19 DATA6 R20 DATA7 P19 DATA8 P20 DATA9 N20 DATA10 N19 DATA11 M19 DATA12 M20 DATA13 MS1 MS2_FLAG2_IRQ2 MS3_FLAG3_IR
A B C D VDDINT U44 1 2 VDDEXT 3 E3 VDDINT1 E4 VDDINT2 C7 VDDINT3 C10 VDDINT4 C13 VDDINT5 C16 VDDINT6 C17 VDDINT7 C18 VDDINT8 G17 VDDINT9 G18 VDDINT10 L3 VDDINT11 L4 VDDINT12 D7 VDDINT13 D10 VDDINT14 D13 VDDINT15 H3 VDDINT16 H4 VDDINT17 U3 VDDINT18 U8 VDDINT19 U12 VDDINT20 U15 VDDINT21 U17 VDDINT22 U18 VDDINT23 K17 VDDINT24 K18 VDDINT25 P3 VDDINT26 P4 VDDINT27 P17 VDDINT28 P18 VDDINT29 V3 VDDINT30 V8 VDDINT31 V12 VDDINT32 V15 VDDINT33 L17 VDDINT34 L18 VDDINT35 F17 VDDIO1 K4 VDDIO2 C4 VDDIO3 G4 VDDIO
A B C D SDRAM 128Mb (1M x 32-bit x 4 Banks) U36 ADDR[1:18] 1 DATA[0:31] ADDR1 25 ADDR2 26 ADDR3 27 ADDR4 60 ADDR5 61 ADDR6 62 ADDR7 63 ADDR8 64 ADDR9 65 ADDR10 66 A2 A3 A4 A5 A6 A7 A8 A9 21 A11 ADDR17 22 ADDR18 23 BA0 BA1 20 MS2_FLAG2_IRQ2 CS 67 SDCKE CKE 68 SDCLK0 CLK 17 SDWE 2 A1 A10 ADDR12 R24 10K 402 DNP A0 24 SDA10 3.
C D SPDIF OUT SPDIF IN LEFT (WHITE) DAC4 DAC4 DAC3 DAC2 DAC1 B ADC A RIGHT (RED) 3.3V IN (P10) OUT (J5) 3.3V OUT (P7) IN (P8) OUT (P9) 1 1 AUDIO OSC AD1835 AUDIO CODEC R33 10K 402 R34 10K 402 R27 33 402 U1 U31 DAIP8_ADC_LRCLK ALRCLK ASDATA 38 DAIP13_DAC_BCLK DBCLK 37 DAIP14_DAC_LRCLK DLRCLK 41 DAIP12_DAC_D1 DSDATA1 42 DAIP11_DAC_D2 DSDATA2 ADCRN DAIP5_ADC_DATA DSDATA4 3.
A B C D 1 1 R67 5.49K 0603 R39 11K 0603 R48 5.49K 0603 C117 100PF 0603 R36 3.32K 0603 R50 11K 0603 OUTLN1 C99 100PF 0603 R49 3.32K 0603 OUTLN2 C116 330PF 0603 DAC1 LEFT 2 C90 DNP 0603 C101 330PF 0603 U9 1 DAC2 LEFT 3 R37 5.49K 0603 C115 680PF 0603 R64 1.65K 0603 AD8606AR SOIC8 R65 604 0603 J5 4X2 CON011 C111 10UF 805 OUTLP1 AOUT1_LEFT R38 2.74K 0603 C89 220PF 0603 AUDIO_VREF_DAC C100 DNP 0603 1 3 R51 5.49K 0603 C102 680PF 0603 R52 1.
A B R75 5.49K 0603 1 R73 11K 0603 C R84 5.49K 0603 C125 100PF 0603 R74 3.32K 0603 D R86 11K 0603 OUTLN3 1 C132 100PF 0603 R85 3.32K 0603 OUTLN4 C123 330PF 0603 C124 DNP 0603 DAC3 LEFT C134 330PF 0603 U11 2 1 DAC4 LEFT 3 R72 5.49K 0603 C122 680PF 0603 R71 1.65K 0603 AD8606AR SOIC8 R69 604 0603 J5 4X2 CON011 C144 10UF 805 OUTLP3 AOUT3_LEFT U12 2 C133 DNP 0603 1 3 R87 5.49K 0603 C135 680PF 0603 R88 1.
A B C D R105 301 0603 VREF_MIC_L AIN_AMP_LEFT P10 RCA_1X2 CON031 FER4 600 603 2 C162 10UF 805 R102 11K 0603 R103 5.49K 0603 R104 5.49K 0603 AIN_LEFT 3 C148 680PF 0603 C166 100PF 0603 1 C149 680PF 0603 1 R122 237 0603 U13 2 AGND 2 1 1 ADCLN AGND AUDIO_VREF_ADC 3 C164 0.
A B C D 3.3V 3.3V 3.3V C173 0.01UF 402 C169 0.1UF 402 1 R140 15K 0603 P8 RCA CON012 1X1 SPDIF COAX INPUT C170 0.1UF 402 4 C2+ 5 C2- C168 0.1UF 402 SPDIF_COAX_IN 1 P1 2 V+ ADM3202 C185 0.22UF 805 2 U32 1 C1+ 3 C1- 1 6 6 V- 2 7 1 DPI10_UART0_RX DAIP18_SPDIF_IN 2 7 12 3 6 DPI11_UART0_RTS 4 5 ON DPI12_UART0_CTS R124 22 402 10 4 R125 10K 0603 8 VCC 7 ROUT 6 NC3 5 GND 8 3 1 RIN2 RIN+ 3 NC1 4 NC2 SW5 1 2 C186 0.22UF 805 DPI9_UART0_TX U2 1 R141 75.
A B C D TP13 VDDINT_SHUNT VDDINT A5V R146 90.9K 0603 JP4 1 JP2 1 U5 ELVIS_SELECT 1 2 ELVIS_TRIGGER_S IDC2X1 IDC2X1 3 IN+ 2 IN8 RG+ 1 RG- R143 0.1 0603 1 DAIP4_ELVIS_TRIG 2 7 V+ 4 VOUT REF U33 2 R145 10K 0603 6 6 SHORTING JUMPER DEFAULT=NOT INSTALLED ACH0+ SHORTING JUMPER DEFAULT=NOT INSTALLED 3 AD820 SOIC8 5 AD623 USOIC8 R142 10K 0603 C192 0.01UF 402 ELVIS Programmable Flag Jumper ELVIS Select Jumper A5V R144 11K 0603 C187 0.1UF 603 C190 0.
A B C D 3.3V R175 10K 402 LABEL "PB1" R179 100 402 5 1 R157 10 0603 U40 SW8 SWT013 SPST-MOMENTARY 3.3V 6 RS_P0 1 74LVC14A SOIC14 C197 1.
A B C D 5V EXPANSION INTERFACE (TYPE A) VDDEXT 3.3V VDDINT 3.3V 5V VDDINT_SHUNT DATA[0:31] 1 1 ADDR[0:23] 3.
A B C D UNREG_IN POWER IN 5V F1 2.5A FUS001 D3 2A DO-214AA 1 FER7 CHOKE_COIL 4 3 1 2 1 C214 1000PF 402 C215 10UF 1210 UNREG_IN VR3 7 IN1 8 IN2 J4 2 5V_B UNREG_IN C216 0.1UF 805 3 7.5V_POWER CON005 2.
I INDEX A AD1835A, CAD and DAC ADC_DATA pin, 2-11 configuration registers, 1-10 master clock (MCLK), 2-5, 2-10 master/slave modes, 1-10, 2-10 setup switch (SW3), 2-10 SPI interface, 2-6 ADSP-21369 processors ADDRx pins, 2-7 async memory controller, 1-8 CLKCFGx pins, 2-3 core clock, 2-8 core frequency, 2-3 core voltage, 2-2 DAIPx/DATAx pins, 2-7 DAIx pins, 1-12, 2-12, 2-17, 2-20, 2-24 DPIx pins, 1-12, 2-7, 2-12 external port, 2-3, 2-8 FLAGx/~IRQx pins, 1-11, 1-12, 2-7, 2-12, 2-14, 2-16 IO voltage, 2-2 peri
INDEX configuration, of this EZ-KIT Lite, 1-4 connectors diagram of locations, 2-20 J1-3 (expansion), 2-3, 2-5, 2-6, 2-7, 2-20 J4 (power), 1-4, 2-22 J5 (audio out RCA), 1-10, 2-22 P10 (audio in RCA), 1-10, 2-22 P1 (RS-232), xi, 2-23 P2 (JTAG), 2-8, 2-25 P3 (DPI header), 2-24 P4 (DAI header), 2-24 P5 (USB), 1-4, 2-24 P7 (headphone out), 1-10, 2-22 P8-9 (SPDIF coax), 2-23 contents, of EZ-KIT Lite package, 1-2 core frequency, 2-3 to CLKIN ratio, 2-10 current limit, 2-7 customer support, xiv D DAI, See digita
INDEX H headphone out jack (P7), xi, 2-22 Help, online, xix master input clock (MCLK), 1-9 ~MS2-0, memory select pins, 1-7 ~MS3, memory select pin, 1-7, 1-12 I N installation, of this EZ-KIT Lite, 1-4 interrupts, configuring push buttons as, 1-11 IO voltage, 2-2 notation conventions, xxii O oscilloscope config switch (SW1), 2-13 J JTAG emulation port, 2-8 header (P2), xii, 2-25 jumpers diagram of locations, 2-17 JP1 (VCO select), 2-17 JP2 (ELVIS select), 2-19 JP3 (voltage select), 2-19 JP4 (ELVIS pr
INDEX S SDRAM chip select pin (FLAG8), 2-6 configuration, 1-7 control signals, 2-7 via external port, 2-3 serial peripheral interconnect (SPI) flash memory, xi, xii, 1-7, 1-8, 2-6 master/slave boot modes, 2-3, 2-9 session startup, 1-4 signal routing units SRU2 (DPI interface), 2-5 SRU (DAI interface), 2-4 spacing headers, 2-24 SPDIF input/output, xii receiver, 1-9 SPI master/slave boot modes, 2-9 SRAM async memory controller, 1-8 configuration, 1-7 via external port, 2-3 stereo IO, xi SW12 (reset) push but
