SHARC Processors ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—3M bits of on-chip SRAM S/PDIF-compatible digital audio receiver/transmitter 8 channels of asynchronous sample rate converters (SRC) 16 PWM outputs configured as four groups of four outputs ROM-based security featur
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 TABLE OF CONTENTS Summary ............................................................... 1 ESD Caution ...................................................... 16 Dedicated Audio Components .................................... 1 Maximum Power Dissipation ................................. 16 General Description ................................................. 3 Absolute Maximum Ratings ...................................
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 GENERAL DESCRIPTION The ADSP-2136x SHARC® processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices, Inc., Super Harvard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SHARC FAMILY CORE ARCHITECTURE Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Data Register File Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 3.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Serial ports operate in four modes: generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms).
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 audio channels in I2S, left-justified sample pair, or right-justified mode. One frame sync cycle indicates one 64-bit left/right pair, but data is sent to the FIFO as 32-bit words (that is, onehalf of a frame at a time). The processor supports 24- and 32-bit I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justified formats.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 100nF 10nF 1nF features. Also available are various EZ-Extenders®, which are daughter cards delivering additional specialized functionality, including audio and video processing. For more information visit www.analog.com and search on “ezkit” or “ezextender”. ADSP-213xx AVDD VDDINT HIGH-Z FERRITE BEAD CHIP EZ-KIT Lite Evaluation Kits AVSS LOCATE ALL COMPONENTS CLOSE TO AVDD AND AVSS PINS Figure 3.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 VisualDSP++. For more information visit www.analog.com and search on “Blackfin software modules” or “SHARC software modules”. Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PIN FUNCTION DESCRIPTIONS The processor’s pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS and TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for the following: DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI, and AD15–0.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 6. Pin Descriptions (Continued) Pin SPICLK Type I/O (pu) State During and After Reset Three-state with pull-up enabled, driven high in SPImaster boot mode Function Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master can transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 6. Pin Descriptions (Continued) Pin BOOT_CFG1–0 Type I State During and After Reset Input only Function Boot Configuration Select. This pin is used to select the boot mode for the processor. The BOOT_CFG pins must be valid before reset is asserted. For a description of the boot mode, refer to Table 5, Boot Mode Selection. RESETOUT O Output only Reset Out. Drives out the core reset signal to an external device.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPECIFICATIONS Specifications are subject to change without notice. OPERATING CONDITIONS K Grade B Grade Y Grade Parameter Description Min Nom Max Min Nom Max Min Nom Max Unit VDDINT Internal (Core) Supply Voltage 1.14 1.2 1.26 1.14 1.2 1.26 0.95 1.0 1.05 V AVDD Analog (PLL) Supply Voltage 1.14 1.2 1.26 1.14 1.2 1.26 0.95 1.0 1.05 V VDDEXT External (I/O) Supply Voltage 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ELECTRICAL CHARACTERISTICS Parameter Description Test Conditions Min Max Unit VOH1 High Level Output Voltage @ VDDEXT = Min, IOH = –1.0 mA2 2.4 VOL1 Low Level Output Voltage @ VDDEXT = Min, IOL = 1.0 mA2 0.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PACKAGE INFORMATION The information presented in Figure 4 provides details about the package branding for the ADSP-2136x processor. For a complete listing of product availability, see Ordering Guide on Page 56. Table 8.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 • The product of CLKIN and PLLM must never exceed 1/2 fVCO (max) in Table 11 if the input divider is not enabled (INDIV = 0). fINPUT = CLKIN ÷ 2 when the input divider is enabled Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 9. All of the timing specifications for the ADSP-2136x peripherals are defined in relation to tPCLK.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Power-Up Sequencing three-state leakage current pull-up, pull-down, may be observed on any pin, even if that is an input only (for example the RESET pin) until the VDDINT rail has powered up. The timing requirements for processor startup are given in Table 10. Note that during power-up, when the VDDINT power supply comes up after VDDEXT, a leakage current of the order of Table 10.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Clock Input Table 11. Clock Input Parameter Min Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK4 CCLK Period VCO Frequency tVCO5 tCKJ6, 7 CLKIN Jitter Tolerance 200 MHz1 Max 303 12.5 12.5 Min 100 18 7.5 7.5 3 10 600 +250 5.0 200 –250 333 MHz2 Max Unit 100 ns ns ns ns ns MHz ps 3 10 800 +250 3.0 200 –250 1 Applies to all 200 MHz models.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Reset Table 12. Reset Parameter Timing Requirements tWRST1 tSRST 1 RESET Pulse Width Low RESET Setup Before CLKIN Low Min Unit 4 × tCK 8 ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 9.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP pin). Table 14. Core Timer Parameter Switching Characteristic tWCTIM TMREXP Pulse Width Min Unit 2 × tPCLK – 1 ns tWCTIM FLAG3 (TMREXP) Figure 11. Core Timer Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specification provided below are valid at the DAI_P20–1 pins. Table 16.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Flags The timing specifications provided below apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface (SPI). See Table 6 on Page 11 for more information on flag use. Table 19. Flags Parameter Timing Requirement tFIPW FLAG3–0 IN Pulse Width Switching Characteristic FLAG3–0 OUT Pulse Width tFOPW FLAG INPUTS tFIPW FLAG OUTPUTS tFOPW Figure 16. Flags Rev.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the processor is accessing external memory space. Table 20. 8-Bit Memory Read Cycle K and B Grade Parameter Min Max Timing Requirements tDRS AD7–0 Data Setup Before RD High 3.3 tDRH AD7–0 Data Hold After RD High 0 tDAD AD15–8 Address to AD7–0 Data Valid D + tPCLK – 5.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 21. 16-Bit Memory Read Cycle K and B Grade Max Parameter Min Timing Requirements tDRS AD15–0 Data Setup Before RD High 3.3 tDRH AD15–0 Data Hold After RD High 0 Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 tADAS1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tALERW ALE Deasserted to Read Asserted 2 × tPCLK – 3.8 tRRH2 Delay Between RD Rising Edge to Next Falling H + tPCLK – 1.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the processor is accessing external memory space. Table 22. 8-Bit Memory Write Cycle K and B Grade Parameter Min Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 tADAS1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.8 tALERW ALE Deasserted to Write Asserted 2 × tPCLK – 3.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 23. 16-Bit Memory Write Cycle K and B Grade Parameter Min Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 tADAS1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tALERW ALE Deasserted to Write Asserted 2 × tPCLK – 3.8 tRWALE Write Deasserted to ALE Asserted H + 0.5 tWRH2 Delay Between WR Rising Edge to Next WR Falling Edge F + H + tPCLK – 2.3 1 tADAH AD15–0 Address Hold After ALE Deasserted tPCLK – 2.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync (FS) delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SCLK) width. Serial port signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 24.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK) DAI_P20–1 (SCLK) tDFSI tDFSE tSFSI tHOFSI tHFSI DAI_P20–1 (FS) tSFSE tHFSE tSDRE tHDRE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tS
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 26. Serial Ports—External Late Frame Sync Parameter Min Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit Frame Sync or External Receive FS with MCE = 1, MFD = 0 tDDTENFS1 Data Enable for MCE = 1, MFD = 0 0.5 1 K and B Grade Max Y Grade 9 The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as serial mode, and MCE = 1, MFD = 0.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 27. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK tDDTTE1 Data Disable from External Transmit SCLK 1 tDDTIN Data Enable from Internal Transmit SCLK 1 Min K and B Grade Max Y Grade Unit 8.5 ns ns ns 2 7 –1 Referenced to drive edge.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Input Data Port (IDP) The timing requirements for the IDP are given in Table 28. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 28.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 29. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, refer to the ADSP-2136x SHARC Processor Hardware Reference, “Input Data Port” chapter. Note that the most significant 16 bits of external 20-bit PDAP data can be provided through either the parallel port AD15–0 pins or the DAI_P20–5 pins.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Pulse-Width Modulation Generators Table 30. PWM Timing1 Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period 1 Min Max Unit tPCLK – 2 2 × tPCLK – 1.5 (216 – 2) × tPCLK (216 – 1) × tPCLK ns ns Note that the PWM output signals are shared on the parallel port bus (AD15-0 pins). tPWMW PWM OUTPUTS tPWMP Figure 26.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SAMPLE EDGE DAI_P20–1 (SCLK) tSRCCLK tSRCCLKW tSRCSFS tSRCHFS DAI_P20–1 (FS) tSRCSD tSRCHD DAI_P20–1 (SDATA) Figure 27. SRC Serial Input Port Timing Rev.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold time and delay specification with regard to serial clock. Note that the serial clock rising edge is the sampling edge and the falling edge is the drive edge. Table 32.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 29 shows the right-justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Figure 30 shows the default I2S-justified mode. The frame sync is low for the left channel and high for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition but with a delay. Table 34.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 36. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 36.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. This feature is not available on the ADSP-21363 processors. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 38.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Master The processor contains two SPI ports. The primary has dedicated pins and the secondary is available through the DAI. The timing provided in Table 39 and Table 40 applies to both ports. Table 39.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Slave Table 40.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPIDS (INPUT) tSPICHS SPICLK (CP = 0, CP = 1) (INPUT) tSPICLS tSPICLKS tHDS tSDPPW tSDSCO tDSOE tDSDHI tDDSPIDS tDDSPIDS tHDSPIDS MISO (OUTPUT) tSSPIDS tHSPIDS CPHASE = 1 MOSI (INPUT) tHDSPIDS MISO (OUTPUT) tDSOV tHSPIDS CPHASE = 0 tSSPIDS MOSI (INPUT) Figure 35. SPI Slave Timing Rev.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 JTAG Test Access Port and Emulation Table 41.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 OUTPUT DRIVE CURRENTS CAPACITIVE LOADING Figure 37 shows typical I-V characteristics for the output drivers of the processor. The curves represent the current drive capability of the output drivers as a function of output voltage. Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 38). Figure 42 shows graphically how output delays and holds vary with load capacitance.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Values of θJC are provided for package comparison and PCB design considerations when an exposed pad is required. Note that the thermal characteristics values provided in Table 42 through Table 44 are modeled values. 10 OUTPUT DELAY OR HOLD (ns) 8 y = 0.0488x - 1.5923 6 Table 42. Thermal Characteristics for BGA (No Thermal vias in PCB) 4 Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT 2 0 -2 -4 0 50 100 150 200 LOAD CAPACITANCE (pF) Figure 42.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 144-LEAD LQFP_EP PIN CONFIGURATIONS The following table shows the processor’s pin names and, when applicable, their default function after reset in parentheses. Table 45. LQFP_EP Pin Assignments Pin Name VDDINT CLK_CFG0 CLK_CFG1 BOOT_CFG0 BOOT_CFG1 GND VDDEXT GND VDDINT GND VDDINT GND VDDINT GND FLAG0 FLAG1 AD7 GND VDDINT GND VDDEXT GND VDDINT AD6 AD5 AD4 VDDINT GND AD3 AD2 VDDEXT GND AD1 AD0 WR VDDINT Pin No.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Figure 43 shows the top view of the 144-lead LQFP_EP pin configuration. Figure 44 shows the bottom view of the 144-lead LQFP_EP lead configuration. LEAD 144 LEAD 109 LEAD 1 LEAD 108 LEAD 1 INDICATOR ADSP-2136x 144-LEAD LQFP_EP TOP VIEW LEAD 36 LEAD 73 LEAD 37 LEAD 72 Figure 43.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 136-BALL BGA PIN CONFIGURATIONS The following table shows the processor’s ball names and, when applicable, their default function after reset in parentheses. Table 46. BGA Pin Assignments Ball Name CLK_CFG0 XTAL TMS TCK TDI RESETOUT TDO EMU MOSI MISO SPIDS VDDINT GND GND VDDINT GND GND GND GND GND GND GND GND FLAG3 Ball No.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 46. BGA Pin Assignments (Continued) Ball Name AD5 AD4 GND GND GND GND GND GND VDDINT DAI_P16 (SD4B) AD15 ALE RD VDDINT VDDEXT AD8 VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT GND DAI_P10 (SD2B) Ball No.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A A B B C C D D E E F F G G H H J J K K L L M M N N P P KEY KEY VDDINT VDDEXT GND AVSS AVDD VDDINT GND AVDD I/O SIGNALS VDDEXT AVSS I/O SIGNALS Figure 45. BGA Pin Assignments (Bottom View, Summary) Rev. J | Figure 46.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PACKAGE DIMENSIONS The processor is available in 136-ball BGA and 144-lead exposed pad (LQFP_EP) packages. 22.20 22.00 SQ 21.80 1.60 MAX 0.75 0.60 0.45 20.20 20.00 SQ 19.80 109 144 109 108 1 SEATING PLANE 144 108 1 PIN 1 EXPOSED* PAD 1.45 1.40 1.35 0.20 0.15 0.09 0.15 0.10 0.05 0.08 COPLANARITY 7° 3.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 A1 BALL CORNER 12.10 12.00 SQ 11.90 14 13 12 11 10 9 8 7 6 5 4 3 2 A1 BALL CORNER 1 A B C D E F G H J K L M N P 10.40 BSC SQ 0.80 BSC BOTTOM VIEW TOP VIEW DETAIL A DETAIL A 0.25 MIN 1.70 MAX *0.50 SEATING PLANE 0.45 0.40 BALL DIAMETER 1.31 1.21 1.10 COPLANARITY 0.12 *COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1 WITH EXCEPTION TO BALL DIAMETER. Figure 48.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 AUTOMOTIVE PRODUCTS Some ADSP-2136x models are available for automotive applications with controlled manufacturing. Note that these special models may have specifications that differ from the general release models. The automotive grade products shown in Table 48 are available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information.
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ORDERING GUIDE Model1 ADSP-21363KBC-1AA ADSP-21363KBCZ-1AA ADSP-21363KSWZ-1AA ADSP-21363BBC-1AA ADSP-21363BBCZ-1AA ADSP-21363BSWZ-1AA ADSP-21363YSWZ-2AA ADSP-21364KBCZ-1AA ADSP-21364KSWZ-1AA ADSP-21364BBCZ-1AA ADSP-21364BSWZ-1AA ADSP-21364YSWZ-2AA ADSP-21366KBCZ-1AR ADSP-21366KBCZ-1AA ADSP-21366KSWZ-1AA Notes 3 3, 4, 5 3, 4 3, 4 Temperature Range2 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +105°C 0°C
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06359-0-7/13(J) Rev.
