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SHARC

Embedded Processor

ADSP-21261/ADSP-21262/ADSP-21266

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SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Code compatibility—at assembly level, uses the same

instruction set as other SHARC DSPs

Processes high performance audio while enabling low

system costs

Audio decoders and postprocessor algorithms support

nonvolatile memory that can be configured to contain a

combination of PCM 96 kHz, Dolby Digital, Dolby Digital

Surround EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1, DTS

96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-

PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and

DTS Neo:6

Various multichannel surround sound decoders are con-

tained in ROM. For configurations of decoder algorithms,

see Table 3 on Page 4.

Single-instruction multiple-data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point/32-bit fixed-point/

40-bit extended precision floating-point computational

units, each with a multiplier, ALU, shifter, and register file

High bandwidth I/O—a parallel port, an SPI port, 6 serial

ports, a Digital application interface (DAI), and JTAG

DAI incorporates two precision clock generators (PCGs), an

input data port (IDP) that includes a parallel data acquisi-

tion port (PDAP), and 3 programmable timers, all under

software control by the signal routing unit (SRU)

On-chip memory—up to 2M bits on-chip SRAM and a dedi-

cated 4M bits on-chip mask-programmable ROM

The ADSP-2126x processors are available with a 150 MHz or a

200 MHz core instruction rate. For complete ordering

information, see Ordering Guide on Page 45.

Figure 1. Functional Block Diagram

ADDR

DATA

PX REGISTER

JTAG TEST & EMULATION

SE RIAL PORTS (6 )

INPUT

DATA PORTS (8)

PARALLEL DATA

ACQUIS ITION PORT

PE RIPHERAL

TI ME R S ( 3 )

SI GNAL

RO U TI NG

UNIT

PRECISI ON CLOCK

GENERATORS (2)

DIGITAL AUDIO INTERFACE

ADDRESS/

DATA BUS / GPIO

CONTROL/GPIO

PARALLEL

PORT

IOP

REGISTERS

(MEMORY MAPPED)

CONTROL,

STATUS,

DATA BUFFERS

SP I PO RT ( 1)

DMA CONTROLLER

22 CHANNELS

GPIO FLAG S/

IRQ /TIMEXP

PROCESSING

ELEMENT

(PEY)

PROCES SING

ELEM ENT

(PEX)

TIMER

INSTRUCTION

CACHE

32 ⴛ 48-BIT

DAG1

8 ⴛ 4 ⴛ 32

DAG2

8 ⴛ 4 ⴛ 32

32PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

CORE PROCESS OR

PROGRAM

SEQ UE NCER

ADDR DATA

SRAM

1M BIT ROM

2M BIT

DUAL PORTED MEMORY

BLOCK 0

SRAM

1M BIT ROM

2M BIT

DUAL PORTED MEMORY

BL O CK 1

IOD

(32)

IOA

(19)

I/O PROCESSOR

Summary of content (48 pages)

PAGE 1
SHARC Embedded Processor ADSP-21261/ADSP-21262/ADSP-21266 SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Processes high performance audio while enabling low system costs Audio decoders and postprocessor algorithms support nonvolatile memory that can be configured to contain a combination of PCM 96 kHz, Dolby Digital, Dolby Digital Surround EX, DTS-ES Discre
PAGE 2
ADSP-21261/ADSP-21262/ADSP-21266 TABLE OF CONTENTS Summary ............................................................... 1 ESD Caution ...................................................... 15 General Description ................................................. 3 Maximum Power Dissipation ................................. 15 Family Core Architecture ........................................ 3 Absolute Maximum Ratings ................................... 15 Memory and I/O Interface Features ..........
PAGE 3
ADSP-21261/ADSP-21262/ADSP-21266 GENERAL DESCRIPTION The ADSP-21261/ADSP-21262/ADSP-21266 SHARC® DSPs are members of the SIMD SHARC family of DSPs featuring Analog Devices, Inc., Super Harvard Architecture. The ADSP-2126x is source code compatible with the ADSP-21160 and ADSP-21161 DSPs as well as with first generation ADSP2106x SHARC processors in SISD (single-instruction, singledata) mode.
PAGE 4
ADSP-21261/ADSP-21262/ADSP-21266 elements, but each processing element operates on different data. This architecture is efficient at executing math intensive audio algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements.
PAGE 5
ADSP-21261/ADSP-21262/ADSP-21266 The ADSP-2126x’s SRAM can be configured as a maximum of 64K words of 32-bit data, 128K words of 16-bit data, 42K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that can be stored on-chip.
PAGE 6
ADSP-21261/ADSP-21262/ADSP-21266 Table 5.
PAGE 7
ADSP-21261/ADSP-21262/ADSP-21266 Serial Peripheral (Compatible) Interface The serial peripheral interface is an industry-standard synchronous serial link, enabling the ADSP-2126x SPI-compatible port to communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes.
PAGE 8
ADSP-21261/ADSP-21262/ADSP-21266 TARGET BOARD JTAG EMULATOR CONNECTOR Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-2126x processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks.
PAGE 9
ADSP-21261/ADSP-21262/ADSP-21266 breakpoints, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports connection of the DSP’s JTAG port to the emulator.
PAGE 10
ADSP-21261/ADSP-21262/ADSP-21266 PIN FUNCTION DESCRIPTIONS The ADSP-2126x pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST).
PAGE 11
ADSP-21261/ADSP-21262/ADSP-21266 Table 6. Pin Descriptions (Continued) State During and After Reset Three-state with pull-up enabled, driven high in SPImaster boot mode Pin SPICLK Type I/O SPIDS I Input only MOSI I/O (O/D) Three-state with pull-up enabled, driven low in SPImaster boot mode MISO I/O (O/D) Three-state with pull-up enabled BOOT_CFG1–0 I Input only CLKIN I Input only XTAL O Output only2 Function Serial Peripheral Interface Clock Signal.
PAGE 12
ADSP-21261/ADSP-21262/ADSP-21266 Table 6. Pin Descriptions (Continued) Pin CLK_CFG1–0 Type I State During and After Reset Input only RESETOUT RESET O I/A Output only Input only TCK I Input only3 TMS I/S TDI I/S TDO TRST O I/A Three-state with pull-up enabled Three-state with pull-up enabled Three-state4 Three-state with pull-up enabled EMU O (O/D) VDDINT P VDDEXT P AVDD P AVSS GND G G Three-state with pull-up enabled Function Core/CLKIN Ratio Control.
PAGE 13
ADSP-21261/ADSP-21262/ADSP-21266 ADDRESS DATA PINS AS FLAGS ADDRESS DATA MODES To use these pins as flags (FLAG15–0), set (= 1) Bit 20 of the SYSCTL register and disable the parallel port. Table 10 shows the functionality of the AD pins for 8-bit and 16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23–A8 when asserted, followed by address bits A7–A0 and data bits D7–D0 when deasserted.
PAGE 14
ADSP-21261/ADSP-21262/ADSP-21266 PRODUCT SPECIFICATIONS OPERATING CONDITIONS Parameter1 VDDINT AVDD VDDEXT VIH VIL VIH_CLKIN VIL_CLKIN TAMB K Grade TAMB B Grade Description Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage2 @ VDDEXT = Max Low Level Input Voltage2 @ VDDEXT = Min High Level Input Voltage3 @ VDDEXT = Max Low Level Input Voltage @ VDDEXT = Min Ambient Operating Temperature4, 5 Ambient Operating Temperature4, 5 Min 1.14 1.14 3.
PAGE 15
ADSP-21261/ADSP-21262/ADSP-21266 PACKAGE INFORMATION The information presented in Figure 3 provides details about the package branding for the ADSP-21266 processors. For a complete listing of product availability, see Ordering Guide on Page 45. this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 12.
PAGE 16
ADSP-21261/ADSP-21262/ADSP-21266 Table 13. CLKOUT and CCLK Clock Generation Operation Voltage Controlled Oscillator In application designs, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds fVCO specified in Table 16. Timing Requirements CLKIN CCLK • The product of CLKIN and PLLM must never exceed 1/2 of fVCO (max) in Table 16 if the input divider is not enabled (INDIV = 0).
PAGE 17
ADSP-21261/ADSP-21262/ADSP-21266 Power-Up Sequencing The timing requirements for DSP startup are given in Table 15 and Figure 5. Note that during power-up, a leakage current of approximately 200 A may be observed on the RESET pin. This leakage current results from the weak internal pull-up resistor on this pin being enabled during power-up. Table 15.
PAGE 18
ADSP-21261/ADSP-21262/ADSP-21266 Clock Input See Table 16 and Figure 6. Table 16. Clock Input Parameter 150 MHz1 Max Min Timing Requirements tCK CLKIN Period CLKIN Width Low tCKL tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) 5 fvco VCO Frequency tCCLK CCLK Period6 203 7.53 7.53 1604 804 804 3 800 10 200 6.66 1 Applies to all 150 MHz models. See Ordering Guide on Page 45. Applies to all 200 MHz models. See Ordering Guide on Page 45.
PAGE 19
ADSP-21261/ADSP-21262/ADSP-21266 Reset See Table 17 and Figure 8. Table 17. Reset Parameter Timing Requirements tWRST RESET Pulse Width Low1 tSRST RESET Setup Before CLKIN Low 1 Min Max Unit 4  tCK 8 ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 8.
PAGE 20
ADSP-21261/ADSP-21262/ADSP-21266 Core Timer The timing specification in Table 19 and Figure 10 applies to FLAG3 when it is configured as the core timer (CTIMER). Table 19. Core Timer Parameter Switching Characteristics tWCTIM CTIMER Pulse Width Min Max 4 × tCCLK – 1 Unit ns tWCTIM FLAG3 (CTIMER) Figure 10. Core Timer Timer PWM_OUT Cycle Timing The timing specification in Table 20 and Figure 11 applies to Timer in PWM_OUT (pulse-width modulation) mode.
PAGE 21
ADSP-21261/ADSP-21262/ADSP-21266 Timer WDTH_CAP Timing The timing specification in Table 21 and Figure 12 applies to Timer in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 21. Timer Width Capture Timing Parameter Timing Requirements tPWI Timer Pulse Width Min Max Unit 2 × tCCLK 2(231 – 1) × tCCLK ns tPWI TIMER CAPTURE INPUTS Figure 12.
PAGE 22
ADSP-21261/ADSP-21262/ADSP-21266 Precision Clock Generator (Direct Pin Routing) The timing in Table 23 and Figure 14 is valid only when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers), there is no timing data available.
PAGE 23
ADSP-21261/ADSP-21262/ADSP-21266 Flags The timing specifications in Table 24 and Figure 15 apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface. See Table 6 on Page 10 for more information on flag use. Table 24. Flags Parameter Timing Requirements tFIPW FLAG3–0 IN Pulse Width Min Switching Characteristics tFOPW FLAG3–0 OUT Pulse Width Unit 2 × tCCLK + 3 ns 2 × tCCLK – 1 ns FLAG INPUTS tFIPW FLAG OUTPUTS tFOPW Figure 15. Flags Rev.
PAGE 24
ADSP-21261/ADSP-21262/ADSP-21266 Memory Read—Parallel Port The specifications in Table 25, Table 26, Figure 16, and Figure 17 are for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-2126x is accessing external memory space. Table 25. 8-Bit Memory Read Cycle Parameter Timing Requirements tDRS Address/Data 7–0 Setup Before RD High tDRH Address/Data 7–0 Hold After RD High Address 15–8 to Data Valid tDAD Min 2 × tCCLK – 2 1 × tCCLK – 0.5 2.5 × tCCLK – 2.0 0.5 × tCCLK – 0.
PAGE 25
ADSP-21261/ADSP-21262/ADSP-21266 Table 26.
PAGE 26
ADSP-21261/ADSP-21262/ADSP-21266 Memory Write—Parallel Port Use the specifications in Table 27, Table 28, Figure 18, and Figure 19 for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-2126x is accessing external memory space. Table 27.
PAGE 27
ADSP-21261/ADSP-21262/ADSP-21266 Table 28.
PAGE 28
ADSP-21261/ADSP-21262/ADSP-21266 Serial Ports To determine whether communication is possible between two devices at a given clock speed, the specifications in Table 29, Table 30, Table 31, Table 32, Figure 20, Figure 21, and Figure 22 must be confirmed: 1) frame sync delay and frame sync setup and hold; 2) data delay and data setup and hold; and 3) SCLK width. Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P20–1 pins using the SRU.
PAGE 29
ADSP-21261/ADSP-21262/ADSP-21266 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK) DAI_P20–1 (SCLK) tDFSI tDFSE tSFSI tHOFSI tHFSI DAI_P20–1 (FS) tSFSE tHFSE tSDRE tHDRE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK)
PAGE 30
ADSP-21261/ADSP-21262/ADSP-21266 Table 31. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN Data Enable from External Transmit SCLK1 Data Disable from External Transmit SCLK1 tDDTTE tDDTIN Data Enable from Internal Transmit SCLK1 1 Min Unit 7 ns ns ns 2 –1 Referenced to drive edge. DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, EXT) tDDTEN tDDTTE DAI_P20–1 (DATA CHANNEL A/B) DRIVE EDGE DAI_P20–1 (SCLK, INT) tDDTIN DAI_P20–1 (DATA CHANNEL A/B) Figure 21.
PAGE 31
ADSP-21261/ADSP-21262/ADSP-21266 Table 32. Serial Ports—External Late Frame Sync Parameter Min Switching Characteristics tDDTLFSE Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 01 tDDTENFS Data Enable for MCE = 1, MFD = 01 0.5 1 The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.
PAGE 32
ADSP-21261/ADSP-21262/ADSP-21266 Input Data Port (IDP) The timing requirements for the IDP are given in Table 33 and Figure 23. IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 33.
PAGE 33
ADSP-21261/ADSP-21262/ADSP-21266 Note that the most significant 16 bits of external PDAP data can be provided through either the parallel port AD15–0 or the DAI_P20–5 pins. The remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DAI_P20–1 pins or at the AD15–0 pins. Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 34 and Figure 24. PDAP is the parallel mode operation of Channel 0 of the IDP.
PAGE 34
ADSP-21261/ADSP-21262/ADSP-21266 SPI Interface Protocol—Master Table 35.
PAGE 35
ADSP-21261/ADSP-21262/ADSP-21266 SPI Interface Protocol—Slave Table 36.
PAGE 36
ADSP-21261/ADSP-21262/ADSP-21266 JTAG Test Access Port and Emulation Table 37.
PAGE 37
ADSP-21261/ADSP-21262/ADSP-21266 OUTPUT DRIVE CURRENTS CAPACITIVE LOADING Figure 28 shows typical I-V characteristics for the output drivers of the ADSP-2126x. The curves represent the current drive capability of the output drivers as a function of output voltage. Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 29).
PAGE 38
ADSP-21261/ADSP-21262/ADSP-21266 Values of JA are provided for package comparison and PCB design considerations (JMA indicates moving air). JA can be used for a first order approximation of TJ by the equation 10 OUTPUT DELAY OR HOLD (ns) 8 T J = T A +   JA  P D  y = 0.0488x – 1.5923 6 4 where: 2 TA = ambient temperature C) 0 Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. –2 Table 38.
PAGE 39
ADSP-21261/ADSP-21262/ADSP-21266 144-LEAD LQFP PIN CONFIGURATIONS Table 40 shows the ADSP-2126x’s pin names and their default function after reset (in parentheses). Table 40. 144-Lead LQFP Pin Assignments Pin Name VDDINT CLK_CFG0 CLK_CFG1 BOOT_CFG0 BOOT_CFG1 GND VDDEXT GND VDDINT GND VDDINT GND VDDINT GND FLAG0 FLAG1 AD7 GND VDDINT GND VDDEXT GND VDDINT AD6 AD5 AD4 VDDINT GND AD3 AD2 VDDEXT GND AD1 AD0 WR VDDINT LQFP Pin No.
PAGE 40
ADSP-21261/ADSP-21262/ADSP-21266 136-BALL BGA PIN CONFIGURATIONS Table 41 shows the ADSP-2126x’s pin names and their default function after reset (in parentheses). Figure 34 on Page 42 shows the BGA package pin assignments. Table 41. 136-Ball BGA Pin Assignments Pin Name CLK_CFG0 XTAL TMS TCK TDI RESETOUT TDO EMU MOSI MISO SPIDS VDDINT GND GND VDDINT GND GND GND GND GND GND GND GND FLAG3 BGA Pin No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 E01 E02 E04 E05 E06 E09 E10 E11 E13 E14 BGA Pin No.
PAGE 41
ADSP-21261/ADSP-21262/ADSP-21266 Table 41. 136-Ball BGA Pin Assignments (Continued) Pin Name AD5 AD4 GND GND GND GND GND GND VDDINT DAI_P16 (SD4B) AD15 ALE RD VDDINT VDDEXT AD8 VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT GND DAI_P10 (SD2B) BGA Pin No. J01 J02 J04 J05 J06 J09 J10 J11 J13 J14 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 BGA Pin No.
PAGE 42
ADSP-21261/ADSP-21262/ADSP-21266 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P KEY VDDINT GND AVDD VDDEXT AVSS I/O SIGNALS * USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary) Rev.
PAGE 43
ADSP-21261/ADSP-21262/ADSP-21266 OUTLINE DIMENSIONS The ADSP-2126x is available in a 144-lead LQFP package and a 136-ball BGA package shown in Figure 35 and Figure 36. 0.75 0.60 0.45 22.20 22.00 SQ 21.80 1.60 MAX 109 144 108 1 PIN 1 20.20 20.00 SQ 19.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 73 36 0.08 COPLANARITY 72 37 VIEW A VIEW A ROTATED 90° CCW 0.50 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BFB Figure 35.
PAGE 44
ADSP-21261/ADSP-21262/ADSP-21266 A1 CORNER INDEX AREA 12.10 12.00 SQ 11.90 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BALL A1 INDICATOR 10.40 BSC SQ TOP VIEW BOTTOM VIEW A B C D E F G H J K L M N P 0.80 BSC DETAIL A 1.70 MAX 1.31 1.21 1.10 DETAIL A 0.25 MIN *0.50 0.45 0.40 BALL DIAMETER 0.12 MAX COPLANARITY SEATING PLANE *COMPLIANT WITH JEDEC STANDARDS MO-205-AE WITH EXCEPTION TO BALL DIAMETER. Figure 36.
PAGE 45
ADSP-21261/ADSP-21262/ADSP-21266 AUTOMOTIVE PRODUCTS The ADSP-21261W and ADSP-21262W are available for automotive applications with controlled manufacturing. Note that these special models may have specifications that differ from the general release models. Contact your local ADI account repre- sentative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS compliant.
PAGE 46
ADSP-21261/ADSP-21262/ADSP-21266 Rev.
PAGE 47
ADSP-21261/ADSP-21262/ADSP-21266 Rev.