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SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC

Embedded Processor

ADSP-21261

Rev. 0

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

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SUMMARY

High performance 32-bit/40-bit floating-point processor

Code compatibility—at assembly level, uses the same

instruction set as other SHARC DSPs

Single-instruction multiple-data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point/32-bit fixed-point/

40-bit extended precision floating-point computational

units, each with a multiplier, ALU, shifter, and register file

High bandwidth I/O—a parallel port, an SPI

port, four serial

ports, a digital applications interface (DAI), and JTAG

DAI incorporates two precision clock generators (PCGs), an

input data port (IDP) that includes a parallel data acquisi-

tion port (PDAP), and three programmable timers, all

under software control by the signal routing unit (SRU)

On-chip memory—1M bit of on-chip SRAM and a dedicated

3M bit of on-chip mask-programmable ROM

The ADSP-21261 is available in commercial and industrial

temperature grades. For complete ordering information,

see Ordering Guide on Page 44.

KEY FEATURES

Serial ports offer left-justified sample-pair and I

S support

via 12 programmable and simultaneous receive or trans-

mit pins, which support up to 24 transmit or 24 receive I

channels of audio when all four serial ports (SPORTs) are

enabled or six full duplex TDM streams of up to 128

channels per frame

At 150 MHz (6.67 ns) core instruction rate, the ADSP-21261

operates at 900 MFLOPS peak/600 MFLOPS sustained per-

formance whether operating on fixed- or floating-point

data

300 MMACS sustained performance at 150 MHz

Super Harvard Architecture—three independent buses for

dual data fetch, instruction fetch, and nonintrusive, zero-

overhead I/O

Transfers between memory and core at up to four 32-bit

floating- or fixed-point words per cycle, sustained

1.8G byte/s bandwidth at 150 MHz core instruction rate

and 900M byte/s is available via DMA

Figure 1. Functional Block Diagram

ADDR

DATA

PX REGISTER

JTAG TES T & EM U LATION

SE RIAL PORTS (4 )

INPUT

DATA PORTS (8 )

PARALLEL DATA

ACQUIS ITION PORT

TIMERS ( 3)

SI GNAL

RO UTI NG

UNI T

PRECISI ON CLOCK

GENERATORS (2)

DIGITAL APPLICATIONS INTERFACE

ADDRES S/

DATA BUS/GPIO

CONTROL/GPIO

P ARALLEL

PORT

IOP

REGISTERS

(MEMORY MAPPED)

CO NTROL,

STATUS,

DATA BUFFERS

SP I PO RT (1)

DMA CO N TROLLER

18 CHANNE LS

GPIO FLA GS/

IRQ /TIM EXP

PROCESSING

ELEMENT

(PE Y)

PROCES SING

ELEM ENT

(PEX)

TIMER

INSTRUCTION

CACHE

32 ⴛ 48-BIT

DAG1

8 ⴛ 4 ⴛ 32

DAG2

8 ⴛ 4 ⴛ 32

PM ADDRE SS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

CORE PROCESS OR

PROGRAM

SEQ UE NCER

ADDR DATA

SRAM

0.5M BIT

RO M

1.5 M BIT

DUAL POR TED MEMORY

BLOCK 0

DUAL PORTED MEMORY

BLOCK 1

IOD

(32)

IOA

(18)

I/O PROCESSOR

ROM

1. 5M BIT

SRAM

0. 5M BIT

Summary of content (44 pages)

PAGE 1
SHARC® Embedded Processor ADSP-21261 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, four serial ports,
PAGE 2
ADSP-21261 ADDITIONAL KEY FEATURES 1M bit on-chip dual-ported SRAM (0.5M bit block 0, 0.5M bit block 1) for simultaneous access by core processor and DMA 3M bit on-chip dual-ported mask-programmable ROM (1.5M bit in block 0 and 1.
PAGE 3
ADSP-21261 TABLE OF CONTENTS General Description ................................................. 4 Reset ............................................................. 20 ADSP-21261 Family Core Architecture ...................... 4 Interrupts ....................................................... 20 SIMD Computational Engine ............................... 4 Core Timer ..................................................... 20 Independent, Parallel Computation Units ................
PAGE 4
ADSP-21261 GENERAL DESCRIPTION The ADSP-21261 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices Super Harvard Architecture. The ADSP-21261 is source code compatible with the ADSP-2126x, ADSP-21160, and ADSP-21161 DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode.
PAGE 5
ADSP-21261 ADS P-21261 CLKOUT CLKI N XTAL CLOCK 2 2 3 ADDR BOOTCFG1– 0 DATA FLAG 3– 1 RD OE WR WE FLAG0 CS PARALLE L PO RT RAM, ROM BOOT ROM I/O DEVICE DATA SRU ADDRESS DAI_ P1 DAI_P 2 DAI_P 3 SCLK0 SFS0 DAC (OP TIONAL) CLK FS S DAT LATCH AD15 –0 CONTROL ADC (OPTI ONAL) CLK FS S DAT ALE CLK_ CFG 1– 0 SD0A SD0B DAI_ P1 8 DAI_ P19 DAI_P 20 S PORT0 SP ORT1 SPO RT2 S PORT3 CLK FS DAI RESE T PCG A P CGB J TAG 6 Figure 2.
PAGE 6
ADSP-21261 Flexible Instruction Set Digital Applications Interface (DAI) The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the ADSP-21261 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction.
PAGE 7
ADSP-21261 INTERNAL MEMORY SPACE LONG WORD ADDRESSING NORMAL WORD ADDRESSING SHORT WORD ADDRESSING IOP REGISTERS 0x0000 0000–0x0003 FFFF IOP REGISTERS 0x0000 0000–0x0003 FFFF IOP REGISTERS 0x0000 0000–0x0003 FFFF BLOCK 0 SRAM (0.5M B IT) 0x0004 0000–0x0004 1FFF BLOCK 0 SRAM ( 0.5M BIT) 0x0008 0000–0x0008 3FFF B LOCK 0 SRAM (0.5M BIT) 0x0010 0000–0x0010 7FFF RESERVED 0x0004 2000–0x0005 7FFF RESERVED 0x0008 4000 - 0x000A FFFF R ESERVED 0x0010 8000–0x0015 FFFF BLOCK 0 R OM (1.
PAGE 8
ADSP-21261 DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE (address latch enable) pins are the control pins for the parallel port. in Figure 4 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip.
PAGE 9
ADSP-21261 complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program.
PAGE 10
ADSP-21261 EVALUATION KIT ADDITIONAL INFORMATION ®† Analog Devices offers a range of EZ-KIT Lite evaluation platforms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker.
PAGE 11
ADSP-21261 PIN FUNCTION DESCRIPTIONS ADSP-21261 pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for the following: • DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI, and AD15–0 (NOTE: These pins have internal pull-up resistors.
PAGE 12
ADSP-21261 Table 2. Pin Function Descriptions (Continued) State During and After Reset Three-state with programmable pull-up Pin DAI_P20–1 Type I/O/T SPICLK I/O Three-state with pull-up enabled SPIDS I Input only MOSI I/O (O/D) Three-state with pull-up enabled MISO I/O (O/D) Three-state with pull-up enabled BOOTCFG1–0 I Input only Function Digital Applications Interface Pins. These pins provide the physical interface to the SRU.
PAGE 13
ADSP-21261 Table 2. Pin Function Descriptions (Continued) Pin CLKIN Type I State During and After Reset Input only XTAL O Output only2 CLKCFG1–0 I Input only RSTOUT/CLKOUT O Output only RESET I/A Input only TCK I Input only3 TMS I/S TDI I/S TDO TRST O I/A Three-state with pull-up enabled Three-state with pull-up enabled Three-state4 Three-state with pull-up enabled EMU O (O/D) VDDINT P VDDEXT P AVDD P AVSS GND G G Three-state with pull-up enabled Function Local Clock In.
PAGE 14
ADSP-21261 ADDRESS DATA PINS AS FLAGS ADDRESS DATA MODES To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the SYSCTL register and disable the parallel port. Table 6 shows the functionality of the AD pins for 8-bit and 16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23–A8 when asserted, followed by address bits A7–A0 and data bits D7–D0 when deasserted.
PAGE 15
ADSP-21261 ADSP-21261 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter1 Min Max Unit VDDINT Internal (Core) Supply Voltage 1.14 1.26 V AVDD Analog (PLL) Supply Voltage 1.14 1.26 V VDDEXT External (I/O) Supply Voltage 3.13 3.47 V 2.0 VDDEXT + 0.5 V –0.5 +0.8 VIH VIL 2 High Level Input Voltage @ VDDEXT = max 2 Low Level Input Voltage @ VDDEXT = min 3 V VIH_CLKIN High Level Input Voltage @ VDDEXT = max 1.74 VDDEXT + 0.
PAGE 16
ADSP-21261 ABSOLUTE MAXIMUM RATINGS Parameter Internal (Core) Supply Voltage (VDDINT)1 Analog (PLL) Supply Voltage (AVDD)1 External (I/O) Supply Voltage (VDDEXT)1 Input Voltage –0.5 V to VDDEXT1 Output Voltage Swing –0.5 V to VDDEXT1 Load Capacitance1 Storage Temperature Range1 Junction Temperature Under Bias 1 Rating –0.3 V to +1.4 V –0.3 V to +1.4 V –0.3 V to +3.8 V +0.5 V +0.5 V 200 pF –65°C to +150°C 125°C Stresses greater than those listed above may cause permanent damage to the device.
PAGE 17
ADSP-21261 TIMING SPECIFICATIONS The ADSP-21261’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’s internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1–0 pins.
PAGE 18
ADSP-21261 Power-Up Sequencing The timing requirements for DSP startup are given in Table 9 and Figure 6. Table 9.
PAGE 19
ADSP-21261 Clock Input See Table 10 and Figure 7. Table 10. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low CLKIN Width High tCKH tCKRF CLKIN Rise/Fall (0.4 V–2.0 V) tCCLK CCLK Period3 Min Max Unit 201 7.51 7.51 1602 802 802 3 10 ns ns ns ns ns 6.66 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL. Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
PAGE 20
ADSP-21261 Reset See Table 11 and Figure 9. Table 11. Reset Parameter Timing Requirements tWRST RESET Pulse Width Low1 tSRST RESET Setup Before CLKIN Low 1 Min Max Unit 4tCK 8 ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 9.
PAGE 21
ADSP-21261 Timer PWM_OUT Cycle Timing The timing specification in Table 14 and Figure 12 applies to Timer PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 14.
PAGE 22
ADSP-21261 DAI Pin-to-Pin Direct Routing See Table 16 and Figure 14 for direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 16. DAI Pin-to-Pin Direct Routing Parameter Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid Min Max Unit 1.5 10 ns DAI_Pn DAI_Pm tDPIO Figure 14. DAI Pin-to-Pin Direct Routing Rev.
PAGE 23
ADSP-21261 cases where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P07 – DAI_P20).
PAGE 24
ADSP-21261 Flags The timing specifications in Table 18 and Figure 16 apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface. See Table 2 on Page 11 for more information on flag use. Table 18. Flags Parameter Timing Requirement tFIPW FLAG3–0 IN Pulse Width Min Switching Characteristic tFOPW FLAG3–0 OUT Pulse Width Unit 2 × tCCLK + 3 ns 2 × tCCLK – 1 ns DAI_P20–1 (FLAG3–0IN) (AD15–0) tFIPW DAI_P20–1 (FLAG3–0OUT ) (AD15–0) tFOPW Figure 16. Flags Rev.
PAGE 25
ADSP-21261 Memory Read—Parallel Port The specifications in Table 19, Table 20, Figure 17, and Figure 18 are for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21261 is accessing external memory space. Table 19. 8-Bit Memory Read Cycle Parameter Timing Requirements tDRS Address/Data7–0 Setup Before RD High tDRH Address/Data7–0 Hold After RD High Address 15–8 to Data Valid tDAD Min Unit D + 0.5 × tCCLK – 3.5 ns ns ns 3.
PAGE 26
ADSP-21261 Table 20. 16-Bit Memory Read Cycle Parameter Timing Requirements tDRS tDRH Min Address/Data15–0 Setup Before RD high Address/Data15–0 Hold After RD high Max Unit 3.3 0 ns ns 2 × tCCLK – 2 1 × tCCLK – 0.5 2.5 × tCCLK – 2.0 0.5 × tCCLK – 0.8 0.5 × tCCLK – 0.
PAGE 27
ADSP-21261 Memory Write—Parallel Port Use the specifications in Table 21, Table 22, Figure 19, and Figure 20 for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21261 is accessing external memory space. Table 21.
PAGE 28
ADSP-21261 Table 22.
PAGE 29
ADSP-21261 Serial Ports To determine whether communication is possible between two devices at clock speed n, the specifications in Table 23, Table 24, Table 25, Table 26, Figure 21, and Figure 22 must be confirmed: 1) frame sync delay and frame sync setup and hold; 2) data delay and data setup and hold; and 3) SCLK width. Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 23.
PAGE 30
ADSP-21261 Table 25. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN Data Enable from External Transmit SCLK1 Data Disable from External Transmit SCLK1 tDDTTE tDDTIN Data Enable from Internal Transmit SCLK1 1 Min Max Unit 7 ns ns ns Max Unit 7 ns ns 2 –1 Referenced to drive edge. Table 26.
PAGE 31
ADSP-21261 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE SAMPLE EDGE tSCLKIW tSCLKW DAI_P20–1 (SCLK) DAI_P20–1 (SCLK) tDFSI tDFSE tHFSI tSFSI tHOFSI DAI_P20–1 (FS) tHFSE tSFSE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) tSDRE tHDRE DAI_P20–1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
PAGE 32
ADSP-21261 Input Data Port (IDP) The timing requirements for the IDP are given in Table 27 and Figure 23. IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 27.
PAGE 33
ADSP-21261 Note that the most significant 16 bits of external PDAP data can be provided through either the parallel port AD15–0 or the DAI_P20–5 pins. The remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DAI_P20–1 pins or at the AD15–0 pins. Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 28 and Figure 24. PDAP is the parallel mode operation of Channel 0 of the IDP.
PAGE 34
ADSP-21261 SPI Protocol—Master Table 29.
PAGE 35
ADSP-21261 Table 30.
PAGE 36
ADSP-21261 JTAG Test Access Port and Emulation See Table 31 and Figure 27. Table 31.
PAGE 37
ADSP-21261 OUTPUT DRIVE CURRENTS CAPACITIVE LOADING Figure 28 shows typical I-V characteristics for the output drivers of the ADSP-21261. The curves represent the current drive capability of the output drivers as a function of output voltage. Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 29). Figure 33 shows graphically how output delays and holds vary with load capacitance.
PAGE 38
ADSP-21261 Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required. 7 OUTPUT DELAY OR HOLD (ns) 6 Table 32. Thermal Characteristics for 136-Ball BGA1 5 Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT 4 y = 0.0904x - 2.712 3 2 1 0 –1 –2 –3 –4 0 20 40 60 80 100 1 120 Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 31.0 27.3 26.0 6.99 0.16 0.30 0.
PAGE 39
ADSP-21261 136-BALL BGA PIN CONFIGURATIONS Table 34 shows the ADSP-21261’s pin names and their default function after reset (in parentheses). Figure 34 on Page 41 shows the BGA package pin assignments. Table 34. 136-Ball BGA Pin Assignments Pin Name CLKCFG0 XTAL TMS TCK TDI CLKOUT TDO EMU MOSI MISO SPIDS VDDINT GND GND VDDINT GND GND GND GND GND GND GND GND FLAG3 Ball No.
PAGE 40
ADSP-21261 Table 34. 136-Ball BGA Pin Assignments (Continued) Pin Name AD5 AD4 GND GND GND GND GND GND VDDINT DAI_P16 (SD4B) AD15 ALE RD VDDINT VDDEXT AD8 VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT GND DAI_P10 (SD2B) Ball No.
PAGE 41
ADSP-21261 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P KEY VDDINT GND AVDD VDDEXT AVSS I/O SIGNALS * USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary) Rev.
PAGE 42
ADSP-21261 144-LEAD LQFP PIN CONFIGURATIONS Table 35 shows the ADSP-21261’s pin names and their default function after reset (in parentheses). Table 35. 144-Lead LQFP Pin Assignments Pin Name VDDINT CLKCFG0 CLKCFG1 BOOTCFG0 BOOTCFG1 GND VDDEXT GND VDDINT GND VDDINT GND VDDINT GND FLAG0 FLAG1 AD7 GND VDDINT GND VDDEXT GND VDDINT AD6 AD5 AD4 VDDINT GND AD3 AD2 VDDEXT GND AD1 AD0 WR VDDINT LQFP Pin No.
PAGE 43
ADSP-21261 PACKAGE DIMENSIONS The ADSP-21261 is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure 35 and Figure 36. 10.40 BSC SQ 12.00 BSC SQ 0.80 BSC TYP PIN A1 INDICATOR 0.80 BSC TYP 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TOP VIEW 1.70 MAX A B C D E F G H J K L M N P DETAIL A BOTTOM VIEW 1. DIMENSIONS ARE IN MILIMETERS (MM). 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.15 MM OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 3.
PAGE 44
ADSP-21261 SURFACE MOUNT DESIGN Table 36 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 36. BGA Data for Use with Surface Mount Design Ball Attach Package Type 136-Ball Mini-BGA Solder Mask (BC-136-3) Defined Solder Mask Opening 0.40 mm diameter Ball Pad Size 0.