SHARC Processor ADSP-21161N SUMMARY Integrated peripherals—integrated I/O processor, 1M bit onchip dual-ported SRAM, SDRAM controller, glueless multiprocessing features, and I/O ports (serial, link, external bus, SPI, and JTAG) ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit floating-point formats 100 MHz/110 MHz core instruction rate Single-cycle instruction execution, including SIMD operations in both computational units Up to 660 MFLOPs peak and 440 MFLOPs sustained performance 225-ball 17 m
ADSP-21161N TABLE OF CONTENTS Summary ............................................................... 1 Absolute Maximum Ratings ................................... 19 General Description ................................................. 3 ESD Caution ...................................................... 19 ADSP-21161N Family Core Architecture .................... 3 Timing Specifications ........................................... 19 ADSP-21161N Memory and I/O Interface Features .......
ADSP-21161N GENERAL DESCRIPTION The ADSP-21161N SHARC® DSP is a low cost derivative of the ADSP-21160 featuring Analog Devices Super Harvard Architecture. Easing portability, the ADSP-21161N is source code compatible with the ADSP-21160 and with first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. Like other SHARC DSPs, the ADSP21161N is a 32-bit processor that is optimized for high performance DSP applications.
ADSP-21161N When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Data Register File A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results.
ADSP-21161N Instruction Cache The ADSP-21161N includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache enables full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.
ADSP-21161N IOP REGISTERS INTERNAL MEMORY SPACE ADDRESS ADDRESS 0x0000 0000 - 0x0001 FFFF 0x0020 0000 LONG WORD ADDRESSING 0x0002 0000 - 0x0002 1FFF (BLK 0) 0x0002 8000 - 0x0002 9FFF (BLK 1) NORMAL WORD ADDRESSING 0x0004 0000 - 0x0004 3FFF (BLK 0) 0x0005 0000 - 0x0005 3FFF (BLK 1) SHORT WORD ADDRESSING 0x0008 0000 - 0X0008 7FFF (BLK 0) 0x000A 0000 - 0x000A 7FFF (BLK 1) MS0 BANK 0 0x00FF FFFF (NON-SDRAM) 0x03FF FFFF (SDRAM) 0x0400 0000 IOP REGISTERS OF ADSP-21161N WITH ID = 001 0x0010 0000 - 0x
ADSP-21161N DATA47–16 47 40 39 32 31 its own double-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are programmable as either transmit or receive. DATA15–0 24 23 PROM BOOT 16 15 8 7 0 L1DATA7–0 L0DATA7–0 DAT A15-8 DA TA7–0 Serial Ports The ADSP-21161N features four synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices.
ADSP-21161N DATA ADDRESS ADSP-21161N #3 CONTROL ADSP-21161N #4 CLOCK RESET ADDR23-0 DATA47-16 CLKIN RESET 3 ID2-0 CONTROL ADSP-21161N #2 CLKIN ADDR23-0 DATA47-16 RESET 2 ID2-0 CONTROL ADDR DATA ADSP-21161N #1 CS BMS CLKIN ADDR23-0 ADDR DATA47-16 DATA RESET 1 ID2-0 RD OE WR WE ACK ACK BOOT EPROM (OPTIONAL) GLOBAL MEMORY AND PERIPHERALS (OPTIONAL) CS MS3-0 SBTS CS CONTROL HBR HBG REDY ADDR DATA DATA ADDRESS CONTROL BR6-2 BR1 HOST PROCESSOR INTERFACE (OPTIONAL) RAS RAS
ADSP-21161N (for example 10k ohm). These pins must be driven low with a strong enough drive strength (10–50 ohms) to overcome the SHARC keeper latches present on these pins. If the drive strength provided is not strong enough, data access failures can occur. For single processor SHARC systems using this host access feature, address pins ADDR17, ADDR18, ADDR19, and ADDR20 may be tied low (for example through a 10k ohm resistor), driven low by a buffer/driver, or left floating.
ADSP-21161N Core Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices processors. Software Add-Ins for CrossCore Embedded Studio Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities and reduce development time.
ADSP-21161N PIN FUNCTION DESCRIPTIONS ADSP-21161N pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST).
ADSP-21161N Table 2. Pin Function Descriptions (Continued) Pin BRST Type I/O/T ACK I/O/S SBTS I/S CAS I/O/T RAS I/O/T SDWE I/O/T DQM O/T SDCLK0 SDCLK1 I/O/S/T O/S/T SDCKE I/O/T SDA10 O/T IRQ2–0 I/A FLAG11–0 I/O/A TIMEXP O HBR I/A HBG I/O CS I/A Function Sequential Burst Access. BRST is asserted by ADSP-21161N to indicate that data associated with consecutive addresses is being read or written.
ADSP-21161N Table 2. Pin Function Descriptions (Continued) Pin REDY Type O (O/D) DMAR1 I/A DMAR2 I/A DMAG1 O/T DMAG2 O/T BR6–1 I/O/S BMSTR O ID2–0 I RPBA I/S PA I/O/T DxA I/O DxB I/O SCLKx I/O FSx I/O SPICLK I/O Function Host Bus Acknowledge. The ADSP-21161N deasserts REDY (low) to add wait states to a host access of its IOP registers when CS and HBR inputs are asserted. DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services.
ADSP-21161N Table 2. Pin Function Descriptions (Continued) Pin SPIDS Type I MOSI I/O (o/d) MISO I/O (o/d) LxDAT7–0 [DATA15–0] I/O [I/O/T] LxCLK I/O LxACK I/O EBOOT I LBOOT I BMS I/O/T CLKIN I XTAL O CLK_CFG1-0 I Function Serial Peripheral Interface Slave Device Select. An active low signal used to enable slave devices. This input signal behaves like a chip select, and is provided by the master device for the slave devices.
ADSP-21161N Table 2. Pin Function Descriptions (Continued) 1 Pin CLKDBL Type I CLKOUT O/T RESET I/A RSTOUT1 O TCK TMS TDI I I/S I/S TDO TRST O I/A EMU O (O/D) VDDINT VDDEXT AVDD P P P AGND GND NC G G Function Crystal Double Mode Enable. This pin is used to enable the 2 clock double circuitry, where CLKOUT can be configured as either 1 or 2 the rate of CLKIN.
ADSP-21161N Table 3. Clock Rate Ratios CLKDBL 1 1 1 0 0 0 CLK_CFG1 0 0 1 0 0 1 CLK_CFG0 0 1 0 0 1 0 Core:CLKIN 2:1 3:1 4:1 4:1 6:1 8:1 BOOT MODES Table 4. Boot Mode Selection EBOOT 1 0 0 0 0 1 LBOOT 0 0 1 1 0 1 BMS Output 1 (Input) 0 (Input) 1 (Input) 0 (Input) x (Input) Booting Mode EPROM (Connect BMS to EPROM chip select.) Host Processor Serial Boot via SPI Link Port No Booting. Processor executes from external memory. Reserved Rev.
ADSP-21161N SPECIFICATIONS OPERATING CONDITIONS 100 MHz Parameter1 Description VDDINT AVDD VDDEXT VIH VIL TCASE Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage2 Low Level Input Voltage2 Case Operating Temperature3 Test Conditions @ VDDEXT = Max @ VDDEXT = Min 110 MHz Min Max Min Max Unit 1.71 1.71 3.13 2.0 –0.5 –40 1.89 1.89 3.47 VDDEXT +0.5 +0.8 +105 1.71 1.71 3.13 2.0 –0.5 –40 1.89 1.89 3.47 VDDEXT +0.5 +0.
ADSP-21161N ELECTRICAL CHARACTERISTICS Parameter Description VOH VOL IIH IIL IIHC IILC IIKH IIKL IIKH-OD IIKL-OD IILPU IOZH IOZL IOZLPU1 IOZLPU2 IOZHPD1 IOZHPD2 IDD-INPEAK High Level Output Voltage1 Low Level Output Voltage1 High Level Input Current3, 4 Low Level Input Current3 CLKIN High Level Input Current5 CLKIN Low Level Input Current5 Keeper High Load Current6 Keeper Low Load Current6 Keeper High Overdrive Current6, 7, 8 Keeper Low Overdrive Current6, 7, 8 Low Level Input Current Pull-Up4 Three-State
ADSP-21161N PACKAGE INFORMATION ESD CAUTION The information presented in Figure 7 provides details about how to read the package brand and relate it to specific product features. ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD.
ADSP-21161N ASYNCHRONOUS EP MULTIPROCESSING SBSRAM HOST SRAM CLOCK DOUBLER x1, x2 CCLK (33.3–110 MHz) CLKIN (CRYSTAL OSCILLATOR 4.2–55 MHz) CORE I/O PROCESSOR HARDWARE INTERRUPT I/O FLAG TIMER PLLICLK (4.2–50MHz) SYNCHRONOUS EP PLL CLKDBL CLKOUT SDRAM x1, x1/2 SERIAL PORTS x1/2 MAX RATIOS x2, x3, x4 XTAL (QUARTZ CRYSTAL 27.5 MHz MAX) LINK PORTS x1, x1/2, x1/3, x1/4 SPI x1/8 MAX CLK_CFG1–0 Figure 8. Core Clock and System Clock Relationship to CLKIN Table 7.
ADSP-21161N Table 8.
ADSP-21161N protection circuitry. With this technique, if the 1.8 V rail rises ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail along with the 1.8 V rail. Power-Up Sequencing — Silicon Revision 1.2 and Greater The timing requirements for DSP startup are given in Table 10. During the power-up sequence of the DSP, differences in the ramp-up rates and activation time between the two supplies can cause current to flow in the I/O ESD protection circuitry.
ADSP-21161N Clock Input In systems that use multiprocessing or SBSRAM, CLKDBL cannot be enabled nor can the systems use an external crystal as the CLKIN source. Do not use CLKOUT as the clock source for the SBSRAM device. Using an external crystal in conjunction with CLKDBL to generate a CLKOUT frequency is not supported. Negative hold times can result from the potential skew between CLKIN and CLKOUT. Table 11.
ADSP-21161N Clock Signals The ADSP-21161N can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21161N to use its internal clock generator by connecting CLKIN the necessary components to CLKIN and XTAL. Figure 12 shows the component connections used for a crystal operating in fundamental mode. XTAL X1 C1 27pF C2 27pF SUGGESTED COMPONENTS FOR 100MHz OPERATION: ECLIPTEK EC2SM-25.000M (SURFACE MOUNT PACKAGE) ECLIPTEK EC-25.
ADSP-21161N Interrupts Table 13. Interrupts Parameter Timing Requirements tSIR IRQ2–0 Setup Before CLKIN1 tHIR IRQ2–0 Hold After CLKIN1 tIPW IRQ2–0 Pulsewidth2 1 2 Min Max Unit 6 0 tCKOP + 2 ns ns ns Only required for IRQx recognition in the following cycle. Applies only if tSIR and tHIR requirements are not met. CLKIN tSIR tHIR IRQ2–0 tIPW Figure 14. Interrupts Timer Table 14.
ADSP-21161N Flags Table 15.
ADSP-21161N Memory Read — Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN except for ACK pin requirements listed in footnote 4 of Table 16. These specifications apply when the ADSP-21161N is the bus master accessing external memory space in asynchronous access mode. Table 16. Memory Read — Bus Master 100 MHz 110 MHz Parameter Min Max Min Max Timing Requirements tDAD Address, Selects Delay to tCKOP –0.25tCCLK –8.
ADSP-21161N tHDA ADDRESS MSx, BMS tDARL tDRHA tRW RD tSDS tDRLD tDAD tHDRH DATA tDSAK tDAAK tRWR ACK tHAKC tSAKC CLKIN WR, DMAG Figure 17. Memory Read — Bus Master Rev.
ADSP-21161N Memory Write — Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN except for ACK pin requirements listed in footnote 1 of Table 17. These specifications apply when the ADSP-21161N is the bus master accessing external memory space in asynchronous access mode. Table 17. Memory Write — Bus Master Parameter Min Max Timing Requirements ACK Delay from Address, Selects1, 2 tCKOP–0.
ADSP-21161N ADDRESS MSx, BMS tDAWH tDAWL tDWHA tWW WR tWWR tDATRWH tWDE tDDWH tDDWR DATA tDSAK tDWHD tDAAK ACK tHAKC tSAKC CLKIN RD, DMAG Figure 18. Memory Write — Bus Master Rev.
ADSP-21161N Synchronous Read/Write — Bus Master Use these specifications for interfacing to external memory systems that require CLKIN, relative to timing or for accessing a slave ADSP-21161N (in multiprocessor memory space). When accessing a slave ADSP-21161N, these switching characteristics must meet the slave's timing requirements for synchronous read/writes (see Synchronous Read/Write — Bus Slave on Page 32).
ADSP-21161N Synchronous Read/Write — Bus Slave Use these specifications for ADSP-21161N bus master accesses of a slave’s IOP registers in multiprocessor memory space. The bus master must meet these (bus slave) timing requirements. Table 19.
ADSP-21161N Host Bus Request Use these specifications for asynchronous host bus requests of an ADSP-21161N (HBR, HBG). Table 20.
ADSP-21161N CLKIN tSH B R I tH H BR I HBR tD H BG O tH H B GO HBG (OUT) tSH B GI tH H B GI HBG (IN) HBR CS tD R DY C S tTR D YH G REDY (O/D) tA R D YTR REDY (A/D) tH B GR CS V HBG (OUT) RD WR CS O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 21. Host Bus Request Rev.
ADSP-21161N Multiprocessor Bus Request Use these specifications for passing of bus mastership between multiprocessing ADSP-21161Ns (BRx). Table 21.
ADSP-21161N Asynchronous Read/Write — Host to ADSP-21161N Use these specifications for asynchronous host processor accesses of an ADSP-21161N, after the host has asserted CS and HBR (low). After HBG is returned by the ADSP-21161N, the host can drive the RD and WR pins to access the ADSP-21161N’s IOP registers. HBR and HBG are assumed low for this timing.
ADSP-21161N READ CYCLE ADDRESS/CS tSADRDL tHADRDH tWRWH RD tHDARW H DATA (OUT) tS DAT RDY tDRDY RDL tDRDHRDY tRDYPRD REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS tS ADW RH tSCS WRL tHADW RH tHCSWRH CS t WWRL tW RW H WR tSDATWH tHDATWH DATA (IN) tDRDY WRL tRDYPW R REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 23. Asynchronous Read/Write — Host to ADSP-21161N Rev.
ADSP-21161N During reset, the DSP will not respond to SBTS, HBR, and MMS accesses. Although the DSP will recognize HBR asserted before reset, a HBG will not be returned by the DSP until after reset is deasserted and the DSP completes bus synchronization. Three-State Timing — Bus Master, Bus Slave These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin.
ADSP-21161N CLKIN tSTSCK tHTSCK SBTS tMIENA, tMIENS, tMIENHG tMITRA, tMITRS, tMITRHG MEMORY INTERFACE tDATEN tDATTR tACKEN tACKTR DATA ACK CLKIN tCDCEN tCDCTR CLKOUT HBG tMENHBG tATRHBG, tSTRHBG, tBTRHBG MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RD, WR, MSx, DMAGx, BMS (IN EPROM MODE) Figure 24. Three-State Timing — Bus Master, Bus Slave Rev.
ADSP-21161N DMA Handshake These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the ADDR23–0, RD, WR, MS3–0, ACK, and DMAG signals. For Paced Master mode, the data transfer is controlled by ADDR23–0, RD, WR, MS3–0, and ACK (not DMAG).
ADSP-21161N CLKIN tDMARLL tSDRC tSDRC tDMARH tWDR DMARx tHDGC tDDGL tWDGL tWDGH DMAGx TRANSFERS BETWEEN ADSP-21161N INTERNAL MEMORY AND EXTERNAL DEVICE tDATRDGH tVDATDGH DATA (FROM ADSP-2116x TO EXTERNAL DRIVE) tDATDRH tHDATIDG tSDATDGL DATA (FROM EXTERNAL DRIVE TO ADSP-21161N) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY1 (EXTERNAL HANDSHAKE MODE) tDGWRL WR tDGWRH (EXTERNAL DEVICE TO EXTERNAL MEMORY) tDGRDR tDGRDL RD tDGWR tDGWRR (EXTERNAL MEMORY TO EXTERNAL DEVICE) tDRDGH t
ADSP-21161N SDRAM Interface — Bus Master Use these specifications for ADSP-21161N bus master accesses of SDRAM: Table 26.
ADSP-21161N CLKIN tDSDK1 tSDKH tSDK SDCLK tSDSDK tSDKL tHDSDK DATA(IN) tSDTRSDK tDCADSDK tSDENSDK tHCADSDK DATA(OUT) CMND1ADDR (OUT) tDCADSDK tHCADSDK tSDCEN tSDCTR CMND1(OUT) ADDR (OUT) tSDAEN tSDATR CLKIN tSDSDKTR tSDSDKEN SDCLK CLKOUT tSSDKC1 SDCLK (IN) tSCSDK CMND2 (IN) tHCSDK 1COMMAND 2COMMAND = SDCKE, MSx, RAS, CAS, SDWE, DQM, AND SDA10. = SDCKE, RAS, CAS, AND SDWE. Figure 26. SDRAM Interface Rev.
ADSP-21161N tions made directly from speed specifications will result in unrealistically small skew times because they include multiple tester guardbands. The setup and hold skew times shown below are calculated to include only one tester guardband. Link Ports Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK.
ADSP-21161N Table 29. Link Ports — Transmit Parameter Timing Requirements tSLACH LACK Setup Before LCLK High LACK Hold After LCLK High tHLACH Switching Characteristics tDLDCH Data Delay After LCLK High tHLDCH Data Hold After LCLK High tLCLKTWL LCLK Width Low tLCLKTWH LCLK Width High tDLACLK LCLK Low Delay After LACK High Min Max Unit 8 –2 ns ns 3 0 0.5tLCLK–1.0 0.5tLCLK–1.0 0.5tLCLK+3 0.5tLCLK+1.0 0.5tLCLK+1.
ADSP-21161N Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 30.
ADSP-21161N Table 34. Serial Ports —– Enable and Three-State Parameter Switching Characteristics tDDTEN Data Enable from External Transmit SCLK1, 2 Data Disable from External Transmit SCLK1 tDDTTE tDDTIN Data Enable from Internal Transmit SCLK1 tDDTTI Data Disable from Internal Transmit SCLK1 Min Max 4 Unit 3 ns ns ns ns Max Unit 13 ns 10 0 1 Referenced to drive edge. 2 SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register. Table 35.
ADSP-21161N DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE DATA RECEIVE— EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE SAMPLE EDGE tSCLKIW tSCLKW SCLK SCLK tDFSI tDFSE tHOFSI tSFSI tHFSI FS tHOFSE tSFSE tHFSE tSDRE tHDRE FS tSDRI tHDRI DXA/DXB DXA/DXB NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
ADSP-21161N EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE SCLK tSFSE/I tHOFSE/I FS tDDTE/I tDDTENFS DXA/DXB tHDTE/I 1ST BIT 2ND BIT tDDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE SCLK tSFSE/I tHOFSE/I FS tDDTE/I tDDTENFS DXA/DXB tHDTE/I 1ST BIT 2ND BIT tDDTLFSE Figure 30. Serial Ports — External Late Frame Sync Rev.
ADSP-21161N SPI Interface Specifications Table 36.
ADSP-21161N Table 37.
ADSP-21161N SPIDS (INPUT) tSPICHS tSPICLS tS P I C L K S tHDS SPICLK (CP = 0) (INPUT) tSPICLS tS D S C O SPICLK (CP = 1) (INPUT) tSPICHS tDSD HI tDDSPIDS tDSOE tS D P P W tD D S P I D S MISO (OUTPUT) t H D S P ID S MSB LSB t H S P ID S tSSPIDS CPHASE = 1 tSSPIDS MOSI (INPUT) MSB VALID LSB VALID tDSOV MISO (OUTPUT) t H D S PI D S LSB MSB CPHASE = 0 MOSI (INPUT) t H D LS B S tDDSPIDS tDSOE t H S P ID S tSSPIDS MSB VALID LSB VALID Figure 32.
ADSP-21161N JTAG Test Access Port and Emulation Table 38.
ADSP-21161N OUTPUT DRIVE CURRENTS Figure 34 shows typical I-V characteristics for the output drivers of the ADSP-21161N. The curves represent the current drive capability of the output drivers as a function of output voltage. REFERENCE SIGNAL tMEASURED tDIS tENA VOH (MEASURED) 80 60 VDDEXT = 3.47V, –40°C VOL (MEASURED) 50 VDDEXT = 3.3V, +25°C 40 LOAD (VDDEXT) CURRENT – mA 30 VDDEXT = 3.13V, +105°C VOH (MEASURED) – ⌬V VOH 2.0V (MEASURED) VOL (MEASURED) + ⌬V 1.
ADSP-21161N Capacitive Loading OUTPUT DELAY OR HOLD – ns 25 Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 36 on Page 54). Figure 38 shows graphically how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on Page 54.) The graphs of Figure 38, Figure 39, and Figure 40 may not be linear outside the ranges shown for Typical Output Delay vs.
ADSP-21161N 225-BALL CSP_BGA BALL CONFIGURATIONS Table 40.
ADSP-21161N Table 40.
ADSP-21161N OUTLINE DIMENSIONS The ADSP-21161N comes in a 17 mm 17 mm, 225-ball CSP_BGA package with 15 rows of balls. A1 BALL CORNER 17.20 17.00 SQ 16.80 A1 BALL CORNER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C 14.00 BSC SQ D E F G H 1.00 BSC J K L M N P R 0.50 REF TOP VIEW *1.85 1.71 1.40 DETAIL A 0.54 0.50 0.30 SEATING PLANE BOTTOM VIEW *1.31 1.21 1.10 DETAIL A 0.70 0.60 0.50 BALL DIAMETER COPLANARITY 0.
ADSP-21161N Rev.
ADSP-21161N © 2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02935-0-1/13 (C) Rev.
