a SHARC® DSP Microcomputer ADSP-21160M SUMMARY High-Performance 32-Bit DSP—Applications in Audio, Medical, Military, Graphics, Imaging, and Communication Super Harvard Architecture—Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive, Zero-Overhead I/O Backwards-Compatible—Assembly Source Level Compatible with Code for ADSP-2106x DSPs Single-Instruction-Multiple-Data (SIMD) Computational Architecture—Two 32-Bit IEEE Floating-Point Computation Units, Each with a Multiplier, ALU,
ADSP-21160M FEATURES (CONTINUED) Single Instruction Multiple Data (SIMD) Architecture Provides: Two Computational Processing Elements Concurrent Execution—Each Processing Element Executes the Same Instruction, but Operates on Different Data Code Compatibility—at Assembly Level, Uses the Same Instruction Set as the ADSP-2106x SHARC DSPs Parallelism in Buses and Computational Units Allows: Single-cycle Execution (with or without SIMD) of: A Multiply Operation, An ALU Operation, A Dual Memory Read or Write, an
ADSP-21160M The functional block diagram on page 1 shows a block diagram of the ADSP-21160M, illustrating the following architectural features: • Two processing elements, each made up of an ALU, Multiplier, Shifter, and Data Register File • Data Address Generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data transfers between memory and the core every core processor cycle • Interval timer • On-Chip SRAM (4 Mbit) • External port that support
ADSP-21160M With the ADSP-21160M’s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands and an instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-21160M includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached.
ADSP-21160M +,-.+/0 -12.3 4/5- -678 2+6 (2.9 2.1/0 (2.9 :2., (2.9 +,-.+/0 ) /+; ) ' -12.3 4/5- ' " /+; # # # " ! = +,-.+/0 -12.3 4/5- /+; = +,-.
? tle-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. They offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding. Serial port clocks and frame syncs can be internally or externally generated.
ADSP-21160M ⍀ '',17 '' Figure 5. Analog Power (AVDD) Filter Circuit Development Tools The ADSP-21160M is supported with a complete set of software and hardware development tools, including Analog Devices’ emulators and VisualDSP++1 development environment. The same emulator hardware that supports other ADSP-2116x DSPs, also fully emulates the ADSP-21160M. The VisualDSP++ project management environment lets programmers develop and debug an application.
ADSP-21160M Also, the clearance (length, width, and height) around the header must be considered. Leave a clearance of at least 0.15" and 0.10" around the length and width of the header, and reserve a height clearance to attach and detach the pod connector.
ADSP-21160M Unused inputs should be tied or pulled to VDD or GND, except for ADDR31–0, DATA63–0, FLAG3–0, and inputs that have internal pull-up or pull-down resistors (PA, ACK, BRST, PAGE, CLKOUT, MS3–0, RDx, WRx, DMARx, DMAGx, DTx, DRx, TCLKx, RCLKx, LxDAT7–0, LxCLK, LxACK, TMS, TRST and TDI)—these pins can be left floating. These pins have a logic-level hold circuit (only enabled on the ADSP-21160M with ID2–0 = 00x) that prevents input from floating internally.
ADSP-21160M Table 2. Pin Function Descriptions (Continued) Pin Type Function BRST I/O/T ACK I/O/S SBTS I/S IRQ2–0 I/A FLAG3–0 I/O/A TIMEXP O HBR I/A HBG I/O CS REDY I/A O (O/D) DMAR1 I/A DMAR2 I/A ID2–0 I DMAG1 O/T Sequential Burst Access. BRST is asserted by ADSP-21160M or a host to indicate that data associated with consecutive addresses is being read or written. A slave device samples the initial address and increments an internal address counter after each transfer.
ADSP-21160M Table 2. Pin Function Descriptions (Continued) Pin Type Function DMAG2 O/T BR6–1 I/O/S RPBA I/S PA I/O/T DTx DRx TCLKx O I I/O RCLKx TFSx RFSx LxDAT7–0 I/O I/O I/O I/O LxCLK I/O LxACK I/O EBOOT I LBOOT I BMS I/O/T CLKIN I CLK_CFG3–0 I CLKOUT O/T RESET I/A DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160M to indicate that the requested DMA starts on the next cycle. Driven by bus master only. Multiprocessing Bus Requests.
ADSP-21160M Table 2. Pin Function Descriptions (Continued) Pin Type Function TCK TMS I I/S TDI I/S TDO TRST O I/A EMU O (O/D) CIF O/T VDDINT P VDDEXT AVDD P P AGND GND NC G G Test Clock (JTAG). Provides a clock for JTAG boundary scan. Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal pull-up resistor. Test Data Output (JTAG).
ADSP-21160M ADSP-21160M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 1 Signal K Grade Parameter1 Min Max Unit VDDINT AVDD VDDEXT VIH1 VIH2 VIL TCASE Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage2, @ VDDEXT =Max High Level Input Voltage3, @ VDDEXT =Max Low Level Input Voltage2,3, @ VDDEXT =Min Case Operating Temperature4 2.37 2.37 3.13 2.2 2.3 –0.5 0 2.63 2.63 3.47 VDDEXT +0.5 VDDEXT +0.5 0.
ADSP-21160M 5 Applies to input pins with internal pull-ups: DR0, DR1. 6 Applies to input pins with internal pull-ups: DMARx, TMS, TDI, TRST. 7 Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, TDO. 8 Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU. 9 Applies to three-statable pins with internal pull-ups: MS3–0, RDx, WRx, DMAGx, PA, CIF.
ADSP-21160M Timing Specifications The ADSP-21160M’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP’s internal clock (the clock source for the external port logic and I/O pads).
ADSP-21160M Clock Input Table 4. Clock Input 80 MHz Parameter Timing Requirements: CLKIN Period tCK tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4V–2.0V) Min Max 25 10.5 10.5 80 40 40 3 Unit ns ns ns ns , , ! , Figure 10. Clock Input Reset Table 5. Reset Parameter Min Timing Requirements: RESET Pulsewidth Low1 tWRST tSRST RESET Setup Before CLKIN High2 4tCK 8 Max Unit ns ns 1 Applies after the power-up sequence is complete.
ADSP-21160M Interrupts Table 6. Interrupts 1 2 Parameter Min Timing Requirements: IRQ2–0 Setup Before CLKIN High1 tSIR tHIR IRQ2–0 Hold After CLKIN High1 tIPW IRQ2–0 Pulsewidth2 6 0 2+tCK Max Unit ns ns ns Only required for IRQx recognition in the following cycle. Applies only if tSIR and tHIR requirements are not met. , , ! % $ , ( Figure 12. Interrupts Timer Table 7.
ADSP-21160M Flags Table 8.
ADSP-21160M memory space in asynchronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode. Memory Read—Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21160M is the bus master accessing external Table 9.
ADSP-21160M Memory Write—Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21160M is the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode. Table 10.
ADSP-21160M @ @ " , ( ! , ( , ( ! ,( ( ( ,( , , ( ! ,( ( (! , , ( ! , , , ! @ Figure 16. Memory Write—Bus Master REV.
ADSP-21160M Synchronous Read/Write—Bus Master Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP-21160M (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see Memory Read—Bus Master on page 19 and Memory Write—Bus Master on page 20).
ADSP-21160M , , ( ! , , ( # , @ " , ! @ , , , ! , , # , , ( , ,! ( , , ( ( ( , ! , # Figure 17. Synchronous Read/Write—Bus Master REV.
ADSP-21160M Synchronous Read/Write—Bus Slave Use these specifications for ADSP-21160M bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet these (bus slave) timing requirements. Table 12.
ADSP-21160M , , ! , ! , , ,! ( ( , ! , # ( , ,! ( ( ( , Figure 18. Synchronous Read/Write—Bus Slave REV.
ADSP-21160M Multiprocessor Bus Request and Host Bus Request Use these specifications for passing of bus mastership between multiprocessing ADSP-21160Ms (BRx) or a host processor (HBR, HBG). Table 13.
ADSP-21160M , ! , ! ! ! , ! , !! ! # , , ! # , , # , , # , ! , !! ! , ,! , , ! , ,! ! , , ! , , ! ! # ( = @ = Figure 19. Multiprocessor Bus Request and Host Bus Request REV.
ADSP-21160M is returned by the ADSP-21160M, the host can drive the RDx and WRx pins to access the ADSP-21160M’s internal memory or IOP registers. HBR and HBG are assumed low for this timing Asynchronous Read/Write—Host to ADSP-21160M Use these specifications (Table 14 and Table 15) for asynchronous host processor accesses of an ADSP-21160M, after the host has asserted CS and HBR (low). After HBG Table 14.
ADSP-21160M Table 15.
ADSP-21160M Three-State Timing—Bus Master and Bus Slave These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin. Table 16.
ADSP-21160M , ,! , @ , @ , ! , @ , @ , ! " , , , , , , # ! , , ! " " = @ @ ( @ @ "@ ! @ @ B Figure 22. Three-State Timing—Bus Slave, HBR, SBTS REV.
ADSP-21160M DMA Handshake These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the ADDR31–0, RDx, WRx, PAGE, MS3–0, ACK, and DMAG signals. For Paced Master mode, the data transfer is controlled by ADDR31–0, RDx, WRx, MS3–0, and ACK (not DMAG).
ADSP-21160M , , , ,( , ! , ! , ,( ,( ! " ( , ! , ! " , , ! , ! " " ( D ! ! , ( , ( (
ADSP-21160M Link Ports Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in LDATA relative to LCLK (setup skew = tLCLKTWH Min – tDLDCH – tSLDCL). Hold skew is the maximum delay that can be introduced in LCLK relative to LDATA (hold skew = tLCLKTWL Min – tHLDCH – tHLDCL).
ADSP-21160M Table 19. Link Ports—Receive Parameter Min Timing Requirements: Data Setup Before LCLK Low tSLDCL tHLDCL Data Hold After LCLK Low tLCLKIW LCLK Period tLCLKRWL LCLK Width Low LCLK Width High tLCLKRWH Switching Characteristics: LACK Low Delay After LCLK High1 tDLALC 1 Max 2.5 2.5 tLCLK 6.0 6.0 ns ns ns ns ns 12 17 LACK goes low with tDLALC relative to rise of LCLK after first nibble, but doesn’t go low if the receiver’s link buffer is not about to fill.
ADSP-21160M Table 20. Link Ports—Transmit Parameter Min Timing Requirements: LACK Setup Before LCLK High tSLACH tHLACH LACK Hold After LCLK High Switching Characteristics: Data Delay After LCLK High tDLDCH tHLDCH Data Hold After LCLK High tLCLKTWL LCLK Width Low LCLK Width High tLCLKTWH tDLACLK LCLK Low Delay After LACK High Max Unit 14 –2 ns ns 6.0 –2 0.5tLCLK – 1.5 0.5tLCLK – 1.5 0.5tLCLK +5 0.5tLCLK +1.5 0.5tLCLK +1.
ADSP-21160M Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 21.
ADSP-21160M Table 25. Serial Ports—Internal Clock (Continued) Parameter tDDTI tHDTI tSCLKIW 1 Min 1 Transmit Data Delay After TCLK Transmit Data Hold After TCLK1 TCLK/RCLK Width Max Unit 7.5 0 0.5tSCLK – 2.5 0.5tSCLK +2 ns ns ns Min Max Unit Referenced to drive edge. Table 26.
ADSP-21160M F , F , , " , " , , ! " , !" " , ! " " , " ,! " , ,! " , ,! E ! F , ! " " @ # ( ! B F , ( , " , ! "
ADSP-21160M Table 27. Serial Ports—External Late Frame Sync Parameter Min Switching Characteristics: Data Delay from Late External TFS or External RFS with tDDTLFSE MCE = 1, MFD = 01 tDDTENFS Data Enable from late FS or MCE = 1, MFD = 01 1 1.0 Max Unit 13 ns ns MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.
ADSP-21160M JTAG Test Access Port and Emulation Table 28.
ADSP-21160M Output Drive Currents Figure 29 shows typical I–V characteristics for the output drivers of the ADSP-21160M. The curves represent the current drive capability of the output drivers as a function of output voltage.
ADSP-21160M The load capacitance should include the processor’s package capacitance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2tCK). The write strobe can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects can switch on each cycle. Table 29. ADSP-21160M Operation Types vs.
ADSP-21160M • External data memory writes occur every other cycle, a rate of 1/(4 tCK), with 50% of the pins switching • The bus cycle time is 40 MHz (tCK = 25 ns). Example: Estimate PEXT with the following assumptions: • A system with one bank of external data memory—asynchronous RAM (64-bit) • Four 64K × 16 RAM chips are used, each with a load of 10 pF The PEXT equation is calculated for each class of pins that can drive: Table 30. External Power Calculations (3.
ADSP-21160M *B B $ +8 = B ) A H B " B* * 4" *B " B = B ' H B * # # ! *B Figure 31. Equivalent Device Loading for AC Measurements (Includes All Fixtures) # # # B* B * * $ 4" * Figure 34. Typical Output Rise Time (10%–90%, VDDEXT = Min) vs. Load Capacitance B* B # # ! $ +8 Figure 32.
ADSP-21160M T CASE = T AMB + ( PD × θ CA ) • TCASE = Case temperature (measured on top surface of package) • PD = Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation). • θCA = Value from Table 31. • θ JB= 6.46°C/W Table 31. Airflow Over Package Versus θCA Airflow (Linear Ft./Min.) θCA (°C/W)1 1 θJC = 3.6 °C/W. 0 12.13 200 9.86 400 8.
ADSP-21160M Table 32.
ADSP-21160M Table 32.
ADSP-21160M Table 32.
ADSP-21160M 400-BALL METRIC PBGA PIN CONFIGURATIONS (BOTTOM VIEW, SUMMARY) ) A ' * ) A ' * " ! # ( E D D # ! " # E ! )$ @ )$ @ )$ @ )$ @ )$ @ )$ ! ! ( # # 7 # B –50– REV.
ADSP-21160M OUTLINE DIMENSIONS The ADSP-21160M comes in a 27mm ⴛ 27mm, 400-ball Metric PBGA package with 20 rows of balls.
ADSP-21160M ORDERING GUIDE Part Number1, 2 Case Temperature Range Instruction Rate On-Chip SRAM Operating Voltage ADSP-21160MKB-80 0°C to 85°C 80 MHz 4 Mbit 2.5 INT/3.3 EXT V 1 PRINTED IN U.S.A. C02426–2.5–4/01(0) B = Plastic Ball Grid Array (PBGA) package. 2 See ADSP-21160N data sheet for ordering information for higher-performance derivative. –52– REV.