Datasheet

ManualsBrandsANALOG DEVICES ManualsClock & Timing ICsLFCSP-32-VQ

Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and

Data Recovery IC with Integrated Limiting Amp

ADN2813

Rev. B

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rights of third parties that may result from its use. Specifications subject to change without notice. No

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FEATURES

Serial data input: 10 Mb/s to 1.25 Gb/s

Exceeds SONET requirements for jitter transfer/

generation/tolerance

Quantizer sensitivity: 3.3 mV typ

Adjustable slice level: ±95 mV

Patented clock recovery architecture

Loss-of-signal (LOS) detect range: 2.3 mV to 19 mV

Independent slice level adjust and LOS detector

No reference clock required

Loss-of-lock indicator

C® interface to access optional features

Single-supply operation: 3.3 V

Low power: 450 mW typ

5 mm × 5 mm 32-lead LFCSP, Pb free

APPLICATIONS

SONET OC-1/-3/-12 and all associated FEC rates

Fibre Channel, GbE, HDTVs

WDM transponders

Regenerators/repeaters

Test equipment

Broadband cross-connects and routers

GENERAL DESCRIPTION

The ADN2813 provides the receiver functions of quantization,

signal level detect, and clock and data recovery for continuous

data rates from 10 Mb/s to 1.25 Gb/s. The ADN2813 automati-

cally locks to all data rates without the need for an external

reference clock or programming. All SONET jitter requirements

are met, including jitter transfer, jitter generation, and jitter

tolerance. All specifications are quoted for −40°C to +85°C

ambient temperature, unless otherwise noted.

This device, together with a PIN diode and a TIA preamplifier,

can implement a highly integrated, low cost, low power fiber

optic receiver.

The receiver front-end, loss-of-signal (LOS) detector circuit

indicates when the input signal level has fallen below a user-

adjustable threshold. The LOS detect circuit has hysteresis to

prevent chatter at the output.

The ADN2813 is available in a compact 5 mm × 5 mm,

32-lead LFCSP.

FUNCTIONAL BLOCK DIAGRAM

04951-0-001

SLICEP/N

LOL

DATAOUTP/NLOSTHRADJ CLKOUTP/N

ADN2813

VCC VEECF1 CF2

NIN

VREF

QUANTIZER

VCO

PHASE

SHIFTER

PHASE

DETECT

FREQUENCY

DETECT

LOS

DETECT

DATA

RE-TIMING

LOOP

FILTER

LOOP

FILTER

REFCLKP/N

(OPTIONAL)

Figure 1.

Summary of content (28 pages)

PAGE 1
Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2813 FEATURES GENERAL DESCRIPTION Serial data input: 10 Mb/s to 1.25 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typ Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.
PAGE 2
ADN2813 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 14 Applications ....................................................................................... 1 Functional Description .................................................................. 16 General Description ..................................................................
PAGE 3
ADN2813 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 1.
PAGE 4
ADN2813 Parameter POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT OPERATING TEMPERATURE RANGE 1 2 Conditions Min 3.0 Locked to 1.25 Gb/s –40 Typ 3.3 139 Max 3.6 155 +85 Unit V mA °C PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity. When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2813 input stage.
PAGE 5
ADN2813 OUTPUT AND TIMING SPECIFICATIONS Table 3.
PAGE 6
ADN2813 ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted. THERMAL CHARACTERISTICS Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Range Rating 4.2 V VEE − 0.4 V VCC + 0.4 V 125°C −65°C to +150°C Thermal Resistance 32-LFCSP, 4-layer board with exposed paddle soldered to VEE, θJA = 28°C/W.
PAGE 7
ADN2813 TIMING CHARACTERISTICS CLKOUTP TH 04951-0-002 TS DATAOUTP/N Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP/N VOH VOS 04951-0-032 |VOD| VOL Figure 3. Differential Output Specifications 5mA RLOAD 100Ω VDIFF 100Ω SIMPLIFIED LVDS OUTPUT STAGE Figure 4. Differential Output Stage Rev.
PAGE 8
ADN2813 32 VCC 31 VCC 30 VEE 29 DATAOUTP 28 DATAOUTN 27 SQUELCH 26 CLKOUTP 25 CLKOUTN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADN2813* TOP VIEW (Not to Scale) 24 VCC 23 VEE 22 LOS 21 SDA 20 SCK 19 SADDR5 18 VCC 17 VEE 04951-0-004 PIN 1 INDIC ATOR THRADJ 9 REFCLKP 10 REFCLKN 11 VCC 12 VEE 13 CF2 14 CF1 15 LOL 16 VCC 1 VCC 2 VREF 3 NIN 4 PIN 5 SLICEP 6 SLICEN 7 VEE 8 * THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. Figure 5. Pin Configuration Table 5.
PAGE 9
ADN2813 TYPICAL PERFORMANCE CHARACTERISTICS 16 12 10 8 6 4 04951-0-005 TRIP POINT (mV p-p) 14 2 1 10 100 1k 10k 100k RTH (Ω) Figure 6. LOS Comparator Trip Point Programming Rev.
PAGE 10
ADN2813 I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION R/W CTRL. SLAVE ADDRESS [6...0] A5 SET BY PIN 19 0 0 0 0 0 X 04951-0-007 1 MSB = 1 0 = WR 1 = RD S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P 04951-0-008 Figure 7.
PAGE 11
ADN2813 Table 6. Internal Register Map 1 Reg. Name FREQ0 FREQ1 FREQ2 RATE R/W R R R R Address 0x0 0x1 0x2 0x3 D7 MSB MSB 0 MISC R 0x4 x CTRLA W 0x8 CTRLB W 0x9 Config. LOL Reset MISC[4] System Reset 0 Reset MISC[2] 0 0 0 CTRLC W 0x11 0 0 0 0 0 Config.
PAGE 12
ADN2813 TERMINOLOGY OUTPUT NOISE 1 10mV p-p VREF SCOPE PROBE ADN2813 PIN + QUANTIZER – 50Ω 50Ω VREF 2.5V 3kΩ 04951-0-013 Input Sensitivity and Input Overdrive Sensitivity and overdrive specifications for the quantizer involve offset voltage, gain, and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 12.
PAGE 13
ADN2813 JITTER SPECIFICATIONS The ADN2813 CDR is designed to achieve the best biterror-rate (BER) performance and to exceed the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia Technologies specification. Jitter Generation The jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input. For SONET devices, the jitter generated must be less than 0.
PAGE 14
ADN2813 THEORY OF OPERATION Another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second-order phase-locked loop, and this zero is placed in the feedback path and, thus, does not appear in the closed-loop transfer function. Jitter peaking in a conventional second-order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function.
PAGE 15
ADN2813 At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of its tuning range or at the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger, and therefore the phase shifter takes on the burden of tracking the input jitter.
PAGE 16
ADN2813 FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION LOSS-OF-SIGNAL (LOS) DETECTOR The ADN2813 acquires frequency from the data over a range of data frequencies from 10 Mb/s to 1.25 Gb/s. The lock detector circuit compares the frequency of the VCO and the frequency of the incoming data. When these frequencies differ by more than 1000 ppm, LOL is asserted. This initiates a frequency acquisition cycle. The VCO frequency is reset to the bottom of its range, which is 10 MHz.
PAGE 17
ADN2813 exceeds 1000 ppm (0.1%), the loss-of-lock signal is reasserted and control returns to the frequency loop, which begins a new frequency acquisition starting at the lowest point in the VCO operating range, 10 MHz. The LOL pin remains asserted until the VCO locks onto a valid input data stream to within 250 ppm frequency error. This hysteresis is shown in Figure 20. LOL 1 Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin, Pin 16, to become a static LOL indicator.
PAGE 18
ADN2813 SQUELCH MODE Two SQUELCH modes are available with the ADN2813. SQUELCH DATAOUT and CLKOUT mode is selected when CTRLC[1] = 0 (default mode). In this mode, when the SQUELCH input, Pin 27, is driven to a TTL high state, both the clock and data outputs are set to the zero state to suppress downstream processing. If the SQUELCH function is not required, Pin 27 should be tied to VEE. SQUELCH DATAOUT or CLKOUT mode is selected when CTRLC[1] is 1.
PAGE 19
ADN2813 Using the Reference Clock to Lock onto Data ADN2813 In this mode, the ADN2813 locks onto a frequency derived from the reference clock according to REFCLKP 10 BUFFER Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6] 11 100kΩ 100kΩ VCC/2 04951-0-021 REFCLKN The user must know exactly what the data rate is and provide a reference clock that is a function of this rate.
PAGE 20
ADN2813 The reference clock can range from 10 MHz and 160 MHz. The ADN2813 expects a reference clock between 10 MHz and 20 MHz by default. If it is between 20 MHz and 40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs to configure the ADN2813 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Using the reference clock to determine the frequency of the incoming data does not affect the manner in which the part locks onto data.
PAGE 21
ADN2813 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pin 24, which supplies power to the high speed CLKOUTP/CLKOUTN and DATAOUTP/ DATAOUTN output buffers. Refer to Figure 24 for the recommended connections. Proper RF PCB design techniques must be used for optimal performance.
PAGE 22
ADN2813 Transmission Lines Choosing AC Coupling Capacitors Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN, if a high frequency reference clock is used, such as 155 MHz).
PAGE 23
ADN2813 VCC V1 ADN2813 CIN V2 PIN COUT + DATAOUTP 50Ω TIA V1b CIN V2b CDR LIMAMP VREF DATAOUTN 50Ω COUT – NIN V1 2 1 3 4 V1b V2 VREF V2b VTH VDIFF NOTES: 1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO. 2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS. 3.
PAGE 24
ADN2813 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 13. Look-Up Table Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 FMID 5.3745e+06 5.3741e+06 5.4793e+06 5.5912e+06 5.7111e+06 5.8391e+06 5.9760e+06 6.1215e+06 6.2780e+06 6.4565e+06 6.6391e+06 6.8372e+06 7.0520e+06 7.2868e+06 7.5424e+06 7.8220e+06 7.6663e+06 7.6659e+06 7.8217e+06 7.9880e+06 8.1667e+06 8.
PAGE 25
ADN2813 Code 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 FMID 3.4397e+08 3.4394e+08 3.5067e+08 3.5783e+08 3.6551e+08 3.7370e+08 3.8247e+08 3.9177e+08 4.0179e+08 4.1322e+08 4.2490e+08 4.3758e+08 4.5133e+08 4.6636e+08 4.8272e+08 5.0061e+08 Code 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 FMID 4.9064e+08 4.9062e+08 5.0059e+08 5.1123e+08 5.2267e+08 5.3485e+08 5.4794e+08 5.6195e+08 5.7706e+08 5.9423e+08 6.1189e+08 6.3098e+08 6.5173e+08 6.7423e+08 6.9873e+08 7.
PAGE 26
ADN2813 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 12° MAX 17 16 0.80 MAX 0.65 TYP 0.30 0.23 0.18 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 9 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 1 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 011708-A TOP VIEW 1.00 0.85 0.
PAGE 27
ADN2813 NOTES Rev.
PAGE 28
ADN2813 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04951-0-6/10(B) Rev.