a Single-Chip, DSP-Based High Performance Motor Controller ADMC401 Internal or External Voltage Reference Out-of-Range Detection Voltage Reference Internal 2.0 V 2.0% Voltage Reference Three-Phase 16-Bit PWM Generation Unit Programmable Switching Frequency, Dead Time and Minimum Pulsewidth Edge Resolution of 38.
ADMC401–SPECIFICATIONS (VDD = AVDD = 5 V 5%, GND = AGND = 0 V, TAMB = –40 C to +85 C, RECOMMENDED OPERATING CONDITIONS CLKIN = 13 MHz, unless otherwise noted) B Grade Parameter VDD AVDD TAMB Digital Supply Voltage Analog Supply Voltage Ambient Operating Temperature Min Max Unit 4.75 4.75 –40 5.25 5.
ADMC401 ANALOG-TO-DIGITAL CONVERTER (VDD = AVDD = 5 V 5%, GND = AGND = 0 V, TAMB = –40 C to +85 C, CLKIN = 13 MHz, VIN0 to VIN7 = 4.0 V p-p, VREF = 2.0 V, unless otherwise noted) Parameter AC SPECIFICATIONS SNR Signal to Noise Ratio SNRD Signal to Noise and Distortion THD Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio Test Conditions Min Typ fIN = 1.0 kHz fIN = 1.0 kHz fIN = 1.0 kHz fIN = 1.
ADMC401 ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range (Ambient) . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . .
ADMC401 Parameter Min Max 76.9 20 20 150 Unit Clock Signals tCK is defined as 0.5tCKI. The ADMC401 uses an input clock with a frequency equal to half the instruction rate; a 13 MHz clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor cycle (equivalent to 26 MHz). tCK values within the range of 0.5tCKI period should be substituted for all relevant timing parameters to obtain specification value. Example: tCKH = 0.5tCK – 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.
ADMC401 Parameter Min Max Unit Interrupts and Flags Timing Requirements: tIFS tIFH IRQx or FI Setup before CLKOUT Low1, 2, 3 IRQx or FI Hold after CLKOUT High1, 2, 3 0.25tCK + 15 0.25tCK ns ns Switching Characteristics: tFOH tFOD Flag Output Hold after CLKOUT Low4 Flag Output Delay from CLKOUT Low4 0.5tCK – 7 0.
ADMC401 Parameter Min Max Unit Bus Request/Grant Timing Requirements: tBH tBS BR Hold after CLKOUT High1 BR Setup before CLKOUT Low1 0.25tCK +2 0.25tCK + 17 ns ns Switching Characteristics: tSD tSDB tSE tSEC tSDBH tSEH CLKOUT High to DMS, PMS, BMS, RD, WR Disable DMS, PMS, BMS, RD, WR Disable to BG Low BG High to DMS, PMS, BMS, RD, WR Enable DMS, PMS, BMS, RD, WR Enable to CLKOUT High DMS, PMS, BMS, RD, WR Disable to BGH Low2 BGH High to DMS, PMS, BMS, RD, WR Enable2 0.
ADMC401 Parameter Min Max Unit 0.5tCK – 11 + w 0.75tCK – 12 + w ns ns ns Memory Read Timing Requirements: tRDD tAA tRDH RD Low to Data Valid A0–A13, PMS, DMS, BMS to Data Valid Data Hold from RD High 0 Switching Characteristics: tRP tCRD tASR tRDA tRWR RD Pulsewidth CLKOUT High to RD Low A0–A13, PMS, DMS, BMS Setup before RD Low A0–A13, PMS, DMS, BMS Hold after RD Deasserted RD High to RD or WR Low 0.5tCK – 5 + w 0.25tCK – 5 0.25tCK – 6 0.25tCK – 3 0.5tCK – 5 0.
ADMC401 Parameter Min Max Unit Memory Write Switching Characteristics: tDW tDH tWP tWDE tASW tDDR tCWR tAW tWRA tWWR Data Setup before WR High Data Hold after WR High WR Pulsewidth WR Low to Data Enabled A0–A13, DMS, PMS Setup before WR Low Data Disable before WR or RD Low CLKOUT High to WR Low A0–A13, DMS, PMS, Setup before WR Deasserted A0–A13, DMS, PMS Hold after WR Deasserted WR High to RD or WR Low 0.5tCK – 7 + w 0.25tCK – 2 0.5tCK – 5 + w 0 0.25tCK – 6 0.25tCK – 6 0.25tCK – 5 0.75tCK – 9 + w 0.
ADMC401 Parameter Min Max Unit Serial Ports Timing Requirements: tSCK tSCS tSCH tSCP SCLK Period DR/TFS/RFS Setup before SCLK Low DR/TFS/RFS Hold after SCLK Low SCLKIN Width 50 5 10 20 ns ns ns ns Switching Characteristics: tCC tSCDE tSCDV tRH tRD tSCDH tTDE tTDV tSCDD tRDV CLKOUT High to SCLKOUT SCLK High to DT Enable SCLK High to DT Valid TFS/RFSOUT Hold after SCLK High TFS/RFSOUT Delay from SCLK High DT Hold after SCLK High TFS(Alt) to DT Enable TFS(Alt) to DT Valid SCLK High to DT Disable RFS (
ADMC401 POWER DISSIPATION To determine total power dissipation in a specific application, the following equation should be applied for each output: C × VDD2 × f 3.0V 1.5V 0.0V INPUT 2.0V 1.5V 0.3V OUTPUT C = load capacitance, f = output switching frequency. Example: Figure 7.
ADMC401 PIN FUNCTION DESCRIPTION Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
ADMC401 73 GND 74 D10 75 D9 76 D8 77 D7 78 D6 79 D5 80 D4 81 D3 82 GND 83 D2 84 D1 85 D0 86 P11 87 P10 88 P9 89 P8 91 GND 90 VDD 93 P6 92 P7 95 P4 94 P5 97 P2 96 P3 99 P1 98 GND 100 P0 101 AUX1 102 AUX0 103 ETU1 104 ETU0 105 EIS 106 EIZ 107 EIB 108 EIA PIN CONFIGURATION CONVST 109 72 D11 GND 110 71 VDD VDD 111 70 D12 GND 112 69 D13 AVDD 113 68 D14 AVSS 114 67 D15 VIN7 115 66 D16 VREF 116 65 D17 VIN6 117 64 D18 REFCOM 118 63 GND VIN5 119 62 D19 CAPT 120
ADMC401 (Continued from Page 1) data address generators and a program sequencer. The computational units comprise an ALU, a multiplier/accumulator (MAC) and a barrel shifter. The DSP core also adds instructions for bit manipulation, squaring (x2), biased rounding and global interrupt masking. In addition, two flexible double-buffered, bidirectional synchronous serial ports are included in the ADMC401.
ADMC401 INSTRUCTION REGISTER DATA ADDRESS GENERATOR #1 DATA ADDRESS GENERATOR #2 PM ROM 2K 24 BOOT ADDRESS GENERATOR DM RAM 1K 16 PM RAM 2K 24 PROGRAM SEQUENCER 14 PMA BUS 14 DMA BUS 24 PMD BUS POWER DOWN CONTROL LOGIC 2 14 EXTERNAL ADDRESS BUS 24 BUS EXCHANGE EXTERNAL DATA BUS DMD BUS 16 INPUT REGS ALU OUTPUT REGS INPUT REGS INPUT REGS MAC SHIFTER OUTPUT REGS OUTPUT REGS COMPANDING CIRCUITRY CONTROL LOGIC 16 R BUS TIMER TRANSMIT REG TRANSMIT REG RECEIVE REG RECEIVE RE
ADMC401 register. When the value of the counter reaches zero, an interrupt is generated and the count register is reloaded from a 16bit period register (TPERIOD). Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from data memory and program memory. Each DAG maintains and updates four address pointers (I registers). Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value in one of four modify (M) registers.
ADMC401 PIN FUNCTION DESCRIPTION INTERRUPT OVERVIEW The ADMC401 is available in an 144-lead TQFP package. Table I contains the pin descriptions. The ADMC401 can respond to different interrupt sources, some of which are internal DSP core interrupts and others from the motor control peripherals. The DSP core interrupts include a: Table I.
ADMC401 0x0000 0x0000 0x0000 2K INTERNAL RAM (BOOTED FROM BYTE-WIDE EPROM) 0x07FF 0x0800 0x0FFF 0x1000 2K INTERNAL ROM (ROMENABLE = 1) OR 2K EXTERNAL (ROMENABLE = 0) 2K EXTERNAL MEMORY 0x07FF 0x0800 0x0FFF 0x1000 0x07FF 0x0800 2K INTERNAL ROM (ROMENABLE = 1) OR 2K EXTERNAL (ROMENABLE = 0) 2K INTERNAL ROM (ROMENABLE DEFAULTS TO 1 DURING RESET) 0x0FFF 0x1000 10K EXTERNAL MEMORY 12K EXTERNAL MEMORY 2K INTERNAL RAM (BOOTED VIA SPORT1) 12K EXTERNAL MEMORY 0x3800 2K INTERNAL RAM 0x3FFF 0x3FFF MMAP
ADMC401 SYSTEM INTERFACE CLOCK SIGNALS The ADMC401 uses an input clock with a frequency equal to half the instruction rate; a 13 MHz input clock yields a 38.5 ns processor cycle (which is equivalent to 26 MHz). Normally instructions are executed in a single processor cycle. All device timing is relative to the internal instruction rate, which is indicated by the CLKOUT signal (when enabled). Throughout this data sheet, the period of the CLKIN signal is denoted by tCKI.
ADMC401 Two control lines indicate the direction of the transfer. Memory read, RD, is active low, signaling a read from external memory and memory write; WR, is active low, signaling a write to external memory. Typically, the PMS line is connected to the CE (chip enable) of the external program memory and the RD line is connected to the CE line of the external data memory. The RD line is connected to the OE (output enable) and the WR line is connected to the WE (write enable) of both memories.
ADMC401 The page length is read first and then bytes are loaded from the top of the page downwards. This causes shorter booting times for shorter pages. The length of the boot page is given as: BUS REQUEST/GRANT page length = (number of 24-bit PM words/8) – 1 That is, a page length of 0 causes the boot address generator to generate byte addresses for eight words that reside in 32 sequential EPROM locations.
ADMC401 Entering Power-Down The power-down sequence is initiated by applying a high-to-low transition on the PWD pin or by setting the power-down force control bit (PDFORCE) of the SPORT1 autobuffer/powerdown control register. The DSP core then vectors to the nonmaskable power-down interrupt vector at address 0x002C. Care must be taken to ensure that multiple power-down interrupts do not occur or else stack overflow may result.
ADMC401 and BSHAN) to the inverting terminal of the two sample and hold amplifiers (SHA) so that external signals can be correctly biased about the nominal operating range of the ADC. ASHAN VIN0 VIN1 VIN2 VIN3 SHA A ADC1(15...0) MUX GAIN VIN4 VIN5 ADC2(15...0) MUX 12-BIT PIPELINE FLASH ADC DATA ADC3(15...0) ADC4(15...0) OUT OF RANGE MUX VIN6 VIN7 ADC0(15...0) SHA B END OF CONVERSION CONTROL SIGNALS ADC5(15...0) ADC6(15...0) ADC7(15...0) ADCXTRA(15...0) ADCOTR(7...0) ADCSTAT(4...
ADMC401 CONVERT START COMMAND +VREF The analog-to-digital conversion process of the ADMC401 may be started by either an internal or an external command. Bit 0 of the ADCCTRL register determines whether internal or external convert start mode is enabled. If Bit 0 of the ADCCTRL register is cleared, internal convert start mode is selected, and the ADC conversion process is started on the rising edge of the PWMSYNC signal.
ADMC401 Table II.
ADMC401 ADC6 is valid and Bit 3 is set when the data in ADC3 and ADC7 is valid. At the start of the next conversion sequence, all bits of the ADCSTAT register are cleared. Additionally, at the end of the complete conversion sequence (when the data in the ADC7 register is valid), a dedicated ADC interrupt is generated. This interrupt can be masked and controlled by the PIC block.
ADMC401 The SENSE pin controls whether the A/D system operates with an internal or an external reference. For operation with the internal reference, the SENSE pin should be tied to the REFCOM pin. In this mode, the internally derived 2 V voltage reference appears at the VREF pin. To operate with an external voltage reference, the SENSE pin should be tied to the AVDD pin and the external voltage reference may be applied at the VREF pin. 0.1 F CAPT 10 F 0.1 F CAPB 0.1 F ADMC401 VREF 10 F 0.
ADMC401 lower harmonic distortion in three-phase PWM inverters. This technique also permits closed loop controllers to change the average voltage applied to the machine windings at a faster rate and so permits faster closed loop bandwidths to be achieved. The operating mode of the PWM block (single or double update mode) is selected by a control bit in MODECTRL register. occurrence of a rising edge of the PWMSYNC pulse and the other is generated on the occurrence of any PWM shutdown action.
ADMC401 For example, for a 26 MHz CLKOUT and a desired PWM switching frequency of 10 kHz (TS = 100 µs), the correct value to load into the PWMTM register is: PWMTM = duty cycles of the PWM signals can be updated only once per PWM period at the start of each cycle. The result is that PWM patterns that are symmetrical about the midpoint of the switching period are produced.
ADMC401 Obviously negative values of TAH and TAL are not permitted and the minimum permissible value is zero, corresponding to a 0% duty cycle. In a similar fashion, the maximum value is TS, corresponding to a 100% duty cycle. cycle of the signals on CH and CL. The duty cycle registers are programmed in integer counts of the fundamental time unit, tCK, and define the desired on-time of the high side PWM signal produced by the three-phase timing unit over half the PWM period.
ADMC401 • Full ON: The PWM for any pair of PWM signals is said to operate in FULL ON when the desired HI side output of the three-phase Timing Unit is in the ON state (LO) between successive PWMSYNC pulses. This state may be entered by virtue of the commanded duty cycle values (in conjunction with the PWMDT register) or by virtue of the correct operation of the pulse deletion circuit.
ADMC401 signals, setting Bit 7 enables crossover on the BH/BL pair of PWM signals and setting Bit 6 enables crossover on the CH/CL pair of PWM signals. If crossover mode is enabled for any pair of PWM signals, the high side PWM signal from the timing unit (AH say) is diverted to the associated low side output of the Output Control Unit so that the signal will ultimately appear at the AL pin.
ADMC401 PWMCHA PWMCHA1 PWMCHA AH PWMCHA2 AH 2 PWMDT 2 PWMDT AL AL [4 (GDCLK+1)] BH PWMTM PWMCHB1 PWMCHB2 PWMTM Figure 26. Typical active LO PWM signals with high frequency gate chopping enabled on both high side and low side switches. BL CH PWMCHC1 PWMCHC2 PWM Polarity Control, PWMPOL Pin The polarity of the PWM signals produced at the output pins AH to CL may be selected in hardware by the PWMPOL pin.
ADMC401 Table V.
ADMC401 register is set and an EIU count error interrupt is generated. An additional status bit is provided in the EIUSTAT register that indicates the initialization state of the EIU. Until the EIUMAXCNT register is written to, the EIU is not initialized. Four status bits in the EIUSTAT register provide the state of the four EIU inputs, EIA, EIB, EIZ and EIS. written to, the encoder interface unit is not initialized and Bit 2 of the EIUSTAT register is set.
ADMC401 rate of 1.08 MHz. In general, the maximum encoder rate that can be consistently recognized is given by: f ENCMAX = each edge. This (A signal leads the B signal) is defined as the forward direction of motion. Setting Bit 0 of the EIUCTRL register causes the signal at the EIA pin to be fed to the B input to the quadrature counter and the signal EIB becomes the A input to the quadrature counter.
ADMC401 moving in the reverse direction, the zero marker is recognized at the falling edge of the signal at the EIZ pin. When the ZERO bit of the EIUCTRL register is cleared, the zero marker is not used to reset the counter. In this mode, the contents of the EIUMAXCNT register are used as the reset value for the up/down counter. For example, for an N-line incremental encoder, the appropriate value to write to the EIUMAXCNT register is 4N–1.
ADMC401 asynchronous timing of encoder and DSP-reading events. As a result, more accurate computations of the position and velocity of the motor shaft may be performed. The EET consists of a 16-bit encoder event timer, an encoder pulse decimator and a clock divider. The EET clock frequency is selected by the 16-bit read/write EETDIV clock divide register, whose value divides the CLKOUT frequency. The contents of the encoder event timer are incremented on each rising edge of the divided clock signal.
ADMC401 Table VI. Fundamental Characteristics of Encoder Interface Unit of ADMC401 (At 26 MHz) Parameter fENC fQUAD Test Conditions Encoder Input (EIA, EIB) Rate Quadrature Rate Encoder Loop Timer Timeout Rate Min Typ Max Unit 4.33 17.3 MHz MHz ns sec ns µs 38.5 0.645 TMINENC Minimum Encoder Pulsewidth EIUFILTER = 0x00 EIUFILTER = 0x3F EIU/EET Registers The structure and functionality of the EIU and EET registers are illustrated at the end of the data sheet.
ADMC401 edge on any of them will instantaneously shut down the PWM. However, based on the particular PIO interrupt that is flagged, the user can easily determine the source of the shutdown. This permits the action of the interrupt service routines following a PWM shutdown to be tailored to the particular fault that occurred. On reset, all PIO lines are configured as PWM shutdown sources.
ADMC401 this mode, the AUXTM1 register defines the offset time from the rising edge of the signal on the AUX0 pin to that on the AUX1 pin, according to: ETU REGISTERS The configuration of the ETU registers is shown at the end of the data sheet. TOFFSET = 2 × ( AUXTM1+ 1) × tCK AUXILIARY PWM TIMERS The ADMC401 provides two variable-frequency, variable dutycycle, 8-bit, auxiliary PWM outputs that are available at the AUX1 and AUX0 pins.
ADMC401 of PM. The priority of the peripheral interrupts is fixed in hardware. The ISR at address PM(0x30) has the highest priority whereas the ISR at address PM(0x58) has the lowest. WATCHDOG TIMER OVERVIEW The watchdog timer is used as a protection mechanism against unintentional software events causing the DSP to become stuck in infinite loops. It can be used to cause a complete DSP and peripheral reset in the event of such a software error.
ADMC401 Interrupt Configuration The IFC and ICNTL registers of the DSP core control and configure the interrupt controller of the DSP core. The IFC register is a 16-bit register that may be used to force and/or clear any of the eight DSP interrupts. Bits 0 to 7 of the IFC register may be used to clear the DSP interrupts while Bits 8 to 15 can be used to force a corresponding interrupt. Writing to Bits 11 and 12 in IFC is the only way to create the two software interrupts.
ADMC401 ROM or E2PROM. Clearing the UARTEN bit selects SPORT mode, so that SPORT1 is configured in a manner identical to the standard serial ports of the ADSP-21xx family. Following reset, the UARTEN bit is cleared so that SPORT mode is selected. Bit 6 of the MODECTRL register is used to select between single update and double update operating modes of the PWM generation unit. Clearing this bit selects single update mode, while setting it selects double update mode.
ADMC401 Table VIII. Peripheral Register Map of the ADMC401 Address 0x2000–0x2007 0x2008 0x2009 0x200A 0x200B 0x200C 0x200D 0x200E 0x200F 0x2010 0x2011 0x2012 0x2013 0x2014 0x2015 0x2016 0x2017 0x2018 0x2019–0x201B 0x201C 0x201D 0x201E–0x201F 0x2020 0x2021 0x2022 0x2023 0x2024 0x2025 0x2026 0x2027 0x2028 0x2029 0x202A 0x202B–0x202F 0x2030 0x2031 0x2032 0x2033 0x2034 0x2035 0x2036 0x2037 0x2038 0x2039 0x203A 0x203B 0x203C 0x203D–0x203F 0x2040 0x2041 0x2042 0x2043 0x2044 0x2045 REV.
ADMC401 Address Name Type Bits Reset Value Function 0x2046 0x2047 0x2048–0x204F 0x2050 0x2051 0x2052 0x2053 0x2054 0x2055 0x2056 0x2057–0x205B 0x205C 0x205D 0x205E 0x205F 0x2060 0x2061 0x2062–0x206F 0x2070 0x2071 0x2072 0x2073 0x2074 0x2075–0x23FF PIOINTEN PIOFLAG R/W R [11 . . . 4] [11 . . . 4] 0x000 ETUA0 ETUB0 ETUAA0 ETUA1 ETUB1 ETUAA1 ETUTIME R R R R R R R [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . .
ADMC401 ADC0 (R) ADC1 (R) ADC2 (R) ADC3 (R) ADC4 (R) ADC5 (R) ADC6 (R) ADC7 (R) ADCXTRA(R) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 3 2 1 0 DM (0x2030) DM (0x2031) DM (0x2032) DM (0x2033) DM (0x2034) DM (0x2035) DM (0x2036) DM (0x2037) DM (0x203B) ADC DATA ADCOTR (R) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 = IN RANGE 1 = OUT OF RANGE 7 6 5 4 DM (0x203C) ADC7 OTR ADC0 OTR ADC6 OTR ADC1 OTR ADC5 OTR ADC2 OTR ADC4 OTR ADC3 OTR 0 = IN RANGE 1 = OUT OF
ADMC401 PWMCHA (R/W) PWMCHB (R/W) PWMCHC (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x200C) DM (0x200D) DM (0x200E) PWMTM (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0
ADMC401 EIUCNT (R/W) EIUMAXCNT (R/W) EIUPERIOD (R/W) EIUTIMER (R/W) EETCNT (R) 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 4 3 2 1 0 DM (0x2020) DM (0x2021) DM (0x2024) DM (0x2026) DM (0x2027) EIUSCALE (R/W) 7 6 5 DM (0x2025) EIUSTAT (R) 1 = RECEIVED 0 = NOT RECEIVED 7 6 5 4 3 2 1 0 DM (0x2022) FIRST ZERO MARKER EIS STATE 1 = HI 0 = LO EIZ STATE EIU COUNT ERROR 1 = ERR
ADMC401 EIUFILTER (R/W) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DM (0x2028) ENCODER FILTER CLOCK DIVIDE VALUE EIZLATCH (R) EISLATCH (R) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x2029) DM (0x202A) EETDIV (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 DM (0x2071) EETDELTAT (R) EETT (R) 15 14 13 12 11 10 9 8 7 6 DM (0x2072) DM (0x2073) EETN
ADMC401 PIOLEVEL (R/W) 0 = FALLING EDGE (PIOMODE = 0) = ACTIVE LOW (PIOMODE = 1) 1 = RISING EDGE (PIOMODE = 0) = ACTIVE HIGH (PIOMODE = 1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0
ADMC401 ETUA0 (R) ETUB0 (R) ETUAA0 (R) ETUA1 (R) ETUB1 (R) ETUAA1 (R) ETUTIME (R) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x2050) – DM (0x2056) ETUCONFIG (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x205C) ETU1 MODE 0 = SINGLE SHOT 1 = FREE-RUNNING ETU0 EVENT A 0 = FALLING EDGE 1 = RISING EDGE ETU1 INTERRUPT 0 = NEXT EVENT A 1 = EVENT B ETU0 EVENT B 0 = FALLING EDGE 1 = RISING EDGE ETU1 EVENT B 0 = FALLING EDGE 1 = RI
ADMC401 AUXCH0 (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2010) TON, AUX0 = 2 AUXCH0 tCK AUXCH1 (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2011) TAUX1 = 2 AUXCH1 tCK AUXTM0 (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DM (0x2012) TON, AUX0 = 2 (AUXTM0+1) tCK AUXTM1 (R/W) 15 14 13 12 1
ADMC401 MODECTRL (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 = INDEPENDENT 0 = OFFSET DATA RECEIVE SELECT AUXILIARY PWM MODE 1 = DOUBLE UPDATE 0 = SINGLE UPDATE PWM MODE DM (0x2015) 1 = DR1B 0 = DR1A SPORT1 MODE 1 = UART MODE 0 = SPORT MODE SYSSTAT (R) 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 1 = SECOND HALF CYCLE 0 = FIRST HALF CYCLE 3 PWM PHASE FLAG 2 1 0 DM (0x2016) PWMTRIP PIN STATE 1 =
ADMC401 IMASK (R/W) ICNTL (R/W) 4 3 0 2 1 0 DSP REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP REGISTER 1 = ENABLE, 0 = DISABLE IRQ0 SENSITIVITY IRQ1 SENSITIVITY IRQ2 SENSITIVITY IRQ2 HIP WRITE HIP READ SPORT0 TRANSMIT SPORT0 RECEIVE 1 = EDGE 0 = LEVEL INTERRUPT NESTING 1 = ENABLE, 0 = DISABLE TIMER IRQ0 or SPORT1 RECEIVE IRQ1 or SPORT1 TRANSMIT SOFTWARE 0 SOFTWARE 1 IFC (R/W) 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3
ADMC401 ASTAT (R/W) SSTAT (R) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 DSP REGISTER 7 6 5 4 3 2 1 0 0 1 0 1 0 1 0 1 AZ ALU RESULT ZERO AN ALU RESULT NEGATIVE AV ALU OVERFLOW AC ALU CARRY AS ALU X INPUT SIGN AQ ALU QUOTIENT MV MAC OVERFLOW SS SHIFTER INPUT SIGN DSP REGISTER PC STACK EMPTY PC STACK OVERFLOW COUNT STACK EMPTY COUNT STACK OVERFLOW STATUS STACK EMPTY STATUS STACK OVERFLOW LOOP STACK EMPTY LOOP STACK OVERFLOW MSTAT (R/W) 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DSP RE
ADMC401 MEMWAIT (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DWAIT4 DWAIT3 DWAIT2 ROM ENABLE 1 = ENABLE 0 = DISABLE DWAIT1 DM (0x3FFE) DWAIT0 NOTE: IN STANDALONE MODE (MMAP = BMODE = 1) THE ROM MONITOR WRITES 0x8000 TO THIS REGISTER.
ADMC401 SPORT0_SCLKDIV (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x3FF5) SPORT0_RFSDIV (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x3FF4) SPORT0_AUTOBUF_CTRL (R/W) 15 14 13 12 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 DM (0x3FF3) RBUF RECEIVE AUTOBUFFERING ENABLE CLKODIS CLKOUT DISABLE CONTROL BIT TBUF TRANSMIT AUTOBUFFERING ENABLE BIASRND MAC BIASED ROUNDING CONTROL BIT TIREG TRANSMIT AUTOBUFFER I REGISTER RMREG RECEIVE AUTOBUFFER M REGIS
ADMC401 SPORT1_SCLKDIV (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x3FF1) SPORT1_RFSDIV (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x3FF0) SPORT1_AUTOBUF_CTRL (R/W) 15 14 13 12 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 DM (0x3FEF) RBUF RECEIVE AUTOBUFFER ENABLE TBUF TRANSMIT AUTOBUFFER ENABLE RMREG RECEIVE M REGISTER XTALDELAY 4096 CYCLE DELAY ENABLE 1 = DELAY, 0 = NO DELAY RIREG RECEIVE I REGISTER PDFORCE POWERDOWN FORCE TMREG TRANSMIT M REG
ADMC401 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.063 (1.60) MAX 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) C3491b–1.5–6/00 (rev. B) 00108 144-Lead Plastic Thin Quad Flatpack (LQFP) ST-144 0.866 (22.00) BSC SQ 0.787 (20.00) BSC SQ 109 144 1 108 SEATING PLANE TOP VIEW (PINS DOWN) 0.003 (0.08) MAX 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.40) 0.048 (1.35) 73 36 72 37 0.020 (0.50) BSC 0.011 (0.27) 0.009 (0.22) 0.007 (0.17) PRINTED IN U.S.A. Only dimensions in mm are accurate.
