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Energy Metering IC with Autocalibration

Data Sheet

ADE9153A

Rev. 0

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FEATURES

mSure autocalibration

Automatic calibration based on a direct measurement of

the full signal path

Calibration procedure not requiring a reference meter

mSure autocalibration Class 1 meter guaranteed

3 high performance ADCs

88 dB SNR

High gain current channel: ±26.04 mV peak, 18.4 mV rms

input at highest gain setting

Advanced metrology feature set

WATT, VAR, VA, Wh, VARh, and VAh

Supports active energy standards: IEC 62053-21;

IEC 62053-22; EN50470-3; OIML R46; and ANSI C12.20

Supports reactive energy standards: IEC 62053-23 and

IEC 62053-24

Current and voltage rms measurement

Power quality measurements

Operating temperature, industrial range: −40°C to +85°C

APPLICATIONS

Single-phase energy meters

Energy and power measurement

Street lighting

Smart power distribution system

Machine health

GENERAL DESCRIPTION

The ADE9153A

is a highly accurate, single-phase, energy metering

IC with autocalibration. The mSure® autocalibration feature allows

a meter to automatically calibrate the current and voltage channels

without using an accurate source or an accurate reference meter

when a shunt resistor is used as a current sensor. Class 1 and

Class 2 meters are supported by mSure autocalibration.

The ADE9153A incorporates three high performance analog-

to-digital converters (ADCs), providing an 88 dB signal-to-noise

ratio (SNR). The ADE9153A offers an advanced metrology feature

set of measurements like line voltage and current, active energy,

fundamental reactive energy, and apparent energy calculations,

and current and voltage rms calculations. ADE9153A includes

power quality measurements such as zero crossing detection, line

period calculation, angle measurement, dip and swell, peak and

overcurrent detection, and power factor measurements. Each input

channel supports independent and flexible gain stages. Current

Channel A is ideal for shunts, having a flexible gain stage and

providing full-scale input ranges from 62.5 mV peak down to

26.04 mV peak. Current Channel B has gain stages of 1×, 2×,

and 4× for use with current transformers (CTs). A high speed,

10 MHz, serial peripheral interface (SPI) port allows access to

the ADE9153A registers.

Note that throughout this data sheet, multifunction pins, such

as ZX/DREADY/CF2, are referred to either by the entire pin

name or by a single function of the pin, for example, CF2, when

only that function is relevant.

The ADE9153A operates from a 3.3 V supply and is available in

a 32-lead LFCSP package.

TYPICAL APPLICATIONS CIRCUIT

mSure VOLTAGE DRIVER

DIGITAL SIGNAL

PROCESSING

SINC AND

DECIMATION

METROLOGY ENGINE

WATT, VA, VAR,

WATT-HR, VA-HR,

VAR-HR, IRMS, VRMS

mSure DETECTOR

SAR

TEMPERATURE

SENSOR

CLOCK

GENERATION

ZERO

CROSSING

SPI

INTERFACE

CLKIN

CLKOUT

CF1

ZX/DREADY/CF2

SCLK

MISO/TX

MOSI/RX

AGND/DGND

VAMS

VAN

VAP

AGND/DGND

IAN

IAP

IAMS

IBMS

IBP

IBN

AGND/DGND

SHUNT

BIG

SMALL

PHASENEUTRAL

IRQ

ADC

PGA

mSure

CURRENT DRIVER

ADCPGA

ADE9153A

LOAD

16519-001

Figure 1.

Protected by U.S. Patents 8,350,558; 8,010,304; WO2013038176 A3; 0113507 A1; 0253102 A1; 0354266 A1; and 0154029 A1.

Downloaded from Arrow.com.

Summary of content (50 pages)

PAGE 1
Energy Metering IC with Autocalibration ADE9153A Data Sheet FEATURES GENERAL DESCRIPTION mSure autocalibration Automatic calibration based on a direct measurement of the full signal path Calibration procedure not requiring a reference meter mSure autocalibration Class 1 meter guaranteed 3 high performance ADCs 88 dB SNR High gain current channel: ±26.04 mV peak, 18.
PAGE 2
ADE9153A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 mSure Autocalibration Feature................................................. 21 Applications ....................................................................................... 1 Measurements ............................................................................. 22 General Description ...............................................................
PAGE 3
Data Sheet ADE9153A SPECIFICATIONS VDD = 2.97 V to 3.63 V, AGND = DGND = 0 V, on-chip reference, CLKIN = 12.288 MHz, TMIN to TMAX = −40°C to +85°C, and TA = 25°C (typical), unless otherwise noted. Table 1.
PAGE 4
ADE9153A Parameter ADC PGA Gain Settings (xI_PGAGAIN) Current Channel A (Phase Shunt) Current Channel B (Neutral CT) Pseudo Differential Input Voltage Range (IAP − IAN) (VAP − VAN) Differential Input Voltage Range (IBP − IBN) Maximum Operating Voltage on the Analog Input Pins VAP IAP, IAN IBP, IBN SNR Current Channel A AI_PGAGAIN = 16× AI_PGAGAIN = 38.4× Current Channel B BI_PGAGAIN = 1x BI_PGAGAIN = 4x Voltage Channel ADC Output Pass Band (0.
PAGE 5
Data Sheet Parameter Channel Drift (PGA, ADC, Internal Voltage Reference) Current Channel A Current Channel B Voltage Channel Differential Input Impedance (DC) Current Channel A Current Channel B Voltage Channel INTERNAL VOLTAGE REFERENCE Voltage Reference Temperature Coefficient ADE9153A Min Max Unit ±5 ±20 ±20 ±30 ±50 ±50 ppm/°C ppm/°C ppm/°C 5000 100 240 7800 113 256 kΩ kΩ kΩ 1.25 ±5 ±30 V ppm/°C 0.3 °C °C ±5 12.287 12.288 4 12.289 MHz pF 2.58 MΩ 5 8.7 mA/V 12.287 45:55 12.
PAGE 6
ADE9153A Parameter POWER SUPPLY VDD Pin VDD Pin Current, IDD Data Sheet Min Typ 2.97 9.3 8.5 Max Unit 3.63 12 V mA μA Test Conditions/Comments For specified performance Minimum = 3.3 V − 10%; maximum = 3.3 V + 10% Consumption in operation, without mSure running When the ADE9153A is held in reset AUTOCALIBRATION VDD = 3.3 V, AGND = DGND = 0 V, on-chip reference, CLKIN = 12.
PAGE 7
Data Sheet ADE9153A SPI TIMING CHARACTERISTICS Table 3.
PAGE 8
ADE9153A Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 4.
PAGE 9
Data Sheet ADE9153A 32 31 30 29 28 27 26 25 SS SCLK MISO/TX MOSI/RX RESET IRQ CF1 ZX/DREADY/CF2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADE9153A TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 VDD FA0 FA1 MSH DGND IBMS REFIN AGND NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE LEFT FLOATING. 16519-003 AGND VDDOUT2P5 IBN IBP VAMS VAP VAN AVDDOUT 9 10 11 12 13 14 15 16 DGND DVDDOUT CLKOUT CLKIN VDD IAMS IAN IAP Figure 3. Pin Configuration Table 6.
PAGE 10
ADE9153A Pin No. 18 Mnemonic REFIN 19 IBMS 21 MSH 22 23 25 FA1 FA0 ZX/DREADY/CF2 26 CF1 27 IRQ 28 29 30 31 RESET MOSI/RX MISO/TX SCLK 32 SS EPAD Data Sheet Description Voltage Reference. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.25 V. Decouple this pin to Pin 17 (AGND) with a 0.1 μF ceramic capacitor in parallel with a 4.7 μF ceramic capacitor. After reset, the on-chip reference is enabled. An external reference source with 1.
PAGE 11
Data Sheet ADE9153A TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE Energy characteristics obtained from a 50% of full scale, sinusoidal, 50 Hz voltage signal; the sinusoidal, 50 Hz, swept amplitude current signal is from 100% of full scale to 0.01% of full scale. 0.50 0.25 0 –0.25 –0.25 –0.50 –0.50 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 4.
PAGE 12
ADE9153A 0.75 0.25 0.25 ERROR (%) 0.50 0 0 –0.25 –0.25 –0.50 –0.50 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 10. Total Active Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 1, TA = 25°C, AI PGA Gain = 16× 0.75 0.50 –0.75 0.01 16519-110 –0.75 0.01 0.75 2.97V 3.3V 3.63V 0.50 ERROR (%) ERROR (%) 100 2.97V 3.3V 3.63V 0 –0.25 –0.25 –0.50 –0.50 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) –0.75 0.01 16519-111 –0.
PAGE 13
Data Sheet ADE9153A ENERGY ERROR OVER FREQUENCY AND POWER FACTOR Energy characteristics obtained from a 50% of full scale, sinusoidal, 50 Hz voltage signal and a 10% of full scale, sinusoidal, 50 Hz, current signal over a variable frequency between 45 Hz and 65 Hz. 0.10 0.10 POWER FACTOR = +1 POWER FACTOR = +0.5 POWER FACTOR = –0.5 0.05 ERROR (%) 0 –0.05 –0.05 40 45 50 55 60 65 70 LINE FREQUENCY (Hz) Figure 16. Total Active Energy Error vs. Line Frequency, Power Factor = −0.5, +0.
PAGE 14
ADE9153A Data Sheet RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY RMS linearity obtained with a sinusoidal, 50 Hz current and voltage signals with a swept amplitude from 100% of full scale to 0.033% of full scale. 0.50 0.25 0 0 –0.25 –0.25 –0.50 –0.50 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 19. Current Channel A RMS Error as a Percentage of Full-Scale Current over Temperature, AI PGA Gain = 16× 0.50 –0.75 0.01 16519-126 –0.75 0.01 0.
PAGE 15
Data Sheet ADE9153A 0.75 0.10 TA = –40°C TA = +25°C TA = +85°C 0.50 0.05 ERROR (%) ERROR (%) 0.25 0 0 –0.25 –0.05 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) –0.10 16519-132 –0.75 0.01 50 55 60 65 70 Figure 27. Current Channel A RMS Error vs. Line Frequency 0.10 TA = –40°C TA = +25°C TA = +85°C 0.50 45 LINE FREQUENCY (Hz) Figure 25. Current Channel B RMS Offset Error as a Percentage of Full-Scale Current over Temperature 0.75 40 16519-134 –0.50 0.
PAGE 16
ADE9153A Data Sheet 0.05 0.05 ERROR (%) 0.10 0 45 50 55 60 65 70 LINE FREQUENCY (Hz) –0.10 16519-136 40 50 55 60 65 70 LINE FREQUENCY (Hz) 0.10 0.05 0.05 ERROR (%) 0.10 ERROR (%) 45 Figure 31. Current Channel B RMS Overcurrent Error vs. Line Frequency Figure 29. Voltage Channel RMS Error vs. Line Frequency 0 0 –0.05 –0.05 40 45 50 55 60 LINE FREQUENCY (Hz) 65 70 –0.10 16519-137 –0.10 40 16519-138 –0.05 –0.05 –0.10 0 Figure 30.
PAGE 17
Data Sheet ADE9153A 100 98 98 96 96 94 94 90 90 88 88 86 –25 –20 –15 –10 –5 0 5 INPUT SIGNAL (dBFS) 86 –25 98 98 96 96 94 94 SNR (dB) 100 92 88 88 –10 –5 INPUT SIGNAL (dBFS) 0 5 16519-142 90 –15 Figure 34. Current Channel A SNR with Respect to Full Scale, AI PGA Gain = 38.4× Rev. 0 | Page 17 of 50 Downloaded from Arrow.com. –10 –5 0 5 92 90 –20 –15 Figure 35. Current Channel B SNR with Respect to Full Scale 100 86 –25 –20 INPUT SIGNAL (dBFS) Figure 33.
PAGE 18
ADE9153A Data Sheet TEST CIRCUIT 2 4.7µF DVDDOUT 0.1µF 5 24 VDD PHASE 0.1µF VDD 4.7µF 4.7µF AVDDOUT 16 0.1µF 150Ω 7 IAN REFIN 18 0.1µF SHUNT 0.1µF 4.7µF 0.1µF 4.7µF FA1 22 0.1µF 150Ω 8 IAP 6 IAMS ZX/DREADY/CF2 25 TO MCU CF1 26 TO MCU IRQ 27 TO MCU RESET 28 TO MCU MOSI/RX 29 TO MCU MISO/TX 30 TO MCU SCLK 31 TO MCU SS 32 TO MCU 10 VDDOUT2P5 4.7µF TO LOAD NEUTRAL 0.1µF 150Ω ADE9153A 11 IBN 0.1µF Rb 0.1µF 150Ω 0.
PAGE 19
Data Sheet ADE9153A TERMINOLOGY Crosstalk Crosstalk is measured by grounding one channel and applying a full-scale 50 Hz or 70 Hz signal on all the other channels. The crosstalk is equal to the ratio between the grounded ADC output value and its ADC full-scale output value. The ADC outputs are acquired for 200 sec. Crosstalk is expressed in decibels.
PAGE 20
ADE9153A Data Sheet Absolute Accuracy Absolute accuracy takes into account the accuracy of the mSure reference. The speed of convergence to reach this accuracy depends on the time of an mSure autocalibration run. The longer the time of an mSure autocalibration run, the greater the accuracy. Conversion Constant In this data sheet, the conversion constant (CC) is the value that mSure returns when estimating the transfer function of the sensor and front end.
PAGE 21
Data Sheet ADE9153A THEORY OF OPERATION The ADE9153A offers mSure autocalibration technology, enabling the automatic calibration of the current and voltage channel accurate, automatic calibration. Autocalibration features have two main components: absolute accuracy and the speed of convergence (see the Terminology section for more details). When performing autocalibration, the current channels, AI and BI, can be run in two power modes: turbo mode and normal mode.
PAGE 22
ADE9153A Data Sheet MEASUREMENTS 1501:1 1001:1 619:1 0.500 Current Channel The ADE9153A has two current channels. Channel A is optimized for use with a shunt, and Channel B is for use with a current transformer. The current channel datapaths for Channel A and Channel B are shown in Figure 42 and Figure 43, respectively. 0.400 0.353 0.300 0.250 Current Channel Gain, xIGAIN 0.200 The ADE9153A provides current gain calibration registers, AIGAIN and BIGAIN, with one register for each channel. 0.
PAGE 23
Data Sheet ADE9153A High-Pass Filter A high-pass filter removes dc offsets for accurate rms and energy measurements. This filter is enabled by default and features a corner frequency of 1.25 Hz. To disable the high-pass filter on all current and voltage channels, set the HPFDIS bit in the CONFIG0 register. The corner frequency is configured with the HPF_CRN bits in the CONFIG2 register.
PAGE 24
ADE9153A Data Sheet The total active power calculation, AWATT, is updated every 4 kSPS. With full-scale inputs, the AWATT value is 10,356,306 codes. The total apparent power calculation, AVA, is updated every 4 kSPS. With full-scale inputs, the AVA value is 10,356,306 codes. LPF2 is enabled by default (DISRPLPF = 0) and must be set to this default value for typical operation. Disable LPF2 by setting the DISRPLPF bit in the CONFIG0 register.
PAGE 25
Data Sheet ADE9153A power changes, the corresponding REVx bits in the status register are set and IRQ generates an interrupt. Reset Energy Register on Read The user can reset the energy register on a read using the RD_RST_EN bit in the EP_CFG register. In this way, the value in the user energy register is reset when it is read.
PAGE 26
ADE9153A Data Sheet Digital to Frequency Conversion—CFx Output POWER QUALITY MEASUREMENTS The ADE9153A includes two pulse outputs on the CF1 and CF2 output pins that are proportional to the energy accumulation. The block diagram of the CFx pulse generation is shown in Figure 50. CF2 is multiplexed with ZX and DREADY. Zero-Crossing Detection Calibration Frequency (CF) Energy Selection The ADE9153A offers zero-crossing detection on the voltage and both current channels.
PAGE 27
Data Sheet ADE9153A The zero-crossing detection circuits have two different output rates: 4 kSPS and 512 kSPS. The 4 kSPS zero-crossing signal calculates the line period, updates the ZXx bits in the status register, and monitors the zero-crossing timeout and energy accumulation functions. The 512 kSPS zero-crossing signal calculates the angle and updates the zero-crossing output on the CF2/ZX/ DREADY pin.
PAGE 28
ADE9153A Data Sheet The ADE9153A monitors the rms½ value on current channels to determine overcurrent events. If an rms½ current is greater than the user configured threshold in the OI_LVL register, the OIx bit in the EVENT_STATUS register is set. The overcurrent event generates an interrupt on the IRQ pin. The OIx_EN bits in the CONFIG3 register select the current channel to monitor for overcurrent events. The OIx bits in the EVENT_STATUS register indicate which current channel exceeded the threshold.
PAGE 29
Data Sheet ADE9153A APPLICATIONS INFORMATION INTERRUPTS/EVENTS For the Tier 1 status register bits, Bits[25:0], The ADE9153A has two pins, IRQ and ZX/DREADY/CF2, that can be used as interrupts to the host processor. 1. 2. IRQ PIN INTERRUPTS For the Tier 2 status register bits, Bits[31:29], The IRQ pin goes low when an enabled interrupts occurs and stays low until the event is acknowledged by setting the corresponding status bit in the status register.
PAGE 30
ADE9153A Data Sheet ACCESSING ON-CHIP DATA The UART communication is comprised of 11-bit frames with one start bit, eight data bits, one odd parity bit, and one stop bit. 10 9 SPI PROTOCOL OVERVIEW The ADE9153A has an SPI-compatible interface consisting of four pins: SCLK, MOSI/RX, MISO/TX, and SS. The ADE9153A is always an SPI slave; it never initiates a SPI communication. The SPI interface is compatible with 16-bit and 32-bit read/write operations.
PAGE 31
Data Sheet ADE9153A COMMUNICATION VERIFICATION REGISTERS CONFIGURATION LOCK The ADE9153A includes three register that allow SPI operation verification. The LAST_CMD (Address 0x4AE), LAST_DATA_16 (Address 0x4AC), and LAST_DATA_32 (Address 0x423) registers record the received CMD_HDR and the last read or transmitted data. The configuration lock feature prevents changes to the ADE9153A configuration. To enable this feature, write 0x3C64 to the WR_LOCK register. To disable the feature, write 0x4AD1.
PAGE 32
ADE9153A Data Sheet REGISTER INFORMATION REGISTER SUMMARY Table 8.
PAGE 33
Data Sheet Address 0x210 Name BI_WAV 0x212 0x219 BIRMS BIRMS_OC 0x220 0x221 0x222 0x223 0x224 0x225 0x240 MS_ACAL_AICC MS_ACAL_AICERT MS_ACAL_BICC MS_ACAL_BICERT MS_ACAL_AVCC MS_ACAL_AVCERT MS_STATUS_CURRENT 0x241 VERSION_DSP 0x242 0x39D VERSION_PRODUCT AWATT_ACC 0x39E AWATTHR_LO 0x39F AWATTHR_HI 0x3B1 AVA_ACC 0x3B2 AVAHR_LO 0x3B3 AVAHR_HI 0x3BB AFVAR_ACC 0x3BC AFVARHR_LO 0x3BD AFVARHR_HI 0x3EB PWATT_ACC 0x3EF NWATT_ACC 0x3F3 PFVAR_ACC 0x3F7 NFVAR_ACC 0x400 0x401 0x402 0x40
PAGE 34
ADE9153A Address 0x40F Name VLEVEL 0x410 0x411 0x414 0x415 0x418 0x41C 0x41D 0x41E 0x41F 0x420 DIP_LVL DIPA SWELL_LVL SWELLA APERIOD ACT_NL_LVL REACT_NL_LVL APP_NL_LVL PHNOLOAD WTHR 0x421 0x422 VARTHR VATHR 0x423 LAST_DATA_32 0x424 CT_PHASE_MEAS 0x425 0x471 CF_LCFG TEMP_TRIM 0x472 0x473 0x480 0x481 0x485 CHIP_ID_HI CHIP_ID_LO Run CONFIG1 ANGL_AV_AI 0x488 ANGL_AI_BI 0x48B 0x48C 0x490 0x491 0x492 0x493 0x494 0x495 0x498 0x499 0x49A 0x49D 0x4A8 0x4A9 DIP_CYC SWELL_CYC CFMODE COMPMODE ACCMODE C
PAGE 35
Data Sheet Address 0x4B0 0x4B1 0x4B2 0x4B4 0x4B6 0x4B7 0x4B9 0x4BF 0x4C0 Name EP_CFG PWR_TIME EGY_TIME CRC_FORCE TEMP_CFG TEMP_RSLT AI_PGAGAIN WR_LOCK MS_STATUS_IRQ 0x4C1 EVENT_STATUS 0x4C2 CHIP_STATUS 0x4DC UART_BAUD_SWITCH 0x4FE 0x600 0x601 Version AI_WAV_1 AV_WAV_1 0x602 0x604 0x605 0x606 0x608 0x60A 0x60C 0x60E 0x610 0x611 0x612 0x613 0x614 0x615 0x616 0x617 0x618 0x61A BI_WAV_1 AIRMS_1 BIRMS_1 AVRMS_1 AWATT_1 AFVAR_1 AVA_1 APF_1 AI_WAV_2 AV_WAV_2 AIRMS_2 AVRMS_2 AWATT_2 AVA_2 AFVAR_2 APF_2 B
PAGE 36
ADE9153A Data Sheet REGISTER DETAILS Table 9. Register Details Addr. 0x020 Name CONFIG0 Bits [31:10] 9 8 Bit Name Reserved Reserved DISRPLPF 7 DISAPLPF 6 5 Reserved VNOMA_EN 4 RMS_OC_SRC Settings 0 1 3 ZX_SRC_SEL 0 1 0x023 BI_PGAGAIN 2 INTEN_BI 1 0 RESERVED HPFDIS [31:0] BI_GAIN 0 1 10 Rev. 0 | Page 36 of 50 Downloaded from Arrow.com. Description Reserved. Reserved. Set this bit to disable the low-pass filter in the fundamental reactive power datapath.
PAGE 37
Data Sheet Addr. 0x030 Name MS_ACAL_CFG ADE9153A Bits [31:7] 6 Bit Name Reserved AUTOCAL_AV 5 AUTOCAL_BI 4 AUTOCAL_AI 3 ACALMODE_BI Settings 0 1 2 ACALMODE_AI 0 1 1 ACAL_RUN 0 ACAL_MODE 0x240 MS_STATUS_CURRENT [31:1] 0 Reserved MS_SYSRDYP 0x400 IPEAK [31:27] [26:24] Reserved IPPHASE [23:0] IPEAKVAL [31:24] [23:0] Reserved VPEAKVAL 0x401 VPEAK Rev. 0 | Page 37 of 50 Downloaded from Arrow.com. Description Reserved. Enable autocalibration on the voltage channel.
PAGE 38
ADE9153A Addr. 0x402 Name Status Data Sheet Bits 31 Bit Name CHIP_STAT 30 EVENT_STAT 29 MS_STAT [28:26] 25 Reserved PF_RDY 24 CRC_CHG 23 CRC_DONE 22 21 Reserved ZXTOAV 20 ZXBI 19 ZXAI 18 17 Reserved ZXAV 16 RSTDONE Settings Rev. 0 | Page 38 of 50 Downloaded from Arrow.com. Description When set, this indicates a bit in the CHIP_STATUS register is set. This bit is cleared when CHIP_STATUS is read. When set, this indicates a bit in the EVENT_STATUS register is set.
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Data Sheet Addr. Name ADE9153A Bits 15 Bit Name FVARNL 14 VANL 13 WATTNL 12 TEMP_RDY 11 RMS_OC_RDY 10 PWRRDY 9 DREADY 8 EGYRDY 7 CF2 6 CF1 5 REVPCF2 4 REVPCF1 3 Reserved Settings Rev. 0 | Page 39 of 50 Downloaded from Arrow.com. Description This bit is set when fundamental reactive energy enters or exits the no load condition. This bit is set when total apparent energy enters or exits the no load condition.
PAGE 40
ADE9153A Addr. 0x405 Name Mask Data Sheet Bits 2 Bit Name REVRPA 1 0 Reserved REVAPA 31 CHIP_STAT 30 EVENT_STAT 29 MS_STAT [28:26] 25 Reserved PF_RDY 24 CRC_CHG 23 CRC_DONE 22 21 Reserved ZXTOAV 20 ZXBI Settings Rev. 0 | Page 40 of 50 Downloaded from Arrow.com. Description This bit indicates if the Phase A fundamental reactive power changed sign. This bit is updated when the power value in the AFVAR_ACC register updates, after PWR_TIME 4 kSPS samples. Reserved.
PAGE 41
Data Sheet Addr. Name ADE9153A Bits 19 Bit Name ZXAI 18 17 Reserved ZXAV 16 15 Reserved FVARNL 14 VANL 13 WATTNL 12 TEMP_RDY 11 RMS_OC_RDY 10 PWRRDY 9 DREADY 8 EGYRDY 7 CF2 6 CF1 5 REVPCF2 Settings Rev. 0 | Page 41 of 50 Downloaded from Arrow.com. Description Set this bit to enable an interrupt when a zero crossing is detected on Current Channel A. Reserved. Set this bit to enable an interrupt when a zero crossing is detected on the voltage channel. Reserved.
PAGE 42
ADE9153A Addr. Name Data Sheet Bits 4 Bit Name REVPCF1 3 2 Reserved REVRPA 1 0 Reserved REVAPA 0x409 OI_LVL [31:24] [23:0] Reserved OILVL_VAL 0x40A OIA [31:24] [23:0] Reserved OIA_VAL 0x40B OIB [31:24] [23:0] Reserved OIB_VAL 0x40F VLEVEL [31:24] [23:0] Reserved VLEVEL_VAL 0x411 DIPA [31:24] [23:0] Reserved DIPA_VAL 0x415 SWELLA [31:24] [23:0] Reserved SWELLA_VAL 0x41F PHNOLOAD [31:3] 2 Reserved AFVARNL 1 AVANL 0 AWATTNL Settings Rev.
PAGE 43
Data Sheet Addr. 0x425 0x471 0x481 Name CF_LCFG TEMP_TRIM CONFIG1 ADE9153A Bits [31:21] 20 Bit Name Reserved CF2_LT Settings 19 CF1_LT [18:0] CF_LTMR [31:16] TEMP_OFFSET [15:0] TEMP_GAIN 15 EXT_REF 14 DIP_SWELL_IRQ_MODE 0 1 [13:12] 11 Reserved BURST_EN 10 [9:8] Reserved PWR_SETTLE 0 1 10 11 [7:6] 5 Reserved CF_ACC_CLR Rev. 0 | Page 43 of 50 Downloaded from Arrow.com. Description Reserved. If this bit is set, the CF2 pulse width is determined by the CF_LTMR register value.
PAGE 44
ADE9153A Addr. 0x490 Name CFMODE Data Sheet Bits [4:3] 2 Bit Name Reserved ZX_OUT_OE 1 DREADY_OE 0 SWRST [15:8] 7 Reserved CF2DIS 6 CF1DIS [5:3] CF2SEL Settings 0 10 100 0x492 ACCMODE [2:0] CF1SEL [15:5] 4 Reserved SELFREQ 0 1 [3:2] VARACC 0 1 10 11 [1:0] WATTACC Rev. 0 | Page 44 of 50 Downloaded from Arrow.com. Description Reserved. When this bit is set, ZX is driven to the CF2 pin. When this bit is set, DREADY is driven to the CF2 pin.
PAGE 45
Data Sheet Addr. 0x493 Name CONFIG3 ADE9153A Bits [15:4] [3:2] Bit Name Reserved PEAK_SEL Settings 0 1 10 11 1 OIB_EN 0 OIA_EN 0x49A ZX_CFG [15:1] 0 Reserved DISZXLPF 0x49D PHSIGN [15:8] 7 Reserved CF2SIGN 6 CF1SIGN [5:2] 1 Reserved AVARSIGN 0 AWSIGN Rev. 0 | Page 45 of 50 Downloaded from Arrow.com. Description Reserved. Peak detection phase selection. Phase A and Phase B disabled from voltage and current peak detection.
PAGE 46
ADE9153A Addr. 0x4AF Name CONFIG2 Data Sheet Bits [15:13] 12 Bit Name Reserved UPERIOD_SEL [11:9] HPF_CRN Settings 0 1 10 11 100 101 110 111 0x4B0 EP_CFG [8:0] [15:8] [7:5] Reserved Reserved NOLOAD_TMR 0 1 10 11 100 101 110 111 4 3 Reserved RD_RST_EN 2 EGY_LD_ACCUM Rev. 0 | Page 46 of 50 Downloaded from Arrow.com. Description Reserved. Set this bit to use a user configured line period, in USER_PERIOD, for RMS_OC calculation. If this bit is clear, the voltage line period is used.
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Data Sheet Addr. Name ADE9153A Bits 1 Bit Name EGY_TMR_MODE Settings 0 1 0 EGY_PWR_EN 0x4B4 CRC_FORCE [15:1] 0 Reserved FORCE_CRC_UPDATE 0x4B6 TEMP_CFG [15:4] 3 Reserved TEMP_START 2 TEMP_EN [1:0] TEMP_TIME 0 1 10 11 0x4B7 TEMP_RSLT [15:12] [11:0] Reserved TEMP_RESULT 0x4B9 AI_PGAGAIN [15:5] 4 Reserved AI_SWAP 0 1 Rev. 0 | Page 47 of 50 Downloaded from Arrow.com.
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ADE9153A Addr. Name Data Sheet Bits 3 [2:0] Bit Name Reserved AI_GAIN Settings 10 11 100 101 0x4C0 MS_STATUS_IRQ 15 14 Reserved MS_SYSRDY 13 MS_CONFERR 12 MS_ABSENT 11 10 9 8 7 6 5 4 3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MS_TIMEOUT 2 1 Reserved MS_READY 0 MS_SHIFT Rev. 0 | Page 48 of 50 Downloaded from Arrow.com. Description Reserved. PGA gain for Current Channel A. Gain = 16. Gain = 24. Gain = 32. Gain = 38.4. Reserved.
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Data Sheet Addr. 0x4C1 0x4C2 Name EVENT_STATUS CHIP_STATUS ADE9153A Bits [15:6] 5 Bit Name Reserved OIB 4 OIA 3 2 Reserved SWELLA 1 0 Reserved DIPA [15:8] 7 Reserved UART_RESET 6 UART_ERROR2 5 UART_ERROR1 4 UART_ERROR0 3 ERROR3 2 ERROR2 1 ERROR1 0 ERROR0 Settings Rev. 0 | Page 49 of 50 Downloaded from Arrow.com. Description Reserved. This bit is set when Current Channel B is in an overcurrent condition and is zero when it is not in an overcurrent condition.
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ADE9153A Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 5.10 5.00 SQ 4.90 1 0.50 BSC 3.75 3.60 SQ 3.55 EXPOSED PAD 8 17 TOP VIEW 0.80 0.75 0.70 TOP VIEW PKG-004570 SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 32 25 24 0.50 0.40 0.30 16 9 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.