Datasheet

ManualsBrandsANALOG DEVICES ManualsClock & Timing ICsLFCSP 72 VQ

Dual PLL, Quad Input,

Multiservice

Line Card Adaptive Clock Translator

Data Sheet

AD9559

Rev. C Document Feedback

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FEATURES

Supports GR-1244 Stratum 3 stability in holdover mode

Supports smooth reference switchover with virtually

no disturbance on output phase

Supports Telcordia GR-253 jitter generation, transfer, and

tolerance for SONET/SDH up to OC-192 systems

Supports ITU-T G.8262 synchronous Ethernet slave clocks

Supports ITU-T G.823, G.824, G.825, and G.8261

Auto/manual holdover and reference switchover

Adaptive clocking allows dynamic adjustment of feedback

dividers for use in OTN mapping/demapping applications

Dual digital PLL architecture with four reference inputs

(single-ended or differential)

4x2 crosspoint allows any reference input to drive either PLL

Input reference frequencies from 2 kHz to 1250 MHz

Reference validation and frequency monitoring (2 ppm)

Programmable input reference switchover priority

20-bit programmable input reference divider

4 pairs of clock output pins with each pair configurable as a

single differential LVDS/HSTL output or as 2 single-ended

CMOS outputs

Output frequencies: 262 kHz to 1250 MHz

Programmable 17-bit integer and 23-bit fractional

feedback divider in digital PLL

Programmable digital loop filter covering loop bandwidths

from 0.1 Hz to 2 kHz

Low noise system clock multiplier

Optional crystal resonator for system clock input

On-chip EEPROM to store multiple power-up profiles

Pin program function for easy frequency translation

configuration

Software controlled power-down

72-lead (10 mm × 10 mm) LFCSP package

APPLICATIONS

Network synchronization, including synchronous Ethernet

and SDH to OTN mapping/demapping

Cleanup of reference clock jitter

SONET/SDH clocks up to OC-192, including FEC

Stratum 3 holdover, jitter cleanup, and phase transient

control

Wireless base station controllers

Cable infrastructure

Data communications

GENERAL DESCRIPTION

The AD9559 is a low loop bandwidth clock multiplier that

provides jitter cleanup and synchronization for many systems,

including synchronous optical networks (SONET/SDH). The

AD9559 generates an output clock synchronized to up to four

external input references. The digital PLL allows for reduction

of input time jitter or phase noise associated with the external

references. The digitally controlled loop and holdover circuitry

of the AD9559 continuously generates a low jitter output clock

even when all reference inputs have failed.

The AD9559 operates over an industrial temperature range of

−40°C to +85°C. If a single DPLL version of this part is needed,

refer to the

AD9557.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

REFERENCE

INPUT

MONITOR

AND MUX

STABLE

SOURCE

DIGITAL

PLL 0

DIGITAL

PLL 1

CLOCK

MULTIPLIER

ANALOG

PLL 0

ANALOG

PLL 1

÷3 TO ÷11

HF DIVIDER 0

÷3 TO ÷11

HF DIVIDER 1

EEPROM

SERIAL INTERFACE

(SPI OR I

STATUS AND

CONTROL PINS

CHANNEL 0B

DIVIDER

CHANNEL 0A

DIVIDER

CHANNEL 1A

DIVIDER

CHANNEL 1B

DIVIDER

AD9559

10644-001

Summary of content (120 pages)

PAGE 1
Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9559 Data Sheet FEATURES Pin program function for easy frequency translation configuration Software controlled power-down 72-lead (10 mm × 10 mm) LFCSP package Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.
PAGE 2
AD9559 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital PLL (DPLL) Core .......................................................... 34 Applications ....................................................................................... 1 Loop Control State Machine ..................................................... 36 General Description .......................................................................
PAGE 3
Data Sheet AD9559 System Clock (Register 0x0200 to Register 0x0207) ..............76 Reference Input A (Register 0x0300 to Register 0x031A) .....77 Reference Input B (Register 0x0320 to Register 0x033A)......78 Reference Input C (Register 0x0340 to Register 0x035A) .....79 Reference Input D (Register 0x0360 to Register 0x037A) .....81 DPLL_0 Controls (Register 0x0400 to Register 0x0415) .......82 DPLL_1 Settings for Reference Input A (REFA) (Register 0x055A to Register 0x0566) ...........................
PAGE 4
AD9559 Data Sheet SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for VDD3 = 3.3 V; VDD = 1.8 V; TA= 25°C, unless otherwise noted. SUPPLY VOLTAGE Table 1. Parameter SUPPLY VOLTAGE VDD3 VDD Min Typ Max Unit 3.135 1.71 3.30 1.80 3.465 1.
PAGE 5
Data Sheet AD9559 POWER DISSIPATION Table 3. Parameter POWER DISSIPATION Typical Configuration Min Typ Max Unit Test Conditions/Comments 0.57 0.71 0.85 W All Blocks Running 0.71 0.89 1.1 W 75 110 mW 171 214 257 mW System clock: 49.152 MHz crystal; two DPLLs active; two 19.44 MHz input references in differential mode; two HSTL drivers at 644.53125 MHz; two 3.3 V CMOS drivers at 161.1328125 MHz and 80 pF capacitive load on CMOS output System clock: 49.
PAGE 6
AD9559 Parameter CRYSTAL RESONATOR PATH Crystal Resonator Frequency Range Maximum Crystal Motional Resistance Data Sheet Min Typ 10 Max Unit Test Conditions/Comments 50 100 MHz Ω Fundamental mode, AT cut crystal Max Unit Test Conditions/Comments REFERENCE INPUTS Table 5.
PAGE 7
Data Sheet AD9559 REFERENCE MONITORS Table 6. Parameter REFERENCE MONITORS Reference Monitor Loss of Reference Detection Time Frequency Out-of Range Limits Validation Timer 1 Min Typ Max Unit Test Conditions/Comments 1.15 DPLL PFD period Δf/fREF (ppm) Nominal phase detector period = R/fREF 1 2 105 0.001 65.
PAGE 8
AD9559 Data Sheet DISTRIBUTION CLOCK OUTPUTS Table 8.
PAGE 9
Data Sheet Parameter Rise/Fall Time (20% to 80%)1 1.8 V Mode 3.3 V Strong Mode 3.3 V Weak Mode Duty Cycle 1.8 V Mode 3.3 V Strong Mode 3.3 V Weak Mode Output Voltage High (VOH) VDD3 = 3.3 V, IOH = 10 mA VDD3 = 3.3 V, IOH = 1 mA VDD3 = 1.8 V, IOH = 1 mA Output Voltage Low (VOL) VDD3 = 3.3 V, IOL = 10 mA VDD3 = 3.3 V, IOL = 1 mA VDD3 = 1.
PAGE 10
AD9559 Data Sheet TIME DURATION OF DIGITAL FUNCTIONS Table 9.
PAGE 11
Data Sheet AD9559 SERIAL PORT SPECIFICATIONS—SPI MODE Table 14. Parameter M5/CS Min Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO As an Input Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance As an Output Output Logic 1 Voltage Output Logic 0 Voltage M4/SDO 2.
PAGE 12
AD9559 Data Sheet SERIAL PORT SPECIFICATIONS—I2C MODE Table 15. Parameter SDA, SCL (AS INPUTS) Input Logic 1 Voltage Input Logic 0 Voltage Input Current Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSP SDA (AS OUTPUT) Output Logic 0 Voltage Output Fall Time from VIHmin to VILmax TIMING SCL Clock Rate Min Typ Unit Test Conditions/Comments 0.3 × VDD3 +10 V V µA For VIN = 10% to 90% of VDD3 50 ns 0.4 250 V ns 400 0.7 × VDD3 −10 0.
PAGE 13
Data Sheet AD9559 JITTER GENERATION Jitter Generation (Random Jitter)—49.152 MHz Crystal for System Clock Input Table 18. Parameter JITTER GENERATION fREF = 19.44 MHz; fOUT = 622.08 MHz; fLOOP = 50 Hz; HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz fREF = 19.44 MHz; fOUT = 644.
PAGE 14
AD9559 Parameter fREF = 2 kHz; fOUT = 70.656 MHz; fLOOP = 100 Hz; HSTL Driver, 3.3 V CMOS Driver Bandwidth: 10Hz to 30 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 10 kHz to 400 kHz Bandwidth: 100 kHz to 10 MHz fREF = 25 MHz; fOUT = 1 GHz; fLOOP = 500 Hz; HSTL Driver Bandwidth: 100 Hz to 500 MHz (Broadband) Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Data Sheet Min Typ Max Unit 6.
PAGE 15
Data Sheet Parameter fREF = 2 kHz; fOUT = 70.656 MHz; fLOOP = 10 Hz; HSTL Driver, 3.3 V CMOS Driver Bandwidth: 10 Hz to 30 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 10 kHz to 400 kHz Bandwidth: 100 kHz to 10 MHz AD9559 Min Typ 3.19 418 339 348 Max Unit ps rms fs rms fs rms fs rms Rev.
PAGE 16
AD9559 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 20. Parameter 1.8 V Supply Voltage (VDD) 3.3 V Supply Voltage (VDD3) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 2V 3.6 V −0.5 V to VDD3 + 0.5 V −65°C to +150°C −40°C to +85°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 17
Data Sheet AD9559 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDD3 REFB REFB VDD VDD VDD VDD VDD XOA XOB VDD VDD VDD VDD VDD REFD REFD VDD3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9559 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VDD3 REFC REFC VDD VDD GND VDD VDD VDD LDO_1 LF_1 VDD3 VDD VDD OUT1A OUT1A VDD VDD3 NOTES 1. THE EXPOSED PAD IS THE GROUND CONNECTION ON THE CHIP.
PAGE 18
AD9559 Data Sheet Pin No. 19 Mnemonic OUT0B Input/ Output O 20 OUT0B O 23 RESET I 24 SCLK/SCL I 3.3 V CMOS Logic 3.3 V CMOS 25 SDIO/SDA I/O 3.3 V CMOS 26 M5/CS I/O 3.3 V CMOS 27 M4/SDO I/O 3.3 V CMOS 29, 30, 31, 32 M3, M2, M1, M0 I/O 3.3 V CMOS 35 OUT1B O HSTL, LVDS, 1.8 V CMOS, 3.3 V CMOS 36 OUT1B O 39 OUT1A O HSTL, LVDS, 1.8 V CMOS, 3.3 V CMOS HSTL, LVDS, 1.
PAGE 19
Data Sheet AD9559 Pin No. 63 Mnemonic XOB Input/ Output I 64 XOA I Differential input 70 REFB I Differential input 71 REFB I EP GND O Differential input Exposed pad Pin Type Differential input Description Complementary System Clock Input. Complementary signal to XOA. XOB contains internal dc biasing and should be ac-coupled with a 0.1 μF capacitor except when using a crystal. When a crystal is used, connect the crystal across XOA and XOB. System Clock Input.
PAGE 20
AD9559 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS fR = input reference clock frequency; fOUT = output clock frequency; fSYS = SYSCLK input frequency; VDD3 and VDD at nominal supply voltage.
PAGE 21
Data Sheet AD9559 –60 –60 –70 PHASE NOISE (dBc/Hz): OFFSET LEVEL 10Hz –82 100Hz –90 1kHz –96 10kHz –119 100kHz –128 1MHz –143 10MHz –152 FLOOR –158 –110 PHASE NOISE (dBc/Hz) –90 –100 –120 –130 –90 –100 –110 –120 –130 –140 –140 –150 –150 –160 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) –160 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 8. Absolute Phase Noise (Output Driver = HSTL), fR = 2 kHz, fOUT = 125 MHz, DPLL Loop BW = 100 Hz, fSYS = 49.
PAGE 22
AD9559 Data Sheet –60 –60 –70 PHASE NOISE (dBc/Hz): 10Hz –60 100Hz –85 1kHz –104 10kHz –113 100kHz –114 1MHz –132 10MHz –142 FLOOR –153 PHASE NOISE (dBc/Hz) –90 –100 –110 –120 –130 –110 –120 –130 –140 –150 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) –160 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 10. Absolute Phase Noise (Output Driver = HSTL), fR = 19.44 MHz, fOUT = 644.53 MHz, DPLL Loop BW = 10 Hz, fSYS = 19.2 MHz TCXO Figure 13.
PAGE 23
AD9559 2.00 3.5 1.95 PEAK-TO-PEAK AMPLITUDE (V) 3.0 1.90 1.85 1.80 1.75 1.70 1.65 1.60 3.3V WEAK MODE 2.5 2.0 1.5 1.0 1.50 0 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 FREQUENCY (MHz) 0 80 60 100 FREQUENCY (MHz) Figure 15. Amplitude vs. Toggle Rate, HSTL Mode (LVPECL-Compatible Mode) Figure 18. Amplitude vs. Toggle Rate with 10 pF Load, 3.
PAGE 24
AD9559 80 Data Sheet 3.4 1.8V CMOS 3.3V CMOS WEAK 3.3V CMOS STRONG 70 3.0 2.6 AMPLITUDE (V) 50 40 30 20 2.2 1.8 1.4 1.0 2pF LOAD 10pF LOAD 0.6 10 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) –0.2 –1 10644-122 0 0 1 1.7 0.6 1.5 0.4 1.3 AMPLITUDE (V) 1.9 0.8 0 0.3 –0.8 0.1 1 3 2 4 5 TIME (ns) 6 7 8 TIME (ns) 9 10 11 12 13 14 15 0.7 –0.6 0 5 1.1 –0.4 –1.0 –1 4 0.9 0.5 2pF LOAD 10pF LOAD –0.1 –1 10644-123 DIFFERENTIAL AMPLITUDE (V) 1.0 –0.
PAGE 25
Data Sheet AD9559 3 0 –3 –3 –6 –6 LOOP GAIN (dB) 0 –9 –12 –15 –18 LOOP BW = 100Hz; HIGH PHASE MARGIN; PEAKING: 0.06dB; –3dB: 69Hz –9 –12 –15 –18 –21 –24 LOOP BW = 2kHz; HIGH PHASE MARGIN; PEAKING: 0.097dB; –3dB: 1.23kHz –24 –27 LOOP BW = 5kHz; HIGH PHASE MARGIN; PEAKING: 0.14dB; –3dB: 4.27kHz –27 –30 10 100 1k 10k FREQUENCY OFFSET (Hz) 100k Figure 27.
PAGE 26
AD9559 Data Sheet INPUT/OUTPUT TERMINATION RECOMMENDATIONS Z0 = 50Ω 10pF 0.1µF XOA 0.1µF Z0 = 50Ω 10MHz TO 50MHz FUNDAMENTAL AT-CUT CRYSTAL WITH 10pF LOAD CAPACITANCE XOB 10pF Figure 29. AC-Coupled LVDS or HSTL Output Driver (100 Ω resistor can be placed on either side of decoupling capacitors and should be as close to the destination receiver as possible.) Figure 32. System Clock Input (XOA/XOB) in Crystal Mode (The recommended CLOAD = 10 pF is shown.
PAGE 27
Data Sheet AD9559 GETTING STARTED CHIP POWER MONITOR AND STARTUP The AD9559 monitors the voltage on the power supplies at power-up. When VDD3 is greater than 2.35 V ± 0.1 V and VDD is greater than 1.4 V ± 0.05 V, the device generates a 20 ms reset pulse. The power-up reset pulse is internal and independent of the RESET pin. This internal power-up reset sequence eliminates the need for the user to provide external power supply sequencing.
PAGE 28
AD9559 Data Sheet REGISTER PROGRAMMING OVERVIEW System Clock Configuration This section provides a programming overview of the register blocks in the AD9559, describing what they do and why they are important. This is supplemental information only, needed only if the user wishes to load the registers without using the STP file. The system clock multiplier (SYSCLK) parameters are at Register 0x0200 to Register 0x0207.
PAGE 29
Data Sheet AD9559 Other reference input settings can be found at the following register addresses: Note that the APLL calibration and synchronization bits can be found in the following registers: • • • • • • Reference input enable information is found in the DPLL Feedback Dividers section. Reference power-down is found in Register 0x0A01. Reference priority settings are found in the DPLL profiles.
PAGE 30
AD9559 Data Sheet APLL VCO Calibration Generate the Output Clock VCO calibration ensures that, at the time of calibration, the dc control voltage of the APLL VCO is centered in the middle of its operating range. The user can calibrate VCO_0 independently of VCO_1, and vice versa.
PAGE 31
Data Sheet AD9559 THEORY OF OPERATION 2940MHz TO 3543MHz XOA XOB REF OR XTAL FRAC0 ÷ MOD0 SYSCLK MULTIPLIER ×2 A REFB REFB B REFC REFC C REFD REFD D ÷M0 VCO_0 ÷P0 (÷3 TO ÷11) ÷2, ÷4, ÷8 ÷2 ÷RA ÷2 ÷RB ÷2 ÷RC ÷2 ÷RD FREE RUN TUNING WORD PFD/CP ÷Q0_A OUT0A OUT0A DPFD LOOP FILTER TW CLAMP NCO_0 ÷Q0_B OUT0B OUT0B DPFD LOOP FILTER TW CLAMP NCO_1 ÷Q1_B OUT1B OUT1B PFD/CP ÷Q1_A OUT1A OUT1A REFERENCE MONITORS AND CROSSPOINT MUX FREE RUN TUNING WORD 302kHz TO 1.
PAGE 32
AD9559 Data Sheet REFERENCE INPUT PHYSICAL CONNECTIONS Four pairs of pins (REFA, REFA through REFD, REFD) provide access to the reference clock receivers. To accommodate input signals with slow rising and falling edges, both the differential and single-ended input receivers employ hysteresis. Hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate.
PAGE 33
Data Sheet AD9559 The AD9559 evaluation software includes a frequency planning wizard that configures the profile parameters, based on the input and output frequencies. The following list gives an overview of the five operating modes: • REFERENCE SWITCHOVER An attractive feature of the AD9559 is its versatile reference switchover capability. The flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm that is coupled with register-based controls.
PAGE 34
AD9559 Data Sheet DIGITAL PLL (DPLL) CORE sigma-delta (Σ-Δ) modulator. The digital words from the loop filter steer the SDM frequency toward frequency and phase lock with the input signal (fTDC). DPLL Overview Diagrams of the DPLL cores of the AD9559 (DPLL_0 and DPLL_1) are shown in Figure 35 and Figure 36, respectively. The blocks shown in these diagrams are purely digital. Each DPLL includes a feedback divider that causes the digital loop to operate at an integer-plus-fractional multiple.
PAGE 35
Data Sheet AD9559 The AD9559 loop filter is a third-order digital IIR filter that is analogous to the third order analog filter shown in Figure 37. R2 C2 C3 10644-015 R3 C1 Figure 37. Third Order Analog Loop Filter The AD9559 has default loop filter coefficients for two DPLL settings: nominal (70°) phase margin, and high (88.5°) phase margin. The high phase margin setting is intended for applications that require <0.1 dB of closed-loop peaking.
PAGE 36
AD9559 Data Sheet During any given PFD phase error sample, the detector either adds water with the fill bucket or removes water with the drain bucket (one or the other but not both). The decision of whether to add or remove water depends on the threshold level specified by the user. The phase lock threshold value is a 24-bit number stored in the profile registers and is expressed in picoseconds. Thus, the phase lock threshold extends from 0 ns to ±65.
PAGE 37
Data Sheet AD9559 SYSTEM CLOCK (SYSCLK) SYSCLK INPUTS Functional Description The SYSCLK circuit provides a low jitter, stable, high frequency clock for use by the rest of the chip. The XOA and XOB pins connect to the internal SYSCLK multiplier. The SYSCLK multiplier can synthesize the system clock by connecting a crystal resonator across the XOA and XOB input pins or by connecting a low frequency clock source.
PAGE 38
AD9559 Data Sheet System Clock Stability Timer Because the reference monitors depend on the system clock being at a known frequency, it is important that the system clock be stable before activating the monitors. At initial power-up, the system clock status is not known; therefore, it is reported as being unstable. After the part has been programmed, the system clock PLL eventually locks.
PAGE 39
Data Sheet AD9559 OUTPUT PLL (APLL) There are two output PLLs (APLLs) on the AD9559. They provide the frequency upconversion from the digital PLL (DPLL) outputs. The frequency range is 2940 MHz to 3543 MHz for the APLL_0 and 3405 MHz to 4260 MHz for the APLL_1, while also providing noise filter on the DPLL output. The APLL reference input is the output of the DPLL. The feedback divider is an integer divider. The loop filter is partially integrated with the one external 6.
PAGE 40
AD9559 Data Sheet MAX 1.25GHz CHIP RESET SYNC CHANNEL SYNC BLOCK OUT0A ÷Q0_A MAX 1.25GHz OUT0A 10-BIT INTEGER OUT0B ÷Q0_B OUT0B CHANNEL SYNC (TO Q0_A AND Q0_B) 10644-139 FROM VCO_0 (2940MHz TO 3543MHz) P0 DIVIDER 10-BIT INTEGER 262kHz TO 1.25GHz CLOCK DISTRIBUTION MAX 1.25GHz FROM VCO_1 (3405MHz TO 4260MHz) SYNC CHANNEL SYNC BLOCK ÷Q1_A 10-BIT INTEGER ÷Q1_B OUT1A OUT1A OUT1B OUT1B CHANNEL SYNC (TO Q1_A AND Q1_B) 10644-141 CHIP RESET MAX 1.25GHz 10-BIT INTEGER 302kHz TO 1.
PAGE 41
Data Sheet AD9559 The 3.3 V CMOS drivers feature a CMOS drive strength that allows the user to choose between a strong, high performance CMOS driver or a lower power setting with less EMI and crosstalk. The best setting is application dependent. a reference edge-initiated sync. This provides time for programming the dividers and for the DPLL to lock before the outputs are enabled. A user-initiated sync signal can also be supplied to the dividers at any time (as a manual synchronization) using an M pin.
PAGE 42
AD9559 Data Sheet STATUS AND CONTROL MULTIFUNCTION PINS (M0 TO M5) The AD9559 has six digital CMOS I/O pins (M0 to M5) that are configurable for a variety of uses. To use these functions, the user must set them by writing to Register 0x0100 and Register 0x0101. The function of these pins is programmable via the register map. Each pin can control or monitor an assortment of internal functions based on Register 0x0102 to Register 0x0107.
PAGE 43
Data Sheet AD9559 There are two ways to reset the watchdog timer (thereby preventing it from causing a timeout event). The first method is to write a Logic 1 to the autoclearing clear watchdog timer bit in the clear IRQ groups register (Register 0x0A05, Bit 7). Alternatively, the user can program any of the multifunction pins to reset the watchdog timer. This allows the user to reset the timer by means of a hardware pin rather than by a serial I/O port operation.
PAGE 44
AD9559 Data Sheet EEPROM Instructions Table 22 lists the EEPROM controller instruction set. The controller recognizes all instruction types whether it is in upload or download mode, except for the pause instruction, which is only recognizes in upload mode. The IO_UPDATE, calibrate, distribution sync, and end instructtions are, for the most part, self-explanatory. The others, however, warrant further detail, as described in the following paragraphs.
PAGE 45
Data Sheet AD9559 The controller decodes the number of bytes to transfer directly from the data instruction itself by adding 1 to the value of the instruction. For example, Data Instruction 0x1A has a decimal value of 26; therefore, the controller knows to transfer 27 bytes (one more than the value of the instruction). When the controller encounters a data instruction, it knows to read the next two bytes in the scratchpad because these contain the register map target address.
PAGE 46
AD9559 Data Sheet Automatic EEPROM Download EEPROM Conditional Processing Following a power-up, an assertion of the RESET pin, or a soft reset (Register 0x0000, Bit 5 = 1), if either the M1 pin or M0 pin is high (see Table 23), the instruction sequence stored in the EEPROM executes automatically with one of three conditions. If M1 and M0 are low, the EEPROM is bypassed and the factory defaults are used.
PAGE 47
Data Sheet AD9559 The condition is a 4-bit value with 16 possibilities. Condition = 0 is the null condition. When the null condition is in effect, the EEPROM controller executes all instructions unconditionally. The remaining 15 possibilities, condition = 1 through condition = 15, modify the EEPROM controller’s handling of a download sequence.
PAGE 48
AD9559 Data Sheet Repeat the process of programming the device control registers for a new setup, storing a new upload sequence in the EEPROM scratchpad (Step 1 through Step 4), and executing an EEPROM upload (Register 0x0E02, Bit 0) until all of the desired setups have been uploaded to the EEPROM. (Note that only Condition 1 through Condition 3 are accessible via the M pins.) Then power up the device; an automatic EEPROM download occurs.
PAGE 49
Data Sheet AD9559 SERIAL CONTROL PORT The AD9559 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The AD9559 serial control port is compatible with most synchronous transfer formats, including I²C, Motorola SPI, and Intel SSR protocols. The serial control port allows read/write access to the AD9559 register map. In SPI mode, single or multiple byte transfers are supported.
PAGE 50
AD9559 Data Sheet Communication Cycle—Instruction Plus Data The AD9559 supports the long instruction mode only. The SPI protocol consists of a two-part communication cycle. The first part is a 16-bit instruction word that is coincident with the first 16 SCLK rising edges and a payload. The instruction word provides the AD9559 serial control port with information regarding the payload.
PAGE 51
Data Sheet AD9559 Table 28. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK DON'T CARE R/W W1 W0 A12 A11 A10 A9 SDIO DON'T CARE A7 A8 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D6 D5 D7 D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA REGISTER (N) DATA 10644-029 DON'T CARE Figure 45.
PAGE 52
AD9559 Data Sheet CS tS tC tCLK tHIGH tLOW tDS SCLK SDIO BIT N BIT N + 1 Figure 50. Serial Control Port Timing—Write Table 29.
PAGE 53
Data Sheet AD9559 I²C SERIAL PORT OPERATION The I2C interface has the advantage of requiring only two control pins and is a de facto standard throughout the I2C industry. However, its disadvantage is programming speed, which is 400 kbps maximum. The AD9559 I²C port design is based on the I²C fast mode standard; it supports both the 100 kHz standard mode and 400 kHz fast mode. Fast mode imposes a glitch tolerance requirement on the control signals.
PAGE 54
AD9559 Data Sheet the slave device knows that the data transfer is finished and enters idle mode. The master then takes the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. When all the data bytes are read or written, stop conditions are established.
PAGE 55
Data Sheet AD9559 Data Transfer Format Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. S Slave address W A RAM address high byte A RAM address low byte A RAM Data 0 A RAM Data 1 A RAM Data 2 A P Send byte format—the send byte protocol is used to set up the register address for subsequent reads.
PAGE 56
AD9559 Data Sheet PROGRAMMING THE I/O REGISTERS The register map (see Table 34) spans an address range from 0x0000 through 0x0E4F. Each address provides access to one byte (eight bits) of data. Each individual register is identified by its four-digit hexadecimal address (for example, Register 0x0A23). In some cases, a group of addresses collectively defines a register.
PAGE 57
Data Sheet AD9559 THERMAL PERFORMANCE Table 33. Thermal Parameters for the 72-Lead LFCSP Package Symbol θJA θJMA θJMA θJB θJC ΨJT ΨJT ΨJT 1 2 Thermal Characteristic Using a JEDEC 51-7 Plus JEDEC 51-5 2S2P Test Board1 Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
PAGE 58
AD9559 Data Sheet POWER SUPPLY PARTITIONS The AD9559 power supplies are in two groups: VDD3 and VDD. All power and ground pins should be connected, even if certain blocks of the chip are powered down. 1.8 V SUPPLIES Ferrite beads with low (< 0.7 Ω) dc resistance and approximately 600 Ω impedance at 100 MHz are suitable for this application. Six ferrite beads should be used in the following locations: 3.3 V SUPPLIES All of the 3.3 V supplies can be supplied from one 3.3V power supply.
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Data Sheet AD9559 REGISTER MAP Register addresses that are not listed in Table 34 are not used, and writing to those registers has no effect. The user should write the default value to sections of registers marked reserved. R = read only. A = autoclear. E = excluded from EEPROM loading. W1, W2, W5, W6, and W7 = write detection (see Table 32 for more information). L = live (IO_UPDATE not required for register to take effect or for a read-only register to be updated.) Table 34.
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AD9559 Reg Addr Opt (Hex) System Clock 0x0200 0x0201 Data Sheet Name SYSCLK PLL feedback divider and config 0x0202 SYSCLK period 0x0203 0x0204 0x0205 W6 SYSCLK stability 0x0206 W6 0x0207 W6 Reference Input A 0x0300 REFA logic type 0x0301 REFA R divider 0x0302 (20 bits) 0x0303 0x0304 W0 0x0305 W0 0x0306 W0 0x0307 W0 0x0308 W0 0x0309 W0 0x030A W0 0x030B W0 0x030C W0 0x030D W0 0x030E W0 0x030F W0 0x0310 W0 0x0311 W1 0x0312 W1 0x0313 W1 0x0314 W1 0x0315 W1 0x0316 W1 0x0317 W1 0x0318 W1 0x0319 W1 0x031A W1 Ref
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Data Sheet Reg Addr Opt (Hex) 0x032F W0 0x0330 W0 0x0331 W1 0x0332 W1 0x0333 W1 0x0334 W1 0x0335 W1 0x0336 W1 0x0337 W1 0x0338 W1 0x0339 W1 0x033A W1 Reference Input C 0x0340 Name REFB validation AD9559 D7 D6 D5 REFB phase lock detector REFB frequency lock detector REFC logic type REFC R divider (20 bits) 0x0341 0x0342 0x0343 0x0344 W0 REFC period 0x0345 W0 (up to 0x0346 W0 1.
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AD9559 Data Sheet Reg Addr Opt Name (Hex) 0x036F W0 REFD validation 0x0370 W0 0x0371 W1 REFD phase lock 0x0372 W1 detector 0x0373 W1 0x0374 W1 0x0375 W1 0x0376 W1 REFD frequency 0x0377 W1 lock 0x0378 W1 detector 0x0379 W1 0x037A W1 DPLL_0 General Settings 0x0400 DPLL_0 free run 0x0401 frequency 0x0402 TW 0x0403 0x0404 DCO_0 control 0x0405 0x0406 0x0407 0x0408 0x0409 0x040A 0x040B 0x040C 0x040D 0x040E 0x040F 0x0410 0x0411 0x0412 0x0413 0x0414 0x0415 D7 D6 Reserved DPLL_0 holdover history DPLL_0 histor
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Data Sheet Reg Addr (Hex) 0x0427 Opt 0x0428 0x0429 0x042A 0x042B Name OUT0A OUT0B AD9559 D7 Reserved Reserved Enable 3.
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AD9559 Data Sheet Reg Addr Opt Name D7 (Hex) DPLL_0 Settings for Reference Input C 0x045A Reference priority 0x045B W2 DPLL_0 loop BW 0x045C W2 (16 bits) 0x045D W2 0x045E W2 DPLL_0 N0 divider 0x045F W2 (17 bits) 0x0460 W2 D6 0x0505 0x0506 0x0507 0x0508 0x0509 0x050A DPLL_1 frequency clamp D3 D2 D1 REFC priority, Bits[1:0] Digital PLL_0 loop BW scaling factor, Bits[7:0] (default: 0x01F4 = 50 Hz) Digital PLL_0 loop BW scaling factor, Bits[15:8] Reserved Base filter Digital PLL feedback divider—Intege
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Data Sheet Reg Addr (Hex) 0x050B 0x050C 0x050D 0x050E 0x050F 0x0510 0x0511 0x0512 0x0513 0x0514 0x0515 Opt Name DPLL_1 holdover history DPLL_1 history mode DPLL_1 closed loop phase offset [±0.5 ms] AD9559 D7 D6 Reserved P1 divider OUT1 sync 0x0528 0x0529 0x052A 0x052B OUT1A OUT1B Reserved Reserved Enable 3.
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AD9559 Reg Addr (Hex) 0x054A 0x054B Data Sheet Opt W2 W2 Name D7 DPLL_1 fractional feedback 0x054C W2 Reserved divider modulus (23 bits) DPLL_1 Settings for Reference Input D 0x054D Reference priority 0x054E W2 DPLL_1 loop BW 0x054F W2 (16 bits) 0x0550 W2 0x0551 W2 DPLL_1 N1 divider 0x0552 W2 (17 bits) 0x0553 W2 0x0554 0x0555 0x0556 DPLL_1 fractional feedback Reserved divider (23 bits) 0x0557 W2 DPLL_1 fractional 0x0558 W2 feedback 0x0559 W2 Reserved divider modulus (23 bits) DPLL_1 Settings for Refere
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Data Sheet AD9559 Reg Addr Opt Name D7 (Hex) DPLL_1 Settings for Reference Input B 0x0567 Reference priority 0x0568 W2 DPLL_1 loop BW 0x0569 W2 (16 bits) 0x056A W2 0x056B W2 DPLL_1 N1 divider 0x056C W2 (17 bits) 0x056D W2 0x056E 0x056F 0x0570 0x0571 0x0572 0x0573 W2 W2 W2 DPLL_1 fractional feedback divider (23 bits) DPLL_1 fractional feedback divider modulus (23 bits) Loop Filters 0x0800 L Base loop filter 0x0801 L coefficient 0x0802 L set 0x0803 L (normal phase 0x0804 L margin 0x0805 L of 70°) 0x0806
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AD9559 Data Sheet Reg Addr (Hex) 0x0A05 Opt A Name Clear IRQ groups 0x0A06 A 0x0A07 A Clear common IRQ 0x0A08 A 0x0A09 A 0x0A0A A 0x0A0B A 0x0A0C A 0x0A0D A 0x0A0E A D7 Clear watchdog timer Reserved Reserved Reserved Clear DPLL_0 IRQ Clear DPLL_1 IRQ Frequency unclamped DPLL_0 switching Frequency unclamped DPLL_1 switching PLL_0 Operational Controls 0x0A20 PLL_0 sync cal 0x0A21 PLL_0 output 0x0A22 PLL_0 user mode D6 D5 Reserved D4 SYSCLK unlocked REFB validated REFD valid
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Data Sheet AD9559 Reg Addr Opt Name D7 D6 D5 D4 D3 (Hex) Read-Only Status Common Blocks (These registers are accessible during EEPROM transactions. To show the latest status, Register 0x0D02 to Register 0x0D05 require an IO_UPDATE before being read.
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AD9559 Data Sheet Reg Addr Opt Name D7 D6 D5 D4 D3 (Hex) PLL_1 Read-Only Status (To show the latest status, these registers require an IO_UPDATE before being read.
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Data Sheet Reg Addr (Hex) 0x0E2D 0x0E2E 0x0E2F 0x0E30 0x0E31 0x0E32 0x0E33 0x0E34 0x0E35 0x0E36 0x0E37 0x0E38 0x0E39 0x0E3A 0x0E3B 0x0E3C 0x0E3D 0x0E3E 0x0E3F 0x0E40 0x0E41 0x0E42 0x0E43 0x0E44 0x0E45 0x0E46 0x0E47 0x0E48 0x0E49 to 0x0E4F Opt Name DPLL_0 dividers and BW AD9559 D7 D6 D5 D4 D3 Size of transfer: 52 bytes Starting Address 0x0440 D2 D1 D0 Def (Hex) 0x33 0x04 0x40 0x15 0x05 0x00 0x0E 0x05 0x20 DPLL_1 general settings Size of transfer: 22 bytes Starting Address 0x0500 APLL_1 config an
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AD9559 Data Sheet REGISTER MAP BIT DESCRIPTIONS SERIAL CONTROL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005) Table 35. Serial Configuration (Note that the contents of Register 0x0000 are not stored to the EEPROM.) Address 0x0000 Bits 7 Bit Name SDO enable 6 LSB first/increment address 5 Soft reset [4:0] Reserved Description Enables SPI port SDO pin. 1 = 4-wire (SDO pin enabled). 0 (default) = 3-wire. Bit order for SPI port. 1 = least significant bit and byte first.
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Data Sheet AD9559 USER SCRATCHPAD (REGISTER 0x000E AND REGISTER 0x000F) Table 39. User Scratchpad Address 0x000E 0x000F Bits [7:0] [7:0] Bit Name User scratchpad, Bits[7:0] User scratchpad, Bits[15:8] Description User programmable EEPROM ID registers. These registers enable users to write a unique code of their choosing to keep track of revisions to the EEPROM register loading. It has no effect on part operation. Default = 0x0000.
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AD9559 Data Sheet IRQ MASK (REGISTER 0x010A TO REGISTER 0x112) The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (0x0D08 to 0x0D10). When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts. Table 41.
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Data Sheet AD9559 Table 43.
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AD9559 Data Sheet SYSTEM CLOCK (REGISTER 0x0200 TO REGISTER 0x0207) Table 45. System Clock PLL Feedback Divider (K Divider) and Configuration Address 0x0200 Bits [7:0] Bit Name System clock K divider Description System clock PLL feedback divider value = 4 ≤ K ≤ 255 (default: 0x08). Table 46. SYSCLK Configuration Address 0x0201 Bits [7:4] 4 Bit Name Reserved SYSCLK XTAL enable [2:1] SYSCLK J1 divider 0 SYSCLK doubler enable (J0 divider) Description Reserved.
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Data Sheet AD9559 REFERENCE INPUT A (REGISTER 0x0300 TO REGISTER 0x031A) Table 49. REFA Logic Type Address 0x0300 Bits [7:4] 3 Bit Name Reserved Enable REFA divide-by-2 2 [1:0] Reserved REFA logic type Description Default: 0x0 Enables the reference input divide-by-2 for REFA 0 = bypasses the divide-by-2 (default) 1 = enables the divide-by-2 Default: 0b Selects logic family for REFA input receiver; only the REFA pin is used in CMOS mode 00 (default) = differential 01 = 1.2 V to 1.5 V CMOS 10 = 1.
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AD9559 Data Sheet Table 53. REFA Validation Timer Address 0x030F Bits [7:0] 0x0310 [7:0] Bit Name Validation timer (ms) Description Validation timer, Bits[7:0] (default: 0x0A). This is the amount of time a reference input must be valid before it is declared valid by the reference input monitor (default: 10 ms). Validation timer, Bits[15:8] (default: 0x00). Table 54.
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Data Sheet AD9559 Table 58. REFB Frequency Tolerance Address 0x0329 0x032A 0x032B Bits [7:0] [7:0] [7:4] [3:0] 0x032C 0x032D 0x032E [7:0] [7:0] [7:4] [3:0] Bit Name Inner tolerance Reserved Inner tolerance Outer tolerance Reserved Outer tolerance Description Input reference frequency monitor inner tolerance, Bits[7:0] (default: 0x14) Input reference frequency monitor inner tolerance, Bits[15:8] (default: 0x00) Default: 0x0 Input reference frequency monitor inner tolerance, Bits[19:16].
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AD9559 Data Sheet Table 62. REFC 20-bit DPLL R Divider Address 0x0341 0x0342 0x0343 Bits [7:0] [7:0] [7:4] [3:0] Bit Name R divider Reserved R divider Description DPLL integer reference divider (minus 1), Bits[7:0] (default: 0xCF) DPLL integer reference divider (minus 1), Bits[15:8] (default: 0x00) Default: 0x0 DPLL integer reference divider (minus 1), Bits[19:16] (default: 0x0) Table 63.
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Data Sheet AD9559 REFERENCE INPUT D (REGISTER 0x0360 TO REGISTER 0x037A) Table 67. REFD Logic Type Address 0x0360 Bits [7:4] 3 Bit Name Reserved Enable REFD divide-by-2 2 [1:0] Reserved REFD logic type Description Default: 0x0 Enables the reference input divide-by-2 for REFD 0 = bypasses the divide-by-2 (default) 1 = enables the divide-by-2 Default: 0b Selects logic family for REFD input receiver; only the REFD pin is used in CMOS mode 00 (default) = differential 01 = 1.2 V to 1.5 V CMOS 10 = 1.
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AD9559 Data Sheet Table 72.
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Data Sheet AD9559 Table 76. DPLL_0 History Accumulation Timer Address 0x040B Bits [7:0] 0x040C [7:0] Bit Name History accumulation timer (expressed in units of ms) Description History accumulation timer, Bits[7:0]. Default: 0x0A. For Register 0x040B and Register 0x040C, 0x000A = 10 ms. Maximum: 65 sec. This register controls the amount of tuning word averaging used to determine the tuning word used in holdover. Never program a timer value of 0. Default value: 0x000A = 10 (10 ms).
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AD9559 Data Sheet APLL_0 CONFIGURATION (REGISTER 0x0420 TO REGISTER 0x0423) Table 81. Output PLL_0 (APLL_0) Setting1 Address 0x0420 Bits [7:0] Bit Name APLL_0 charge pump current 0x0421 [7:0] APLL_0 M0 (feedback) divider 0x0422 [7:6] APLL_0 loop filter control [5:3] [2:0] 0x0423 1 [7:1] 0 Reserved Bypass internal Rzero Description LSB: 3.
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Data Sheet AD9559 PLL_0 OUTPUT SYNC AND CLOCK DISTRIBUTION (REGISTER 0x0424 TO REGISTER 0x042E) Table 82. APLL_0 P0 Divider Settings Address 0x0424 Bits [7:4] [3:0] Bit Name Reserved P0 divider divide ratio Description Default: 0x0 0000/0001 = 3 0010 = 4 0011 = 5 0100 = 6 (default) 0101 = 7 0110 = 8 0111 = 9 1000 = 10 1001 = 11 Table 83.
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AD9559 Data Sheet Table 84. Distribution OUT0A Settings Address 0x0427 Bits 7 [6:4] Bit Name Reserved OUT0A format [3:2] OUT0A polarity 1 OUT0A LVDS boost 0 Reserved Description Default: 0b Selects the operating mode of OUT0A. 000 = power-down, tristate. 001 (default) = HSTL. 010 = LVDS. 011 = reserved. 100 = CMOS, both outputs active. 101 = CMOS, P output active, N output power-down. 110 = CMOS, N output active, P output power-down. 111 = reserved. Controls the OUT0A polarity.
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Data Sheet AD9559 Table 87. Q0B_B Divider Setting Address 0x042C Bits [7:0] Bit Name Q0_B divider 0x042D [7:2] [1:0] [7:6] [5:0] Reserved Q0_B divider Reserved Q0_B divider phase 0x042E Description 10-bit channel divider, Bits[7:0] (LSB). Division equals channel divider, Bits[9:0] + 1. ([9:0] = 0 is divide-by-1, [9:0] = 1 is divide-by-2…[9:0] = 1023 is divide-by-1024). Default: 000000b. 10-bit channel divider, Bits[9:8] (MSB), Bits[1:0]. Default: 00b.
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AD9559 Data Sheet Table 92.
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Data Sheet AD9559 DPLL_0 SETTINGS FOR REFERENCE INPUT C (REFC) (REGISTER 0x045A TO REGISTER 0x0466) Table 98. DPLL_0 REFC Priority Setting Address 0x045A Bits [7:3] [2:1] Bit Name Reserved REFC priority 0 Enable REFC Description Default: 00000b. These bits set the priority level (0 to 3) of REFC relative to the other input references. 00 (default) = 0 (highest). 01 = 1. 10 = 2. 11 = 3. This bit enables DPLL_0 to lock to REFC. 0 (default) = REFC is not enabled for use by DPLL_0.
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AD9559 Data Sheet DPLL_0 SETTINGS FOR REFERENCE INPUT D (REFD) (REGISTER 0x0467 TO REGISTER 0x0473) Table 103. DPLL_0 REFD Priority Setting Address 0x0467 Bits [7:3] [2:1] Bit Name Reserved REFD priority 0 Enable REFD Description Default: 00000b. These bits set the priority level (0 to 3) of REFD relative to the other input references. 00 (default) = 0 (highest). 01 = 1. 10 = 2. 11 = 3. This bit enables DPLL_0 to lock to REFD. 0 (default) = REFD is not enabled for use by DPLL_0.
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Data Sheet AD9559 DPLL_1 CONTROLS (REGISTER 0x0500 TO REGISTER 0x0515) Table 108.
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AD9559 Data Sheet Table 112. DPLL_1 History Mode Address 0x050D Bits [7:5] 4 Bit Name Reserved Single sample fallback 3 Persistent history [2:0] Incremental average Description Reserved. Controls holdover history. If tuning word history is not available for the reference that was active just prior to holdover, then: 0 (default) = use the free running frequency tuning word register value. 1 = use the last tuning word from the DPLL. Controls holdover history initialization.
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Data Sheet AD9559 APLL_1 CONFIGURATION (REGISTER 0x0520 TO REGISTER 0x0523) Table 116. Output PLL_1 (APLL_1) Setting1 Address 0x0520 Bits [7:0] Bit Name APLL_1 charge pump current 0x0521 [7:0] APLL_1 M1 (feedback) divider 0x0522 [7:6] APLL_1 loop filter control [5:3] [2:0] 0x0523 1 [7:1] 0 Reserved Bypass internal Rzero Description LSB = 3.
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AD9559 Data Sheet PLL_1 OUTPUT SYNC AND CLOCK DISTRIBUTION (REGISTER 0x0524 TO REGISTER 0x052E) Table 117. APLL_1 P1 Divider Settings Address 0x0524 Bits [7:4] [3:0] Bit Name Reserved P1 divider divide ratio Description Default: 0x0 0000/0001 = 3 0010 = 4 0011 = 5 0100 = 6 (default) 0101 = 7 0110 = 8 0111 = 9 1000 = 10 1001 = 11 Table 118.
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Data Sheet AD9559 Table 119. Distribution OUT1A Settings Address 0x0527 Bits 7 [6:4] Bit Name Reserved OUT1A format [3:2] OUT1A polarity 1 OUT1A LVDS boost 0 Reserved Description Default: 0b. Select the operating mode of OUT1A. 000 = power-down, tristate. 001 (default) = HSTL. 010 = LVDS. 011 = reserved. 100 = CMOS, both outputs active. 101 = CMOS, P output active, N output power-down. 110 = CMOS, N output active, P output power-down. 111 = reserved. Control the OUT1A polarity.
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AD9559 Data Sheet Table 122. OUT1B Divider Setting Address 0x052C Bits [7:0] Bit Name Q1_B divider 0x052D [7:2] [1:0] [7:6] [5:0] Reserved Q1_B divider Reserved Q1_B divider phase 0x052E Description 10-bit channel divider, Bits[7:0] (LSB). Division equals channel divider, Bits[9:0] + 1. ([9:0] = 0 is divide-by-1, [9:0] = 1 is divide-by-2…[9:0] = 1023 is divide-by-1024). Default: 000000b. 10-bit channel divider, Bits[9:8] (MSB), Bits[1:0]. Default: 00b.
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Data Sheet AD9559 Table 127.
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AD9559 Data Sheet DPLL_1 SETTINGS FOR REFERENCE INPUT A (REFA) (REGISTER 0x055A TO REGISTER 0x0566) Table 133. DPLL_1 REFA Priority Setting Address 0x055A Bits [7:3] [2:1] Bit Name Reserved REFA priority 0 Enable REFA Description Default: 00000b. These bits set the priority level (0 to 3) of REFA relative to the other input references. 00 (default) = 0 (highest). 01 = 1. 10 = 2. 11 = 3. This bit enables DPLL_1 to lock to REFA. 0 (default) = REFA is not enabled for use by DPLL_1.
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Data Sheet AD9559 DPLL_1 SETTINGS FOR REFERENCE INPUT B (REFB) (REGISTER 0x0567 TO REGISTER 0x0573) Table 138. DPLL_1 REFB Priority Setting Address 0x0567 Bits [7:3] [2:1] Bit Name Reserved REFB priority 0 Enable REFB Description Default: 00000b. These bits set the priority level (0 to 3) of REFA relative to the other input references. 00 (default) = 0 (highest). 01 = 1. 10 = 2. 11 = 3. This bit enables DPLL_1 to lock to REFB. 0 (default) = REFB is not enabled for use by DPLL_1.
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AD9559 Data Sheet DIGITAL LOOP FILTER COEFFICIENTS (REGISTER 0x0800 TO REGISTER 0x0817) Table 143. Base Digital Loop Filter with Normal Phase Margin (PM = 70°, BW = 0.
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Data Sheet AD9559 COMMON OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A0E) Table 145. Global Operational Controls Address 0x0A00 Bits [7:3] 2 Bit Name Reserved Soft sync all 1 0 Calibrate all Power down all Description Default: 00000b. Setting this bit initiates synchronization of all clock distribution outputs (default = 0b). Nonmasked outputs stall when value is 1; restart is initialized on a 1-to-0 transition. Calibrates both output PLL0 (APLL_0) and output PLL1 (APLL_1).
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AD9559 Data Sheet Table 149.
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Data Sheet AD9559 Table 152.
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AD9559 Data Sheet Table 154.
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Data Sheet AD9559 Table 157.
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AD9559 Data Sheet PLL_1 OPERATIONAL CONTROLS (REGISTER 0x0A40 TO REGISTER 0x0A44) Table 160. PLL_1 Sync and Calibration Address 0x0A40 Bits [7:3] 2 Bit Name Reserved APLL_1 soft sync 1 APLL_1 calibrate (not self-clearing) 0 PLL_1 power-down Description Default: 0x0. Setting this bit initiates synchronization of the clock distribution output. Default: 0b. Nonmasked outputs stall when value is 1; restart is initialized on a 1-to-0 transition.
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Data Sheet AD9559 Table 163. DPLL_1 Reset Address 0x0A43 Bits [7:3] 2 1 0 Bit Name Reserved Reset DPLL_1 loop filter Reset DPLL_1 TW history Reset DPLL_1 autosync Description Default: 00000b. Setting this bit clears the digital loop filter (intended as a debug tool). Setting this bit resets the tuning word history logic (part of holdover functionality). Setting this bit resets the automatic synchronization logic (see Register 0x0525). Table 164.
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AD9559 Data Sheet Table 167.
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Data Sheet Address 0x0D09 0x0D0A Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 AD9559 Bit Name Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault Reserved REFD validated REFD fault cleared REFD fault Reserved REFC validated REFC fault cleared REFC fault Description Reserved IRQ indicating that REFB has been validated IRQ indicating that REFB has been cleared of a previous fault IRQ indicating that REFB has been faulted Reserved IRQ indicating that REFA has
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AD9559 Data Sheet Table 170.
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Data Sheet AD9559 Table 172. DPLL_0 Loop State Address 0x0D21 0x0D22 Bits [7:5] [4:3] Bit Name Reserved DPLL_0 active ref 2 DPLL_0 switching 1 DPLL_0 holdover 0 DPLL_0 free run [7:3] 2 1 0 Reserved DPLL_0 phase slew limited DPLL_0 frequency clamped DPLL_0 history available Description Default: 000b. Indicates the reference input that DPLL_0 is using. 00 = DPLL_0 has selected REFA. 01 = DPLL_0 has selected REFB. 10 = DPLL_0 has selected REFC. 11 = DPLL_0 has selected REFD.
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AD9559 Data Sheet PLL_1 READ-ONLY STATUS (REGISTER 0x0D40 TO REGISTER 0x0D4A) All bits in Register 0x0D40 to Register 0x0D4A are read only. To report the latest status, these bits require an IO_UPDATE (Register 0x0005 = 0x01) immediately before being read. Table 175.
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Data Sheet AD9559 Table 178. DPLL_1 Phase Lock and Frequency Lock Bucket Levels Address 0x0D47 Bits [7:0] 0x0D48 [7:4] [3:0] 0x0D49 0x0D4A [7:0] [7:4] [3:0] Bit Name DPLL_1 phase lock detect bucket Reserved DPLL_1 phase lock detect bucket Frequency tub Reserved Frequency tub Description Read-only DPLL_1 lock detect bucket level, Bits[7:0]; see the DPLL Frequency Lock Detector section. Reserved. Read-only DPLL_1 lock detect bucket level, Bits[11:8]; see the DPLL Frequency Lock Detector section.
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AD9559 Data Sheet Table 181. EEPROM Storage Sequence for System Clock Settings Address 0x0E17 Bits [7:0] 0x0E18 0x0E19 [7:0] [7:0] 0x0E1A [7:0] Bit Name System clock IO_UPDATE Description The default value of this register is 0x07, which is a data instruction. Its decimal value is 7, which tells the controller to transfer eight bytes of data (7 + 1), beginning at the address specified by the next two bytes. The controller stores 0x07 in the EEPROM and increments the EEPROM address pointer.
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Data Sheet AD9559 Table 183. EEPROM Storage Sequence for DPLL_0 General Settings Address 0x0E27 Bits [7:0] 0x0E28 [7:0] 0x0E29 [7:0] Bit Name DPLL_0 general settings Description The default value of this register is 0x15, which the controller interprets as a data instruction. Its decimal value is 21, which tells the controller to transfer 22 bytes of data (21 + 1), beginning at the address specified by the next two bytes.
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AD9559 Data Sheet Table 187. EEPROM Storage Sequence for APLL_1 Configuration and Output Drivers Address 0x0E33 Bits [7:0] 0x0E34 [7:0] 0x0E35 [7:0] Bit Name APLL_1 config and output drivers Description The default value of this register is 0x0E, which the controller interprets as a data instruction. Its decimal value is 14, which tells the controller to transfer 15 bytes of data (14 + 1) beginning at the address specified by the next two bytes.
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Data Sheet AD9559 Table 191. EEPROM Storage Sequence for PLL_0 Operational Control Settings Address 0x0E3F Bits [7:0] 0x0E40 0x0E41 [7:0] [7:0] Bit Name PLL_0 operational controls Description The default value of this register is 0x04, which the controller interprets as a data instruction. Its decimal value is 4, which tells the controller to transfer five bytes of data (4 + 1), beginning at the address specified by the next two bytes.
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AD9559 Data Sheet Table 196.
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Data Sheet AD9559 Table 197.
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AD9559 Data Sheet OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 55 72 54 PIN 1 INDICATOR 1 PIN 1 INDICATOR 9.85 9.75 SQ 9.65 0.50 BSC 0.50 0.40 0.30 19 BOTTOM VIEW 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN 8.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.