Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync AD9558 Data Sheet FEATURES Pin program function for easy frequency translation configuration Software controlled power-down 64-lead, 9 mm × 9 mm, LFCSP package Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.
AD9558 Data Sheet TABLE OF CONTENTS Features ........................................................................................................ 1 Digital PLL (DPLL) Core ...................................................................31 Applications ................................................................................................ 1 Loop Control State Machine .............................................................34 General Description .....................................
Data Sheet AD9558 Register Map Bit Descriptions............................................................... 72 Serial Port Configuration (Register 0x0000 to Register 0x0005)72 Silicon Revision (Register 0x000A) ................................................. 72 Clock Part Serial ID (Register 0x000C to Register 0x000D) ...... 72 System Clock (Register 0x0100 to Register 0x0108) .................... 73 General Configuration (Register 0x0200 to Register 0x0214) ...
AD9558 Data Sheet SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD = 1.8 V; TA= 25°C, unless otherwise noted. SUPPLY VOLTAGE Table 1. Parameter SUPPLY VOLTAGE DVDD3 DVDD AVDD3 AVDD Min Typ Max Unit 3.135 1.71 3.135 1.71 3.30 1.80 3.30 1.80 3.465 1.89 3.465 1.
Data Sheet AD9558 POWER DISSIPATION Table 3. Parameter POWER DISSIPATION Typical Configuration Min Typ Max Unit Test Conditions/Comments 0.47 0.74 1.02 W All Blocks Running 0.6 1.0 1.32 W 44 125 mW System clock: 49.152 MHz crystal; DPLL active; both 19.44 MHz input references in differential mode; one HSTL driver at 644.53125 MHz; one 3.3 V CMOS driver at 161.1328125 MHz and 80 pF capacitive load on CMOS output System clock: 49.
AD9558 Data Sheet LOGIC OUTPUTS (M7 TO M0, IRQ) Table 5. Parameter LOGIC OUTPUTS (M7 to M0, IRQ) Output High Voltage (VOH) Output Low Voltage (VOL) IRQ Leakage Current Active Low Output Mode Active High Output Mode Min Typ Max Unit Test Conditions/Comments 0.4 V V −200 100 μA μA IOH = 1 mA IOL = 1 mA Open-drain mode VOH = 3.
Data Sheet AD9558 REFERENCE INPUTS Table 7. Parameter DIFFERENTIAL OPERATION Frequency Range Sinusoidal Input LVPECL Input LVDS Input Min Max Unit 10 0.002 750 1250 MHz MHz 0.
AD9558 Data Sheet REFERENCE MONITORS Table 8. Parameter REFERENCE MONITORS Reference Monitor Loss of Reference Detection Time Frequency Out-of-Range Limits Validation Timer 1 Min Typ Max Unit Test Conditions/Comments 1.1 DPLL PFD period Δf/fREF (ppm) Nominal phase detector period = R/fREF 1 <2 105 0.001 65.
Data Sheet AD9558 DISTRIBUTION CLOCK OUTPUTS Table 10. Parameter HSTL MODE Output Frequency Min Typ Max Unit Test Conditions/Comments 1250 MHz 140 250 ps OUT5 only; OUT0 to OUT4 minimum output frequency is 360 kHz 100 Ω termination across output pins 48 48 43 950 870 52 53 1200 960 % % % mV mV Magnitude of voltage across pins; output driver static Output driver static 1250 MHz 185 280 ps 48 47 43 53 53 % % % 454 mV 50 mV 1.
AD9558 Parameter OUTPUT TIMING SKEW Between OUT0 and OUT1 Data Sheet Typ Max Unit 10 70 ps Between OUT0 and OUT3 105 222 ps Between OUT0 and OUT5 1.39 1.
Data Sheet AD9558 DIGITAL PLL Table 12. Parameter DIGITAL PLL Phase-Frequency Detector (PFD) Input Frequency Range Loop Bandwidth Phase Margin Closed-Loop Peaking Reference Input (R) Division Factor Integer Feedback (N1) Division Factor Fractional Feedback Divide Ratio Min Typ Max Unit 2 100 kHz 0.1 30 <0.1 2000 89 Hz Degrees dB 1 180 0 220 217 0.
AD9558 Data Sheet SERIAL PORT SPECIFICATIONS—SPI MODE Table 15.
Data Sheet AD9558 SERIAL PORT SPECIFICATIONS—I2C MODE Table 16.
AD9558 Parameter fREF = 19.44 MHz; fOUT = 644.53 MHz; fLOOP = 50 Hz HSTL and/or LVDS Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz fREF = 19.44 MHz; fOUT = 693.48 MHz; fLOOP = 50 Hz HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz fREF = 19.44 MHz; fOUT = 174.
Data Sheet AD9558 Jitter generation (random jitter) uses 19.2 MHz TCXO for system clock input. Table 18. Parameter JITTER GENERATION fREF = 19.44 MHz; fOUT = 644.53 MHz; fLOOP = 0.1 Hz HSTL Driver Bandwidth: 5 kHz to 20 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 16 MHz to 320 MHz fREF = 19.44 MHz; fOUT = 693.48 MHz; fLOOP = 0.
AD9558 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 19. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD3) Analog Supply Voltage (AVDD3) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 2V 2V 3.6 V 3.6 V −0.5 V to DVDD3 + 0.
Data Sheet AD9558 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVDD3 M6 M5 M4 M3 M2 M1 M0 DVDD DVDD REFB REFB DVDD3 DVDD3 REFD REFD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD9558 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 REFC REFC DVDD3 DVDD3 REFA REFA SYNC M7 PINCONTROL RESET AVDD AVDD NC AVDD NC LF_VCO2 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2.
AD9558 Data Sheet Pin No. 13 Mnemonic OUT4 Input/ Output O 14 OUT4 O OUT3 O OUT3 O OUT2 O OUT2 O OUT1 O OUT1 O OUT5 O 24 OUT5 O 25, 26 27 AVDD3 OUT0 I O 28 OUT0 O 31 32 AVDD3 LDO_VCO2 I I Power LDO bypass 33 LF_VCO2 I/O Loop filter 34 35 36 37, 38 39 NC AVDD NC AVDD RESET I Power I I Power 3.3 V CMOS 40 PINCONTROL I 3.3 V CMOS 41 M7 I/O 3.3 V CMOS I 3.
Data Sheet Pin No. 43 Mnemonic REFA Input/ Output I REFA I 44 A Differential input Power I REFC I Differential input I Differential input Differential input 48 REFC A E REFD I REFD I REFB I REFB I M0, M1, M2, M3, M4, M5, M6 I/O Differential input 3.
AD9558 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS fR = input reference clock frequency; fOUT = output clock frequency; fSYS = SYSCLK input frequency; fS = internal system clock frequency; LF = SYSCLK PLL internal loop filter used. AVDD, AVDD3, and DVDD at nominal supply voltage; fS = 786.432 MHz, unless otherwise noted.
Data Sheet AD9558 –80 –60 INTEGRATED RMS JITTER (12kHz TO 20MHz): 302fs INTEGRATED RMS JITTER (12kHz TO 20MHz): 393fs –70 –90 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –80 –100 –110 –120 –130 –140 –90 –100 –110 –120 –130 –140 –150 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) –160 09758-007 1k 10 1M 10M 100M INTEGRATED RMS JITTER (12kHz TO 20MHz): 371s –70 –80 –80 –100 –110 –120 –130 –90 –100 –110 –120 –130 –140 –140 –150 –150 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) –1
AD9558 Data Sheet DIFFERENTIAL PEAK-TO-PEAK AMPLITUDE (V) –70 INTEGRATED RMS JITTER (12kHz TO 20MHz): 391fs –80 –100 –110 –120 –130 –140 –150 –80 PHASE NOISE (dBc/Hz) –90 –100 –110 –120 –130 –140 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) 1300 09758-116 0.9 LVDS BOOST MODE 0.8 0.7 LVDS DEFAULT 0.6 0.5 0.4 09758-014 –150 1.
AD9558 70 3.0 60 2.5 50 2.0 1.5 30 20 0.5 10 0 20 10 30 40 50 60 70 80 FREQUENCY (MHz) Figure 19. Amplitude vs. Toggle Rate with 10 pF Load, 3.3 V (Weak Mode) CMOS 0 0 50 100 150 200 FREQUENCY (MHz) Figure 22. Power Consumption vs. Frequency, One CMOS Driver on Output Driver Power Supply Only (Pin 12, Pin 17, Pin 22, and Pin 29) for 1.8 V CMOS Mode, or on Pin 25 and Pin 26 for 3.3 V CMOS Mode 1.
AD9558 Data Sheet 3 3.4 0 3.0 –3 2.6 –6 1.8 1.4 1.0 0.2 0 1 2 3 4 5 6 7 8 TIME (ns) 9 10 11 12 13 14 15 1.9 LOOP BW = 2kHz; HIGH PHASE MARGIN; PEAKING: 0.097dB; –3dB: 1.23kHz –27 LOOP BW = 5kHz; HIGH PHASE MARGIN; PEAKING: 0.14dB; –3dB: 4.27kHz 100 1k 10k FREQUENCY OFFSET (Hz) 100k 3 0 1.5 –3 –6 LOOP GAIN (dB) 1.3 1.1 0.9 0.7 0.5 –9 –12 –15 –18 –21 2pF LOAD 10pF LOAD 0.3 LOOP BW = 100Hz; NORMAL PHASE MARGIN; PEAKING: 0.
Data Sheet AD9558 INPUT/OUTPUT TERMINATION RECOMMENDATIONS 10pF 0.1µF XOA 0.1µF XOB 10pF Figure 30. AC-Coupled LVDS or HSTL Output Driver (100 Ω resistor can go on either side of decoupling capacitors and should be as close as possible to the destination receiver.) Figure 33. System Clock Input (XOA, XOB) in Crystal Mode (The recommended CLOAD = 10 pF is shown. The values of the 10 pF shunt capacitors shown here should equal the CLOAD of the crystal.
AD9558 Data Sheet GETTING STARTED CHIP POWER MONITOR AND STARTUP The AD9558 monitors the voltage on the power supplies at power-up. When DVDD3 is greater than 2.35 V ± 0.1 V and DVDD and AVDD are greater than 1.4 V ± 0.05 V, the device generates a 20 ms reset pulse. The power-up reset pulse is internal and independent of the RESET pin. This internal power-up reset sequence eliminates the need for the user to provide external power supply sequencing.
Data Sheet AD9558 Program the System Clock and Free Run Tuning Word Program the Clock Distribution Outputs The system clock multiplier (SYSCLK) parameters are at Register 0x0100 to Register 0x0108, and the free run tuning word is at Register 0x0300 to Register 0x0303. Use the following steps for optimal performance: The APLL output goes to the clock distribution block. The clock distribution parameters reside in Register 0x0500 to Register 0x0509. They include the following: 1. 2. 3. 4. 5.
AD9558 Data Sheet Program the Digital Phase-Locked Loop (DPLL) Program the Reference Profiles The DPLL parameters reside in Register 0x0300 to Register 0x032E. They include the following: The reference profile parameters reside in Register 0x0700 to Register 0x07E6. The AD9558 evaluation software contains a wizard that calculates these values based on the user’s input frequency. See the Reference Profiles section for details on programming these functions.
Data Sheet AD9558 THEORY OF OPERATION XO OR XTAL SYNC RESET PINCONTROL M0 M1 M2 M3 M4 M5 M6 M7 IRQ XO FREQUENCIES 10MHz TO 180MHz XTAL: 10MHz TO 50MHz ÷M0 TO ÷M3b ARE 10-BIT INTEGER DIVIDERS 1 2kHz TO 1.
AD9558 Data Sheet REFERENCE CLOCK INPUTS Reference Validation Timer Four pairs of pins provide access to the reference clock receivers. To accommodate input signals with slow rising and falling edges, both the differential and single-ended input receivers employ hysteresis. Hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate. Each reference input has a dedicated validation timer.
Data Sheet AD9558 In the automatic modes, a fully automatic priority-based algorithm selects which reference is the active reference. When programmed for an automatic mode, the device chooses the highest priority valid reference. When both references have the same priority, REFA gets preference over REFB. However, the reference position is used only as a tie-breaker and does not initiate a reference switch.
AD9558 Data Sheet TDC/PFD DPLL Digitally Controlled Oscillator Free Run Frequency The phase-frequency detector (PFD) is an all-digital block. It compares the digital output from the TDC (which relates to the active reference edge) with the digital word from the feedback block. It uses a digital code pump and digital integrator (rather than a conventional charge pump and capacitor) to generate the error signal that steers the DCO frequency toward phase lock.
Data Sheet AD9558 DPLL Phase Lock Detector The DPLL contains an all-digital phase lock detector. The user controls the threshold sensitivity and hysteresis of the phase detector via the profile registers. The phase lock detector behaves in a manner analogous to water in a tub (see Figure 38). The total capacity of the tub is 4096 units with −2048 denoting empty, 0 denoting the 50% point, and +2048 denoting full. The tub also has a safeguard to prevent overflow.
AD9558 Data Sheet LOOP CONTROL STATE MACHINE Switchover Switchover occurs when the loop controller switches directly from one input reference to another. The AD9558 handles a reference switchover by briefly entering holdover mode, loading the new DPLL parameters, and then immediately recovering. During the switchover event, however, the AD9558 preserves the status of the lock detectors to avoid phantom unlock indications.
Data Sheet AD9558 SYSTEM CLOCK (SYSCLK) SYSTEM CLOCK INPUTS Functional Description The SYSCLK circuit provides a low jitter, stable, high frequency clock for use by the rest of the chip. The XOA and XOB pins connect to the internal SYSCLK multiplier. The SYSCLK multiplier can synthesize the system clock by connecting a crystal resonator across the XOA and XOB input pins or by connecting a low frequency clock source.
AD9558 Data Sheet System Clock Stability Timer Because the reference monitors depend on the system clock being at a known frequency, it is important that the system clock be stable before activating the monitors. At initial powerup, the system clock status is not known, and, therefore, it is reported as being unstable. After the part has been programmed, the system clock PLL (if enabled) eventually locks.
Data Sheet AD9558 OUTPUT PLL (APLL) A diagram of the output PLL (APLL) is shown in Figure 39. Calibration of the APLL must be performed at startup and when the nominal input frequency to the APLL changes by more than ±100 ppm, although the APLL maintains lock over voltage and temperature extremes without recalibration. Calibration centers the dc operating voltage at the input to the APLL VCO. INTEGER DIVIDER ÷N2 OUTPUT PLL DIVIDER (APLL) FROM DPLL PFD CP LF TO CLOCK DISTRIBUTION VCO2 3.35GHz TO 4.
AD9558 Data Sheet CLOCK DISTRIBUTION ÷M0 RF DIVIDER 1 ÷3 TO ÷11 MAX 1.25GHz FRAME SYNC MODE ONLY ÷M1 OUT01 OUT01 OUT11 OUT11 OUT21 FROM APLL (3.35GHz TO 4.05GHz) OUT21 RF DIVIDER 2 ÷3 TO ÷11 MAX 1.25GHz ÷M2 OUT31 OUT31 OUT41 OUT41 SYNC SIGNAL TO M0 TO M3 DIVIDERS CHANNEL SYNC BLOCK ÷M3 FRAME SYNC FRAME SYNC ENGAGED SIGNAL Fsync_ALIGN_METHOD SELECTED INPUT FRAME PULSE ÷M3b FRAME SYNC BLOCK ×2 OUT51 OUT51 FRAME SYNC MONITOR OUT0, OUT1, OUT2, OUT3, OUT4: 360kHz TO 1.
Data Sheet AD9558 A channel can be programmed to ignore the sync function by setting the mask Channel x sync bits in Register 0x0500[7:4]. When programmed to ignore the sync, the channel ignores both the user initiated sync signal and the zero delay initiated sync signals, and the channel divider starts toggling, provided that the APLL is calibrated and locked, or if the APLL locked controlled sync bit (Register 0x0405[3]) is set.
AD9558 Data Sheet FRAME SYNCHRONIZATION The AD9558 provides frame synchronization function/mode. With this function, the AD9558 can take a pair consisting of a reference clock and a 2 kHz or 8 kHz frame pulse as input signals and generate a pair consisting of a synchronized output clock and an output frame pulse while the output frame pulse is synchronized with the input frame pulse also.
Data Sheet AD9558 M3b DIVIDER/OUT5 PROGRAMMING IN FRAME SYNCHRONIZATION MODE This means that in frame synchronization mode, the total divide ratio between the RF divider and OUT5 is M0 × M3 × M3b. In frame synchronization mode, the clock distribution signal path for OUT5 is changed, as follows: the OUT5 signal goes from the RF divider to the M0 divider, and then to the M3 and M3b dividers.
AD9558 Data Sheet STATUS AND CONTROL MULTIFUNCTION PINS (M7 TO M0) The AD9558 has eight digital CMOS I/O pins (M7 to M0) that are configurable for a variety of uses. To use these functions, the user must enable them by writing a 0x01 to Register 0x0200. The function of these pins is programmable via the register map. Each pin can control or monitor an assortment of internal functions based on the contents of Register 0x0201 to Register 0x0208.
Data Sheet AD9558 WATCHDOG TIMER EEPROM The watchdog timer is a general purpose programmable timer. To set the timeout period, the user writes to the 16-bit watchdog timer register (Address 0x0210 to Address 0x0211). A value of 0b in this register disables the timer. A nonzero value sets the timeout period in milliseconds (ms), giving the watchdog timer a range of 1 ms to 65.535 sec. The relative accuracy of the timer is approximately 0.1% with an uncertainty of 0.5 ms.
AD9558 Data Sheet Table 21. EEPROM Controller Instruction Set Instruction Value (Hex) 0x00 to 0x7F Instruction Type Data Bytes Required 3 0x80 I/O update 1 0xA0 Calibrate 1 0xA1 Distribution sync 1 0xB0 to 0xCF Condition 1 0xFE Pause 1 0xFF End 1 Description A data instruction tells the controller to transfer data to or from the device settings part of the register map. A data instruction requires two additional bytes that together, indicate a starting address in the register map.
Data Sheet AD9558 A pause instruction, like an end instruction, is stored at the end of a sequence of instructions in the scratch pad. When the controller encounters a pause instruction during an upload sequence, it keeps the EEPROM address pointer at its last value. This way the user can store a new instruction sequence in the scratch pad and upload the new sequence to the EEPROM. The new sequence is stored in the EEPROM address locations immediately following the previously saved sequence.
AD9558 Data Sheet EEPROM Conditional Processing The condition tag board is a table maintained by the EEPROM controller. When the controller encounters a condition instruction, it decodes the B1 through CF instructions as Condition = 1 through Condition = 8, respectively, and tags that particular condition in the condition tag board.
Data Sheet AD9558 Table 23 lists a sample EEPROM download instruction sequence. It illustrates the use of condition instructions and how they alter the download sequence. The table begins with the assumption that no conditions are in effect. That is, the most recently executed condition instruction is either B0 or no conditional instructions have been processed. Table 23. EEPROM Conditional Processing Example Instruction 0x08 0x01 0x00 0xB1 0x19 0x04 0x00 0xB2 0xB3 0x07 0x05 0x00 0x0A 0xB0 0x80 0x0A 4.
AD9558 Data Sheet Programming the EEPROM to Configure an M Pin to Control Synchronization of Clock Distribution The default EEPROM loading sequence from Register 0x0E10 to Register 0x0E16 is unchanged. The following steps must be inserted into the EEPROM storage sequence: A special EEPROM loading sequence is required to use the EEPROM to load the registers and to use an M pin to enable/disable outputs. To control the output sync function by using an M pin, perform the following steps: 1. 2. 3.
Data Sheet AD9558 SERIAL CONTROL PORT The AD9558 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The AD9558 serial control port is compatible with most synchronous transfer formats, including I²C, Motorola SPI, and Intel SSR protocols. The serial control port allows read/write access to the AD9558 register map. In SPI mode, single or multiple byte transfers are supported.
AD9558 Data Sheet Write SPI Instruction Word (16 Bits) If the instruction word indicates a write operation, the payload is written into the serial control port buffer of the AD9558. Data bits are registered on the rising edge of SCLK. The length of the transfer (1, 2, or 3 bytes or streaming mode) depends on the W0 and W1 bits (see Table 25) in the instruction byte.
Data Sheet AD9558 CS SCLK DON'T CARE R/W W1 W0 A12 A11 A10 A9 SDIO DON'T CARE A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 09758-029 DON'T CARE Figure 46.
AD9558 Data Sheet CS tS tC tCLK tHIGH tLOW tDS SCLK SDIO BIT N BIT N + 1 Figure 51. Serial Control Port Timing—Write Table 28.
Data Sheet AD9558 The transfer of data is shown in Figure 52. One clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. I²C SERIAL PORT OPERATION The I2C interface has the advantage of requiring only two control pins and is a de facto standard throughout the I2C industry.
AD9558 Data Sheet Data Transfer Process per transfer is unrestricted. In write mode, the first two data The master initiates data transfer by asserting a start condition. This indicates that a data stream follows. All I²C slave devices connected to the serial bus respond to the start condition. bytes immediately after the slave address byte are the internal memory (control registers) address bytes, with the high address byte first.
Data Sheet AD9558 Data Transfer Format Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. S Slave address A W E A RAM address high byte A RAM address low byte A RAM Data 0 A RAM Data 1 A RAM Data 2 A P Send byte format—the send byte protocol is used to set up the register address for subsequent reads.
AD9558 Data Sheet PROGRAMMING THE I/O REGISTERS The register map spans an address range from 0x0000 through 0x0E3C. Each address provides access to 1 byte (eight bits) of data. Each individual register is identified by its four-digit hexadecimal address (for example, Register 0x0A10). In some cases, a group of addresses collectively defines a register. In general, when a group of registers defines a control parameter, the LSB of the value resides in the D0 position of the register with the lowest address.
Data Sheet AD9558 THERMAL PERFORMANCE Table 31. Thermal Parameters for the 64-Lead LFCSP Package Symbol θJA θJMA θJMA θJB θJC ΨJT 1 2 Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board1 Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
AD9558 Data Sheet POWER SUPPLY PARTITIONS The AD9558 power supplies are divided into four groups: DVDD3, DVDD, AVDD3, and AVDD. All power and ground pins should be connected, even if certain blocks of the chip are powered down. RECOMMENDED CONFIGURATION FOR 3.3 V SWITCHING SUPPLY The ADP7104 is another good choice for converting 3.3 V to 1.8 V.
Data Sheet AD9558 PIN PROGRAM FUNCTION DESCRIPTION The AD9558 supports both hard pin and soft pin program function with the on-chip ROM containing the predefined configurations. When a pin program function is enabled and initiated, the selected predefined configuration is transferred from the ROM to the corresponding registers to configure the part into the desired state.
AD9558 Data Sheet Table 33. Preset Output Frequencies for Hard Pin and Soft Pin Programming Freq ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Frequency (MHz) 19.44 25 125 156.7071 622.08 625 644.53125 657.421875 660.184152 666.5143 669.3266 672.1627 690.5692 693.4830 698.8124 704.380580 Hard Pin Program PINCONTROL = High M3 M2 M1 0 0 0 0 0 ½ 0 0 1 0 ½ 0 0 ½ ½ 0 ½ 1 0 1 0 0 1 ½ 0 1 1 ½ 0 0 ½ 0 ½ ½ 0 1 ½ ½ 0 ½ ½ ½ ½ ½ 1 ½ 1 0 Frequency Description 19.44 MHz 25 MHz 125 MHz 156.25 MHz × 1027/1024 622.
Data Sheet AD9558 • SOFT PIN PROGRAMMING OVERVIEW The soft pin program function is controlled by a dedicated register section (Address 0x0C00 to Address 0x0C08). The purpose of soft pin program is to use the register bits to mimic the hard pins for the configuration section. When in soft pin program mode, both SPI and I2C port are available. • • • • • • Address 0x0C00[0] enables accessibility to Address 0x0C01 and Address 0x0C02 (Soft Pin Section 1). This bit must be set in soft pin mode.
AD9558 Data Sheet REGISTER MAP Register addresses that are not listed in Table 35 are not used, and writing to those registers has no effect. The user should write the default value to sections of registers marked reserved. R = read-only. A = autoclear. E = excluded from EEPROM loading. L = live (I/O update not required for register to take effect or for a read-only register to be updated). Table 35.
Data Sheet Reg Addr (Hex) 0x0209 Opt 0x020A Name IRQ pin output mode AD9558 D7 IRQ mask D6 Reserved Reserved 0x020B D4 SYSCLK unlocked SYSCLK locked Freerun Pin program end Holdover Reserved 0x020C Switching 0x020D Closed Reserved 0x020E Reserved REFB validated 0x020F Reserved REFD validated 0x0210 0x0211 0x0300 0x0301 0x0302 0x0303 0x0304 REFB fault cleared REFD fault cleared Watchdog Timer 1 Freerun frequency TW Reserved Reserved Digital oscillator control 0x0305 0x0306 0x0307
AD9558 Reg Addr (Hex) 0x0323 0x0324 0x0325 0x0326 0x0327 0x0328 0x0329 0x032A 0x032B 0x032C 0x032D 0x032E Opt L L L L L L L L L L L L Data Sheet Name Base loop Filter A coefficient set (normal phase margin of 70º) D7 D6 D5 D4 Reserved Reserved Reserved Reserved Output PLL (APLL) 0x0400 APLL charge pump 0x0401 APLL N divider 0x0402 0x0403 APLL loop filter control 0x0404 0x0405 0x0406 0x0407 0x0408 APLL VCO control 0x0501 Channel 0 0x0502 0x0503 0x0504 0x0505 Channel 1 0x0507 0x0508 Channel
Data Sheet Reg Addr (Hex) Opt Name Reference Inputs 0x0600 Reference power-down 0x0601 Reference logic type 0x0602 Reference priority 0x0603 Frame Synchronization Mode 0x0640 En frame sync 0x0641 Frame sync options Profile A (for REFA) 0x0700 L Reference period (up to 0x0701 L 1.
AD9558 Data Sheet Reg Addr (Hex) Opt Name Profile B (for REFB) 0x0740 L Reference period (up to 0x0741 L 1.
Data Sheet Reg Addr (Hex) Opt Name Profile C (for REFC) 0x0780 L Reference period (up to 0x0781 L 1.
AD9558 Data Sheet Reg Addr (Hex) Opt Name DPLL Profile D (for REFD) 0x07C0 L Reference period (up to 0x07C1 L 1.
Data Sheet AD9558 Reg Addr (Hex) D7 D6 D5 D4 D3 D2 D1 D0 Def DCO PD SYSCLK PD Ref input PD TDC PD APLL PD Clock dist PD Full PD 00 0x0A01 Loop mode Soft reset exclude regmap Reserved User holdover User freerun User ref in manual switchover mode 00 0x0A02 Cal/sync Opt Name Operational Controls 0x0A00 Power-down Reserved 0x0A03 A 0x0A04 A 0x0A05 A 0x0A06 A 0x0A07 A 0x0A08 A Reserved 0x0A09 A Reserved 0x0A0A A Increment phase offset 0x0A0B A Manual reference
AD9558 Data Sheet Reg Addr (Hex) Opt Name D7 D6 D5 Read-Only Status (Accessible During EEPROM Transactions) 0x0D00 R, L EEPROM Reserved D4 D3 D2 D1 D0 Def Fault detected Load in progress Save in progress N/A 0x0D01 R, L SYSCLK and PLL status All PLLs locked APLL VCO status Pin program ROM load process APLL cal in progress APLL lock SYSCLK stable SYSCLK lock detect N/A 0x0D02 R, L IRQ monitor events SYSCLK unlocked SYSCLK locked APLL unlocked APLL lock detect APLL cal ended AP
Data Sheet Reg Addr (Hex) Opt Name EEPROM Storage Sequence 0x0E10 E EEPROM ID 0x0E11 E 0x0E12 E 0x0E13 E System clock 0x0E14 E 0x0E15 E 0x0E16 E I/O update 0x0E17 E General 0x0E18 E 0x0E19 E 0x0E1A E DPLL 0x0E1B E 0x0E1C E 0x0E1D E APLL 0x0E1E E 0x0E1F E 0x0E20 E Clock dist 0x0E21 E 0x0E22 E 0x0E23 E I/O update 0x0E24 E Reference inputs 0x0E25 E 0x0E26 E 0x0E27 E 0x0E28 E 0x0E29 E 0x0E2A E Profile REFA 0x0E2B E 0x0E2C E 0x0E2D E Profile REFB 0x0E2E E 0x0E2F E 0x0E30 E Profile REFC 0x0E31 E 0x0E32 E 0x0E33
AD9558 Data Sheet REGISTER MAP BIT DESCRIPTIONS SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005) Table 36. Serial Configuration (Note that the contents of Register 0x0000 are not stored to the EEPROM.) Address 0x0000 Bits 7 Bit Name SDO enable 6 LSB first/increment address 5 Soft reset [4:0] Reserved Description Enables SPI port SDO pin. 1 = 4-wire (SDO pin enabled). 0 (default) = 3-wire. Bit order for SPI port. 1 = least significant bit and byte first.
Data Sheet AD9558 SYSTEM CLOCK (REGISTER 0x0100 TO REGISTER 0x0108) Table 42. System Clock PLL Feedback Divider (N3 Divider) Address 0x0100 Bits [7:0] Bit Name SYSCLK N3 divider Description System clock PLL feedback divider value: 4 ≤ N3 ≤ 255 (default: 0x08). Table 43. SYSCLK Configuration Address 0x0101 Bits [7:5] 4 Bit Name Reserved Load from ROM (read-only) 3 SYSCLK XTAL enable [2:1] SYSCLK P divider 0 SYSCLK doubler enable Description Reserved.
AD9558 Data Sheet GENERAL CONFIGURATION (REGISTER 0x0200 TO REGISTER 0x0214) Multifunction Pin Control (M0 to M7) and IRQ Pin Control (Register 0x0200 to Register 0x0209) Note that the default setting for the M0 to M5 multifunction pins and the IRQ is that of a 3-level logic input; M6 and M7 are unused inputs at startup. After startup, M0 to M7 are 2-level inputs or 2-level outputs, based on the settings of Register 0x0200 to Register 0x0208.
Data Sheet AD9558 IRQ MASK (REGISTER 0x020A TO REGISTER 0x020F) The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (0x0D02 to 0x0D09). When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts. Table 48.
AD9558 Data Sheet Table 52.
Data Sheet AD9558 Table 57. Fixed Closed-Loop Phase Lock Offset Address 0x030C Bits [7:0] 0x030D [7:0] 0x030E [7:0] 0x030F [7:6] [5:0] Bit Name Fixed phase lock offset (signed; ps) Reserved Fixed phase lock offset (signed; ps) Description Fixed phase lock offset, Bits[7:0]. Default: 0x00. Fixed phase lock offset, Bits[15:8]. Default 0x00. Fixed phase lock offset, Bits[23:16]. Default: 0x00. Reserved; default: 0x0. Fixed phase lock offset, Bits[29:24]. Default: 0x00. Table 58.
AD9558 Data Sheet Table 61. History Mode Address 0x0316 Bits [7:5] 4 Bit Name Reserved Single sample fallback 3 Persistent history [2:0] Incremental average Description Reserved. Controls holdover history. If tuning word history is not available for the reference that was active just prior to holdover, then: 0 (default) = uses the free run frequency tuning word register value. 1 = uses the last tuning word from the DPLL. Controls holdover history initialization.
Data Sheet AD9558 Table 63. Base Digital Loop Filter with Normal Phase Margin (PM = 70°, BW = 0.
AD9558 Data Sheet Address Bits [2:0] Bit Name 0x0404 [7:1] 0 Reserved Bypass internal Rzero 0x0405 [7:4] 3 Reserved APLL locked controlled sync [2:1] 0 Reserved Manual APLL VCO calibration 1 Description Pole 1 Cp1. Cp1 (pF) Bit 2 Bit 1 Bit 0 0 0 0 0 20 0 0 1 80 0 1 0 100 0 1 1 20 1 0 0 40 1 0 1 100 1 1 0 120 (default) 1 1 1 Default: 0x00. 0 (default) = uses the internal Rzero resistor.
Data Sheet AD9558 OUTPUT CLOCK DISTRIBUTION (REGISTER 0x0500 TO REGISTER 0x0515) Table 67. Clock Distribution Output Synchronization Settings Address 0x0500 Bits 7 Bit Name Mask Channel 3 sync 6 Mask Channel 2 sync 5 Mask Channel 1 sync 4 Mask Channel 0 sync 3 2 Reserved Sync source selection [1:0] Automatic sync mode Description Masks the synchronous reset to the Channel 3 (M3) divider. 0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs. 1 = masked.
AD9558 Data Sheet Table 68. Distribution OUT0 Setting Address 0x0501 Bits 7 Bit Name Enable 3.3 V CMOS driver [6:4] OUT0 format [3:2] OUT0 polarity 1 OUT0 drive strength 0 Enable OUT0 Description 0 (default) = disables 3.3 V CMOS driver; the OUT5 1.8 V logic is controlled by Register 0x0501[6:4]. 1 = enables 3.3 V CMOS driver as operating mode of OUT0. This bit should be enabled only if Bits[6:4] are in CMOS mode. This control is valid when Register 0x0501[7] = 0.
Data Sheet AD9558 Table 70.
AD9558 Data Sheet Table 73. Clock Distribution Channel 3 and OUT5 Driver Settings Address 0x050F Bits 7 Bit Name Enable 3.
Data Sheet AD9558 REFERENCE INPUTS (REGISTER 0x0500 TO REGISTER 0x0507) Table 74. Reference Power-Down1 Address 0x0600 1 Bits [7:4] 3 2 1 0 Bit Name Reserved REFD power-down REFC power-down REFB power-down REFA power-down Description Default: 0x0 Power down REFD input receiver (default: not powered down). Power down REFC input receiver (default: not powered down). Power down REFB input receiver (default: not powered down). Power down REFA input receiver (default: not powered down).
AD9558 Data Sheet FRAME SYNCHRONIZATION (REGISTER 0x0640 TO REGISTER 0x0641) Table 77. Frame Sync Setting Address 0x0640 Bit(s) [7:1] 0 Bit Name Reserved Enable Fsync 0x0641 [7:4] 3 Reserved Validate Fsync ref 2 Fsync one shot 1 Fsync arm method 0 Arm soft Fsync Description Reserved; default: 0x00. Enable frame synchronization. 0 (default) = frame synchronization disabled. 1 = frame synchronization enabled. Reserved; default: 0x00.
Data Sheet AD9558 DPLL PROFILE REGISTERS (REGISTER 0x0700 TO REGISTER 0x07E6) Note that the default values of the REFA and REFC profiles are as follows: input frequency=19.44 MHz, output frequency = 622.08 MHz/ 155.52 MHz, loop bandwidth = 400 Hz, normal phase margin, inner tolerance = 5%, and outer tolerance = 10%. The default values of the REFB and REFD profiles are as follows: input frequency = 8 kHz, output frequency = 622.08 MHz/155.
AD9558 Data Sheet Table 83. DPLL Loop BW Scaling Factor—REFA Profile1 Address 0x070F 0x0710 Bits [7:0] [7:0] Bit Name DPLL loop BW scaling factor (unit of 0.1 Hz) 0x0711 [7:1] 0 Reserved BW scaling factor 1 Description Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4). Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01). The default for Register 0x070F to Register 0x0710 = 0x01F4 = 500 (50 Hz loop bandwidth).
Data Sheet AD9558 REFB Profile (Register 0x0740 to Register 0x0766) REFB Profile Register 0x0740 to Register 0x0766 are identical to REFA Profile Register 0x0700 to Register 0x0726. REFC Profile (Register 0x0780 to Register 0x07A6) REFC Profile Register 0x0780 to Register 0x07A6 are identical to REFA Profile Register 0x0700 Register 0x0726. REFD Profile (Register 0x07C0 to Register 0x07E6) REFD Profile Register 0x07C0 to Register 0x07E6 are identical to REFA Profile Register 0x0700 to Register 0x0726.
AD9558 Data Sheet Reset Functions (Register 0x0A03) Table 92. Reset Functions1 Address 0x0A03 (autoclear) 1 Bits 7 6 5 4 3 2 1 Bit Name Reserved Clear LF Clear CCI Reserved Clear auto sync Clear TW history Clear all IRQs 0 Clear watchdog timer Description Default: 0b. Setting this bit clears the digital loop filter (intended as a debug tool). Setting this bit clears the CCI filter (intended as a debug tool). Default: 0b.
Data Sheet AD9558 Table 96. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit Address 0x0A07 Bits [7:5] 4 3 2 1 0 Bit Name Reserved History updated Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Description Reserved Clears history updated IRQ Clears frequency unclamped IRQ Clears frequency clamped IRQ Clears phase slew unlimited IRQ Clears phase slew limited IRQ Table 97.
AD9558 Address 0x0A0D Bits [7:4] 3 2 1 0 Data Sheet Bit Name Reserved Ref Mon Bypass D Ref Mon Bypass C Ref Mon Bypass B Ref Mon Bypass A Description Reserved. Bypasses the reference monitor for Reference D (default: 0). Bypasses the reference monitor for Reference C (default: 0). Bypasses the reference monitor for Reference B (default: 0). Bypasses the reference monitor for Reference A (default: 0). QUICK IN/OUT FREQUENCY SOFT PIN CONFIGURATION (REGISTER 0x0C00 TO REGISTER 0x0C08) Table 100.
Data Sheet Address 0x0C05 AD9558 Bits [7:4] [3:2] Bit Name Reserved Channel 1 output frequency scale [1:0] Channel 0 output frequency scale [7:5] 4 Reserved Sel high PM base loop filter [3:2] DPLL loop BW [1:0] Reference input frequency tolerance 0x0C07 [7:1] 0 Reserved Soft pin start transfer 0x0C08 [7:1] 0 Reserved Soft pin reset 0x0C06 1 Description Reserved. Scales the selected output frequency (defined by Register 0x0C01[7:4]) for the Channel Divider 1 output.
AD9558 Data Sheet Table 102. SYSCLK Status Address 0x0D01 Bits 7 6 Bit Name Reserved DPLL_APLL_Lock 5 All PLLs locked 4 APLL VCO status 3 2 APLL cal in process APLL lock 1 System clock stable 0 SYSCLK lock detect Description Reserved. Indicates the status of the DPLL and APLL. 0 = either the DPLL or the APLL is unlocked. 1 = both the DPLL and APLL are locked. Indicates the status of the system clock PLL, APLL, and DPLL. 0 = system clock PLL or APLL or DPLL is unlocked.
Data Sheet AD9558 Table 105.
AD9558 Data Sheet DPLL Status, Input Reference Status, Holdover History, and DPLL Lock Detect Tub Levels (Register 0x0D08 to Register 0x0D14) Table 108.
Data Sheet AD9558 Table 112. Digital PLL Lock Detect Tub Levels1 Address 0x0D11 Bits [7:0] Bit Name Phase tub 0x0D12 [7:4] [3:0] 0x0D13 [7:0] Frequency tub 0x0D14 [7:4] [3:0] Reserved Frequency tub Description Read-only digital PLL lock detect bathtub level, Bits[7:0]; see the DPLL Frequency Lock Detector section for details. Reserved. Read-only digital PLL lock detect bathtub level, Bits[11:8]; see the DPLL Frequency Lock Detector section for details.
AD9558 Data Sheet EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3C) The default settings of Register 0x0E10 to Register 0x0E3C contain the default EEPROM instruction sequence. The tables in this section provide descriptions of the register defaults, based on the assumption that the controller has been instructed to carry out an EEPROM storage sequence in which all of the registers are stored and loaded by the EEPROM. Table 114.
Data Sheet AD9558 Table 117. EEPROM Storage Sequence for Output PLL Settings Address 0x0E1D Bits [7:0] 0x0E1E [7:0] 0x0E1F [7:0] Bit Name APLL Description The default value of this register is 0x08, which the controller interprets as a data instruction. Its decimal value is 8, which tells the controller to transfer nine bytes of data (8 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments the EEPROM address pointer.
AD9558 Data Sheet Table 121. EEPROM Storage Sequence for REFA Profile Settings Address 0x0E2A Bits [7:0] 0x0E2B [7:0] 0x0E2C [7:0] Bit Name REFA Profile Description The default value of this register is 0x26, which the controller interprets as a data instruction. Its decimal value is 38, so this tells the controller to transfer 39 bytes of data (38 + 1), beginning at the address that is specified by the next two bytes.
Data Sheet AD9558 Table 125. EEPROM Storage Sequence for Operational Control Settings Address 0x0E37 Bits [7:0] 0x0E38 [7:0] 0x0E39 [7:0] Bit Name Operational controls Description The default value of this register is 0x0D, which the controller interprets as a data instruction. Its decimal value is 13, so this tells the controller to transfer 14 bytes of data (13 + 1), beginning at the address specified by the next two bytes.
AD9558 Data Sheet Table 129.
Data Sheet AD9558 Table 130.
AD9558 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.23 0.18 0.60 MAX 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 16 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-14-2012-A 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.85 0.