Dual Input Network Clock Generator/Synchronizer AD9549 FEATURES APPLICATIONS Flexible reference inputs Input frequencies: 8 kHz to 750 MHz Two reference inputs Loss of reference indicators Auto and manual holdover modes Auto and manual switchover modes Smooth A-to-B phase transition on outputs Excellent stability in holdover mode Programmable 16 + 1-bit input divider, R Differential HSTL clock output Output frequencies to 750 MHz Low jitter clock doubler for frequencies of >400 MHz Single-ended CMOS outpu
AD9549 TABLE OF CONTENTS Features .............................................................................................. 1 Power-Up ......................................................................................... 42 Applications ....................................................................................... 1 Power-On Reset .......................................................................... 42 General Description ...........................................................
AD9549 REVISION HISTORY 12/10—Rev. C to Rev. D Changes to IAVDD (Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30, Pin44, Pin 45) Parameter ................................................................. 4 Changes to Total Power Dissipation Parameter and Added Endnote 4 ........................................................................................... 5 Changes to Pin 59 Description ......................................................11 Changes to Direct Digital Synthesizer (DDS) Section ..............
AD9549 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%. AVSS = 0 V, DVSS = 0 V, unless otherwise noted. Table 1.
AD9549 Parameter SYSTEM CLOCK INPUT SYSCLK PLL Bypassed Input Capacitance Input Resistance Internally Generated DC Bias Voltage2 Differential Input Voltage Swing3 SYSCLK PLL Enabled Input Capacitance Input Resistance Internally Generated DC Bias Voltage2 Differential Input Voltage Swing3 Crystal Resonator with SYSCLK PLL Enabled Motional Resistance CLOCK OUTPUT DRIVERS HSTL Output Driver Differential Output Voltage Swing Common-Mode Output Voltage2 CMOS Output Driver Output Voltage High (VOH) Output Voltage
AD9549 AC SPECIFICATIONS fS = 1 GHz, DAC RSET = 10 kΩ, power supply pins within the range specified in the DC Specifications section, unless otherwise noted. Table 2.
AD9549 Parameter CMOS Output Driver (AVDD3/Pin 37) @ 3.3 V Frequency Range Duty Cycle Rise Time/Fall Time (20-80%) CMOS Output Driver (AVDD3/Pin 37) @ 1.
AD9549 Parameter LOCK DETECTION Phase Lock Detector Time Threshold Programming Range Time Threshold Resolution Lock Time Programming Range Unlock Time Programming Range Frequency Lock Detector Normalized Frequency Threshold Programming Range Normalized Frequency Threshold Programming Resolution Lock Time Programming Range Unlock Time Programming Range Min 0 Max Unit Test Conditions/Comments 2097 μs ps sec sec FPFD_gain = 200 FPFD_gain = 200 In power-of-2 steps In power-of-2 steps sec sec FPFD_gain
AD9549 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD_I/O) DAC Supply Voltage (AVDD3 Pins) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature THERMAL RESISTANCE Rating 2V 2V 3.6 V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance 3.
AD9549 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SCLK SDIO SDO CSB IO_UPDATE RESET PWRDOWN HOLDOVER REFSELECT S4 S3 AVDD AVSS DAC_OUTB DAC_OUT AVDD3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9549 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DAC_RSET AVDD3 AVDD3 AVDD AVDD AVSS AVDD FDBK_IN FDBK_INB AVSS OUT_CMOS AVDD3 AVDD OUT OUTB AVSS NOTES 1. NC = NO CONNECT. 2.
AD9549 Pin No. 20, 21 Input/ Output O 22 O 27 I 28 I 31 O 32 I 1.8 V CMOS CLKMODESEL 33, 39, 43, 52 34 O O GND 1.8 V HSTL AVSS OUTB 35 O 1.8 V HSTL OUT 37 I Power AVDD3 38 O 3.3 V CMOS OUT_CMOS 40 I Differential input FDBK_INB 41 I FDBK_IN 48 O 50 O 51 O 56 I/O Differential input Current set resistor Differential output Differential output 3.3 V CMOS 57 I/O 3.3 V CMOS HOLDOVER 58 I 3.3 V CMOS PWRDOWN 59 I 3.
AD9549 Pin No. 60 Input/ Output I Pin Type 3.3 V CMOS Mnemonic IO_UPDATE 61 I 3.3 V CMOS CSB 62 O 3.3 V CMOS SDO 63 I/O 3.3 V CMOS SDIO 64 I 3.3 V CMOS SCLK Exposed Die Pad O GND EPAD Description I/O Update. A logic transition from 0 to 1 on this pin transfers data from the I/O port registers to the control registers (see the Write section). This pin has an internal 50 kΩ pull-down resistor. Chip Select. Active low. When programming a device, this pin must be held low.
AD9549 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, AVDD, AVDD3, and DVDD are at nominal supply voltage; fS = 1 GHz, DAC RSET = 10 kΩ. –70 RMS JITTER (12kHz TO 20MHz): 0.18ps RMS JITTER (50kHz TO 80MHz): 0.24ps PHASE NOISE (dBc/Hz) –90 –100 –110 –120 –110 –120 –140 –140 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M –150 10 10M 100M –110 –120 –90 –100 –110 –120 –130 –140 –140 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 06744-004 –130 Figure 4.
AD9549 –70 RMS JITTER (12kHz TO 20MHz): 4.2ps –80 1.5 PHASE NOISE (dBc/Hz) 12kHz TO 20MHz RMS JITTER (ps) 2.0 1.0 0.5 –90 –100 –110 –120 –130 30 50 70 SYSTEM CLOCK PLL INPUT FREQUENCY (MHz) 90 –150 10 Figure 9. 12 kHz to 20 MHz RMS Jitter vs. System Clock PLL Input Frequency, SYSCLK = 1 GHz, fREF = 19.44 MHz, fOUT = 155.52 MHz RMS JITTER (12kHz TO 20MHz): 1.26ps RMS JITTER (50kHz TO 80MHz): 1.
AD9549 650 0.6 0.4 550 0.2 0 FREQUENCY= 600MHz TRISE (20→80%) = 104ps TFALL (80→20%) = 107ps V p-p = 1.17V DIFF. DUTY CYCLE = 50% –0.2 500 NOM SKEW 25°C, 1.8V SUPPLY SLOW SKEW 90°C, 1.7V SUPPLY –0.4 0 200 400 FREQUENCY (MHz) 600 800 –0.6 06744-012 450 0 0.5 1.0 1.5 TIME (ns) 2.0 2.5 06744-015 AMPLITUDE (V) AMPLITUDE (mV) 600 Figure 15. Typical HSTL Output Waveform, Nominal Conditions, DC-Coupled, Differential Probe Across 100 Ω load Figure 12.
AD9549 INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.01µF 0.01µF AD9549 1.8V HSTL OUTPUT 100Ω DOWNSTREAM DEVICE (HIGH-Z) 100Ω (OPTIONAL) AD9549 SELF-BIASING REF INPUT 0.01µF 06744-018 06744-020 0.01µF Figure 18. AC-Coupled HSTL Output Driver Figure 20. Reference Input 0.1µF 50Ω AD9549 1.8V HSTL OUTPUT AVDD/2 DOWNSTREAM DEVICE (HIGH-Z) 100Ω (OPTIONAL) AD9549 SELF-BIASING FDBK INPUT 0.1µF 06744-021 06744-019 50Ω Figure 19. DC-Coupled HSTL Output Driver Figure 21. FDBK_IN Input Rev.
AD9549 THEORY OF OPERATION OUT_CMOS OUT 2× DIGITAL PLL CORE ÷S FDBK_IN FREQ EST. REFSELECT REFA_IN PFD ÷R PROG. DIGITAL LOOP FILTER FREQUENCY TUNING WORD SLEW LIMIT DDS/DAC DAC_OUT REFB_IN EXTERNAL ANALOG LOW-PASS FILTER LOCK DETECT INPUT REF MONITOR HOLDOVER REF_CNTRL LOW NOISE CLOCK MULTIPLIER OOL AND LOR S1 TO S4 IRQ AND STATUS LOGIC CONTROL LOGIC AMP DIGITAL INTERFACE HOLDOVER SYSCLK 06744-022 SYSCLK PORT Figure 22.
AD9549 The PFD outputs a time series of digital words that are routed to the digital loop filter. The digital filter implementation offers many advantages: The filter response is determined by numeric coefficients rather than by discrete component values; there is no aging of components and, therefore, no drift of component value over time; there is no thermal noise in the loop filter; and there is no control node leakage current (which causes reference feedthrough in a traditional analog PLL).
AD9549 The DCO has a minimum frequency, fDCO[MIN] (see the DAC Output Characteristics section of the AC Specifications table). This minimum frequency imposes a lower bound, SMIN, on the feedback divider value, as well. error samples from the time-to-digital converter replaces the loop filter. A DDS replaces the VCO, which produces a frequency that is linearly related to the digital value provided by the loop filter. This is shown in Figure 25 with some additional detail.
AD9549 PHASE OFFSET 14 48 FREQUENCY TUNING WORD (FTW) 48 48 D Q 19 19 I-SET ANGLE TO 14 AMPLITUDE CONVERSION DAC+ DAC (14-BIT) DAC– 06744-025 48-BIT ACCUMULATOR fS Figure 25. DDS Block Diagram The null points imply the existence of transmission zeros placed at finite frequencies. While transmission zeros placed at infinity yield minimal phase delay, zeros placed closer to dc result in increased phase delay.
AD9549 In holdover mode, the AD9549 uses past tuning words when the loop is closed to determine its output frequency. Therefore, the loop must be successfully closed for holdover mode to work. Switching in and out of holdover mode can be either automatic or manual, depending on register settings. Typically, the AD9549 operates in closed-loop mode. In closedloop mode, the FTW values come from the output of the digital loop filter and vary with time.
AD9549 Phase Detector Gain Matching DIGITAL LOOP FILTER COEFFICIENTS Although the fine and coarse phase detectors use different means to make a timing measurement, it is essential that both have equivalent phase gain. Without proper gain matching, the closed-loop dynamics of the system cannot be properly controlled. Hence, the goal is to make PhaseGainCPD = PhaseGainFPD. To provide the desired flexibility, the loop filter has been designed with three programmable coefficients (α, β, and γ).
AD9549 The min(), max(), floor(), ceil() and round() functions are defined as follows: The three coefficients are implemented as digital elements, necessitating quantized values. Determination of the programmed coefficient values in this context follows. • The quantized α coefficient is composed of three factors, where α0, α1, and α2 are the programmed values for the α coefficient.
AD9549 LOCK DETECTION The resulting loop filter coefficients for the lower loop bandwidth, along with the necessary programming values, are shown as follows: Phase Lock Detection During the phase locking process, the output of the phase detector tends toward a value of 0, which indicates perfect alignment of the phase detector input signals. As the control loop works to maintain the alignment of the phase detector input signals, the output of the phase detector wanders around 0. α = 0.
AD9549 The phase lock detect signal is generated once the control logic observes that the output of the comparator has been in the true state for 2x periods of the P-divider clock (see the Digital Loop Filter section for a description of the P-divider). When the phase lock detect signal is asserted, it remains asserted until cleared by an unlock event or by a device reset.
AD9549 For example, if fR = 3 MHz, R = 5, FPFD_Gain = 200, and a frequency lock threshold of 1% is specified, the frequency lock detect threshold value is The values of the two frequency bounds are f PRESENT = FLDT = 2 5 = 170,667 round (1% × 3 × 10 6 ) × 2 10 × 10 7 × 200 × 6 3 × 10 Hence, 170,667 (0x00029AAB) is the value that should be stored in the frequency lock detect threshold bits.
AD9549 The following four values are needed to calculate the correct values of the reference monitor: System clock frequency, fS (usually 1 GHz) Reference input frequency, fR (in Hz) Error bound, E (1% = 0.01) Monitor window size (W) The monitor window size is the difference between the maximum and minimum number of counts accumulated between adjacent edges of the reference input.
AD9549 Use of Line Card Mode to Eliminate Runt Pulses Effect of Reference Input Switchover on Output Clock When two references are not in exact phase alignment and a transition is made from one to the other, it is possible that an extra pulse may be generated. This depends on the relative edge placement of the two references and the point in time that a switchover is initiated. To eliminate the extra pulse problem, an enable line card mode bit is provided (Register 0x01C1, Bit 4).
AD9549 When calculating frequency error for a hitless switchover environment such as Stratum 3, as defined in Telcordia GR-1244-CORE, the designer must consider the frequency error budget for the entire system. The frequency disturbance caused by a reference clock switchover in the AD9549 contributes to this budget.
AD9549 RESET FAILA & VALIDB & AUTOREFSEL & OVRDREFPIN REFA & HOLDOVER 1 REFB & HOLDOVER 2 REFA & HOLDOVER FA IL AU B & TO V RC AL O IDA O V& & VR A DH OV UT LD RD OR PI RE EF N FP S IN EL & & 3 FAILB & AUTOHOLD & OVRDHLDPIN & (VALIDA OR AUTOREFSEL OR OVRDREFPIN) & EL FS & E N R PI TO EF AU DR & VR IN DB O DP LI & HL A V D V O & RC VR O LA TO I FA AU VALIDB & AUTORCOV & OVRDHLDPIN VALIDA & AUTORCOV & OVRDHLDPIN FAILA & AUTOHOLD & OVRDHLDPIN & (VALIDB OR AUTOREFSEL OR OVRDREFPIN) FAILB & VALIDA &
AD9549 Reference Validation Timers Each of the two reference inputs has a dedicated validation timer. The status of these timers is used by the holdover state machine as part of the decision making process for reverting to a previously faulty reference. For example, suppose that a reference fails (that is, an LOR or OOL condition is in effect) and that the device is programmed to revert automatically to a valid reference when it recovers.
AD9549 OUTPUT FREQUENCY RANGE CONTROL artifacts of the sampling process and other spurs outside the filter bandwidth. The signal is then brought back on-chip to be converted to a square wave that is routed internally to the output clock driver or the 2× DLL multiplier. Under normal operating conditions, the output frequency is dynamically changing in response to the output of the digital loop filter. The loop filter can steer the DDS to any frequency between dc and fS/2 (with 48-bit resolution).
AD9549 FDBK_IN INPUTS VDD The feedback pins, FDBK_IN and FDBK_INB, serve as the input to the feedback path of the digital PLL. Typically, these pins are used to receive the signal generated by the DDS after it has been band-limited by the external reconstruction filter. + VB 1pF REFA_IN (OR REFB_IN) A diagram of the FDBK input pins is provided in Figure 40, which includes some of the internal components used to bias the input circuitry.
AD9549 The maintaining amp on the AD9549 SYSCLK pins is intended for 25 MHz, 3.2 mm × 2.5 mm AT cut fundamental mode crystals with a maximum motional resistance of 100 Ω.
AD9549 External Loop Filter (SYSCLK PLL) The loop bandwidth of the SYSCLK PLL multiplier can be adjusted by means of three external components, as shown in Figure 44. The nominal gain of the VCO is 800 MHz/V. The recommended component values are shown in Table 7. They establish a loop bandwidth of approximately 1.6 MHz with the charge pump current set to 250 μA. The default case is N = 40 and assumes a 25 MHz SYSCLK input frequency and generates an internal DAC sampling frequency (fS) of 1 GHz.
AD9549 DDS DDS PHASE OFFSET 48-BIT ACCUMULATOR 48 SPUR CANCELLATION ENABLE 14 I-SET 48-BIT FREQUENCY TURNING WORD (FTW) 14 48 D Q 19 19 ANGLE TO AMPLITUDE CONVERSION 14 0 14 1 DAC (14-BIT) DDS+ DDS– SYSCLK CH1 CANCELLATION PHASE OFFSET 4 9 2-CHANNEL HARMONIC FREQUENCY GENERATOR HEADROOM CORRECTION 0 CH1 CH2 HARMONIC NUMBER CH2 CANCELLATION PHASE OFFSET 4 CH1 GAIN 9 0 CH2 CH1 CANCELLATION MAGNITUDE CH2 CANCELLATION MAGNITUDE 1 SHIFT SHIFT 1 8 CH2 GAIN 8 HARMONIC SPUR CANCELLA
AD9549 Single-Ended CMOS Output For example, if fS = 1 GHz, PIO = 9, and δf/δt = 5 kHz/sec, then In addition to the high speed differential output clock driver, the AD9549 provides an independent, single-ended output, CMOS clock driver. It serves as a relatively low speed (<150 MHz) clock source. The origin of the signal generated by the CMOS clock driver is determined by the appropriate control bits in the I/O register map. The user can select one of two sources under program control.
AD9549 As an example, consider the following system conditions: The measurement error (ε) associated with the frequency estimator depends on the choice of the measurement interval parameter (K). These are related by ε= ρK floor (ρK ) − 1 fS = 400 MHz R=8 fREF_IN = 155.52 MHz ε0 = 0.00005 (that is, 50 ppm) −1 These conditions yield KMAX = 3185, which is the largest K value that can be programmed without causing the frequency estimator counter to overflow. With K = KMAX, Tmeas = 163.84 μs, and ε = 30.
AD9549 INTERNAL STATUS FLAGS REFA LOR 0 REFA OOL 1 REFA INVALID 0 REFB LOR 1 REFB OOL 0 REFB INVALID 1 REF LOR REF OOL REF INVALID PHASE LOCK PHASE LOCK DETECT STATUS PIN (1 OF 4) FREQ. LOCK FREQUENCY LOCK DETECT IRQ IRQ REFAB LOR REFAB OOL REFAB INVALID REFAB PHASE LOCK FREQUENCY LOCK IRQ 06744-049 STATUS PIN CONTROL REGISTER (1 OF 4) Figure 49.
AD9549 The DDS output frequency listed in Table 8 assumes that the internal DAC sampling frequency (fS) is 1 GHz. These frequencies scale 1:1 with fS, meaning that other startup frequencies are available by varying the SYSCLK frequency. Interrupt Request (IRQ) Any one of the four status pins (S1 to S4) can be programmed as an IRQ pin. If a status pin is programmed as an IRQ pin, the state of the internal IRQ flag appears on that pin.
AD9549 THERMAL PERFORMANCE Table 9. Thermal Parameters Symbol θJA θJMA θJMA θJB θJC ΨJT Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board Junction-to-ambient thermal resistance, 0.0 m/sec air flow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec air flow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.0 m/sec air flow per JEDEC JESD51-6 (moving air) Junction-to-board thermal resistance, 1.
AD9549 POWER-UP POWER-ON RESET On initial power-up, it is recommended that the user apply a RESET pulse, at least 75 ns in duration, on Pin 59 after both of the following two conditions are met: • • The 3.3 V supply is greater than 2.35 V ± 0.1 V. The 1.8 V supply is greater than 1.4 V ± 0.05 V. The high-to-low transition of the RESET pulse is the active edge of the pulse and therefore the user is afforded the option of holding RESET high during power–up.
AD9549 POWER SUPPLY PARTITIONING The AD9549 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the consumption of each power block varies with frequency. 1.8 V SUPPLIES DVDD (Pin 3, Pin 5, Pin 7) The recommendations here are for typical applications, and for these applications, there are four groups of power supplies: 3.3 V digital, 3.3 V analog, 1.8 V digital, and 1.8 V analog.
AD9549 SERIAL CONTROL PORT The AD9549 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9549 serial control port can be configured for a single bidirectional I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/SDO).
AD9549 Read If the instruction word is for a read operation (I15 = 1), the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1, 2, 3, 4, as determined by [W1:W0]. In this case, 4 is used for streaming mode where four or more words are transferred per read. The data readback is valid on the falling edge of SCLK. The default mode of the AD9549 serial control port is bidirectional mode, and the data readback appears on the SDIO pin.
AD9549 Table 11. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 R/W I14 W1 I13 W0 I12 A12 I11 A11 I10 A10 I9 A9 I8 A8 I7 A7 I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 LSB I0 A0 I1 A1 CSB SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 REGISTER (N) DATA D6 D5 D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 06744-053 DON'T CARE Figure 53.
AD9549 tH tS CSB tCLK tHI SCLK tLO tDS SDIO BIT N BIT N + 1 Figure 58. Serial Control Port Timing—Write Table 12.
AD9549 I/O REGISTER MAP All address and bit locations that are left blank in Table 13 are unused. Accessing reserved registers should be avoided. In cases where some of the bits in register are reserved, the user can rely on the default value in the I/O register map and write the same value back to the reserved bits in that register. Table 13. Addr Bit 7 Bit 6 Type1 Name (Hex) Serial port configuration and part identification 0x0000 Serial SDO LSB first config.
AD9549 Addr (Hex) Type1 0x0108 M 0x0109 M 0x010A M 0x010B M 0x010C M 0x010D M 0x010E M 0x010F M 0x0110 M 0x0111 M 0x0112 0x0113 0x0114 0x0115 RO 0x0116 RO 0x0117 RO 0x0118 RO 0x0119 RO 0x011A RO 0x011B M 0x011C M 0x011D M 0x011E M 0x011F M 0x0120 M 0x0121 M 0x0122 M 0x0123 M 0x0124 M 0x0125 M 0x0126 M 0x0127 M 0x0128 M 0x0129 M 0x012A M 0x012B M 0x012C M 0x012D 0x012E 0x012F 0x0130 Free-run mode 0x01A0 0x01A1 0x01A2 0x01A3 0x01A4 0x01A5 Name Loop coefficients Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Alpha-0, Bit
AD9549 Addr (Hex) 0x01A6 0x01A7 0x01A8 0x01A9 0x01AA Type1 M M M M M 0x01AB M Name FTW0 (open-loop frequency tuning word) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 BIt 2 FTW0, Bits[47:0] LSB: Register 0x01A6 Bit 1 Bit 0 0x01AC M Phase and (open loop 0x01AD only) Reference selector/holdover 0x01C0 M Automatic control DDS phase word, Bits[15:0] Holdover mode Reserved 0x01C1 Enable line card mode Enable REF_AB Enable Holdover ref input holdover on/off override override FTW windowed average size, Bits[3:0
AD9549 Addr (Hex) 0x030E 0x030F 0x0310 0x0311 0x0312 0x0313 0x0314 0x0315 0x0316 0x0317 0x0318 Type1 RO RO RO RO RO RO M M M M M Name HFTW 0x0319 0x031A 0x031B 0x031C 0x031D M M M M M Frequency lock 0x031E 0x031F 0x0320 0x0321 0x0322 0x0323 0x0324 0x0325 0x0326 0x0327 0x0328 0x0329 0x032A 0x032B 0x032C 0x032D 0x032E 0x032F 0x0330 0x0331 0x0332 0x0333 0x0334 0x0335 M M M M M M M M M M M M M M M M M M M M M M M M Loss of reference Phase lock Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 BIt 2 Bit 1 Average or ins
AD9549 Addr Bit 7 (Hex) Type1 Name Calibration (user-accessible trim) 0x0400 K-divider 0x0401 0x0402 M CPFD gain 0x0403 M 0x0404 FPFD gain 0x0405 Reserved 0x0406 RO Part Part version version 0x0407 Reserved 0x0408 0x0409 M PFD offset 0x040A M 0x040B DAC full-scale 0x040C current Reserved Reserved Reference bias level 0x0410 Reserved Harmonic spur reduction 0x0500 M Spur A Bit 6 Bit 5 Bit 4 M M M M 0x0505 M 0x0506 0x0507 0x0508 0x0509 M M M M 1 BIt 2 Bit 1 Bit 0 K-divider, Bits[15:0] Part versi
AD9549 I/O REGISTER DESCRIPTIONS SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005) Register 0x0000—Serial Configuration Table 14. Bits [7:4] 3 2 Bit Name 1 LSB first 0 SDO active Long instruction Soft reset Description These bits are the mirror image of Bits[3:0]. Read-only. The AD9549 supports only long instructions. Resets register map, except for Register 0x0000.
AD9549 Register 0x0011—Reserved Register 0x0012—Reset (Autoclear) To reset the entire chip, the user can also use the (nonself-clearing) soft reset bit in Register 0x0000. Except for IRQ reset, the user normally would not need to use this bit. However, if the user attempts to lock the loop for the first time when no signal is present, the user should write 1 to Bits[4:0] of this register before attempting to lock the loop again. Table 18.
AD9549 Register 0x0023—PFD Divider Table 22. Bits [3:0] Bit Name PFD divider Description Divide ratio for PFD clock from system clock. This is typically varied only in cases where the designer wishes to run the DPLL phase detector fast while SYSCLK is run relatively slowly. The ratio is equal to PFD divider × 4. For a 1 GHz system clock, the ADC runs at 1 GHz/20 = 50 MHz, and the DPLL phase detector runs at half this speed, which, in this case, is 25 MHz.
AD9549 Register 0x0104—S-Divider (DPLL Feedback Divider) Table 27. Bits [7:0] Bit Name S-divider Description Feedback divider. Divide ratio = 1 − 65,536. If the desired feedback ratio is greater than 65,536, or if the feedback signal on FDBK_IN is greater than 400 MHz, then Bit 0 of Register 0x0106 must be set. Note that the actual S-divider is the value in this register plus 1, so to have an R-divider of 1, Register 0x0104 and Register 0x0105 must both be 0x00.
AD9549 Register 0x010A—Loop Coefficients (Continued) Table 33. Bits [4:0] Bit Name Alpha-1 Description Power-of-2 multiplier for alpha coefficient. Register 0x010B—Loop Coefficients (Continued) Table 34. Bits [2:0] Bit Name Alpha-2 Description Power-of-2 divider for alpha coefficient. Register 0x010C—Loop Coefficients (Continued) Table 35. Bits [7:0] Bit Name Beta-0 Description Linear coefficient for beta coefficient. Register 0x010D—Loop Coefficients (Continued) Table 36.
AD9549 Register 0x0115—FTW Estimate (Read Only) Table 41. Bit [7:0] Bit Name FTW estimate Description This frequency estimate is from the frequency estimator circuit and is informational only. It is useful for verifying the input reference frequency. See the Frequency Estimator section for a description. Register 0x0116—FTW Estimate (Read Only) (Continued) Table 42. Bit [15:8] Bit Name FTW estimate Description This frequency estimate is from the frequency estimator circuit and is informational only.
AD9549 Register 0x011B—FTW Lower Limit Table 47. Bits [7:0] Bit Name FTW lower limit Description Lowest DDS tuning word in closed-loop mode. This feature is recommended when a band-pass reconstruction filter is used. See the Output Frequency Range Control section. Register 0x011C—FTW Lower Limit (Continued) Table 48. Bits [15:8] Bit Name FTW lower limit Description Lowest DDS tuning word in closed-loop mode. This feature is recommended when a band-pass reconstruction filter is used.
AD9549 Register 0x0121—FTW Upper Limit Table 53. Bits [7:0] Bit Name FTW upper limit Description Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass reconstruction filter is used. See the Output Frequency Range Control section. Register 0x0122—FTW Upper Limit (Continued) Table 54. Bits [15:8] Bit Name FTW upper limit Description Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass reconstruction filter is used.
AD9549 FREE-RUN (SINGLE-TONE) MODE (REGISTER 0x01A0 TO REGISTER 0x01AD) Register 0x01A0 to Register 0x01A5—Reserved Register 0x01A6—FTW0 (Frequency Tuning Word) Table 60. Bit [7:0] Bit Name FTW0 Description FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0).
AD9549 Register 0x01AC to Register 0x01AD—Phase Table 66. Bits [7:0] Bit Name DDS phase word Description Allows user to vary the phase of the DDS output. See the Direct Digital Synthesizer section. Register 0x01AC is the least significant byte of the phase offset word (POW). Note that a momentary phase discontinuity may occur as the phase passes through 45° intervals. Active only when the loop is not closed. Register 0x01AD—Phase (Continued) Table 67.
AD9549 Register 0x01C3—Reference Validation Table 71. Bits [7:5] [4:0] Bit Name Reserved Validation timer Description Reserved. The value in this register sets the time required to validate a reference after an LOR or OOL event before the reference can be used as the DPLL reference. This circuit uses the digital loop filter clock (see Register 0x0107). Validation time = loop filter clock period × 2(Validation Timer [4:0] +1) − 1.
AD9549 MONITOR (REGISTER 0x0300 TO REGISTER 0x0335) Register 0x0300—Status This register contains the status of the chip. This register is read-only and live update. Table 74. Bits 7 6 Bit Name Reserved PFD frequency too high 5 PFD frequency too low 4 Frequency estimator done 3 Reference selected 2 1 Free run Phase lock detect 0 Frequency lock detect Description Reserved. This flag indicates that the frequency estimator failed and detected a PFD frequency that is too high.
AD9549 Register 0x0305—IRQ Mask (Continued) Table 77. Bits 4 3 2 1 0 Bit Name Frequency estimator done Phase unlock Phase lock Frequency unlock Frequency lock Description Trigger IRQ when the frequency estimator is done. Trigger IRQ on falling edge of phase lock signal. Trigger IRQ on rising edge of phase lock signal. Trigger IRQ on falling edge of frequency lock signal. Trigger IRQ on rising edge of frequency lock signal. Register 0x0306—IRQ Mask (Continued) Table 78.
AD9549 Register 0x030C—Control Table 81. Bits 7 6 5 4 [3:2] 1 0 Bit Name Enable REFA LOR Enable REFA OOL Enable REFB LOR Enable REFB OOL Reserved Enable phase lock detector Enable frequency lock detector Description The REFA LOR limits are set up in Registers 0x031E to Register 0x031F. The REFA OOL limits are set up in Register 0x0322 to Register 0x032B. The REFB LOR limits are set up in Register 0x0320 to Register 0x0321. The REFB OOL limits are set up in Register 0x032C to Register 0x0335. Reserved.
AD9549 Register 0x0314—Phase Lock Table 88. Bits [7:0] Bit Name Phase lock threshold Description See the Phase Lock Detection section. Register 0x0315—Phase Lock (Continued) Table 89. Bits [15:8] Bit Name Phase lock threshold Description See the Phase Lock Detection section. Register 0x0316—Phase Lock (Continued) Table 90. Bits [23:16] Bit Name Phase lock threshold Description See the Phase Lock Detection section. Register 0x0317—Phase Lock (Continued) Table 91.
AD9549 Register 0x031E—Loss of Reference Table 98. Bits [7:0] Bit Name REFA LOR divider Description See the Loss of Reference section. Register 0x031F—Loss of Reference (Continued) Table 99. Bits [15:8] Bit Name REFA LOR divider Description See the Loss of Reference section. Register 0x0320—Loss of Reference (Continued) Table 100. Bits [7:0] Bit Name REFB LOR divider Description See the Loss of Reference section. Register 0x0321—Loss of Reference (Continued) Table 101.
AD9549 Register 0x0328—Reference OOL (Continued) Table 108. Bits [7:0] Bit Name REFA OOL lower limit Description See the Reference Frequency Monitor section. Register 0x0329—Reference OOL (Continued) Table 109. Bits [15:8] Bit Name REFA OOL lower limit Description See the Reference Frequency Monitor section. Register 0x032A—Reference OOL (Continued) Table 110. Bits [23:16] Bit Name REFA OOL lower limit Description See the Reference Frequency Monitor section.
AD9549 Register 0x0332—Reference OOL (Continued) Table 118. Bits [7:0] Bit Name REFB OOL lower limit Description See the Reference Frequency Monitor section. Register 0x0333—Reference OOL (Continued) Table 119. Bits [15:8] Bit Name REFB OOL lower limit Description See the Reference Frequency Monitor section. Register 0x0334—Reference OOL (Continued) Table 120. Bits [23:16] Bit Name REFB OOL lower limit Description See the Reference Frequency Monitor section.
AD9549 Register 0x0406—Part Version Table 127. Bits [7:6] Bit Name Part version [5:0] Reserved Description 01b = AD9549, Revision A 00b = AD9549, Revision 0 N/A Register 0x0407 to Register 0x0408—Reserved Register 0x0409—PFD Offset Table 128. Bits [7:0] Bit Name DPLL phase offset Description This register controls the static time offset of the PFD (phase frequency detector) in closed-loop mode. It has no effect when the DPLL is open. Register 0x040A—PFD Offset (Continued) Table 129.
AD9549 Register 0x0500—Spur A Table 133. Bits 7 6 [5:4] [3:0] Bit Name HSR-A enable Amplitude gain × 2 Reserved Spur A harmonic Description Harmonic Spur Reduction A enable. Reserved. Spur A Harmonic 1 to Spur A Harmonic 15. Register 0x0501—Spur A (Continued) Table 134. Bits [7:0] Bit Name Spur A magnitude Description Linear multiplier for Spur A magnitude. Register 0x0503—Spur A (Continued) Table 135. Bits [7:0] Bit Name Spur A phase Description Linear offset for Spur A phase.
AD9549 APPLICATIONS INFORMATION SAMPLE APPLICATIONS CIRCUIT DIFF HSTL OUTPUT AD9514 LVPECL CMOS OUTPUT INPUT A INPUT B OUT0/ OUT0B /1...../32 FDBK_IN FDBK_INB REF A LVPECL CLK DDS/ DAC LOW-PASS FILTER OUT1/ OUT1B /1...../32 CLKB REF B LDDS/CMOS AD9549 /1...../32 SYNCB OUT2/ OUT2B 06744-059 SYSCLK Δt Figure 59.
AD9549 OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 MAX 0.60 MAX 48 64 49 1 PIN 1 INDICATOR PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 MIN 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 062209-A SEATING PLANE 16 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.85 0.80 5.36 5.
AD9549 NOTES Rev.
AD9549 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06744-0-12/10(D) Rev.