Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs AD9524 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.
AD9524 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .................................................................................... 18 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 19 Functional Block Diagram ..........................................
Data Sheet AD9524 REVISION HISTORY 2/13—Rev. C to Rev. D Deleted VDD1.8_PLL2................................................. Throughout Changes to Data Sheet Title ............................................................ 1 Added TJ of 115°C, Table 1 .............................................................. 4 Changed VDD3_PLL1, Supply Voltage for PLL1 Typical Parameter from 22 mA to 37 mA and Changed VDD3_PLL1, Supply Voltage for PLL1 Maximum Parameter from 25.2 mA to 43 mA, Table 2 .............
AD9524 Data Sheet SPECIFICATIONS fVCXO = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, fVCO = 3932.16 MHz, doubler is off, channel control low power mode off, divider phase =1, unless otherwise noted. Typical is given for VDD = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD and TA (−40°C to +85°C) variation, as listed in Table 1. CONDITIONS Table 1.
Data Sheet Parameter CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON LVDS Mode, 7 mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers LVDS Mode, 3.
AD9524 Data Sheet POWER DISSIPATION Table 3. Parameter POWER DISSIPATION Typical Configuration Min PD, Power-Down INCREMENTAL POWER DISSIPATION Low Power Typical Configuration Switched to One Input, Reference Single-Ended Mode Switched to Two Inputs, Reference Differential Mode Switched to Two Inputs, Reference Single-Ended Mode Output Distribution, Driver On LVDS LVPECL Compatible HSTL CMOS Typ Max Unit Test Conditions/Comments 559 593 mW 101 132.
Data Sheet AD9524 Parameter Input Capacitance Duty Cycle Pulse Width Low Pulse Width High Min Typ 1 Max Unit pF Test Conditions/Comments Duty cycle bounds are set by pulse width high and pulse width low 1.6 1.6 ns ns OSC_CTRL OUTPUT CHARACTERISTICS Table 5. Parameter OUTPUT VOLTAGE High Low Min Typ Max Unit Test Conditions/Comments V mV RLOAD > 20 kΩ 150 Max Unit Test Conditions/Comments 250 MHz V V VDD3_PLL1 − 0.15 REF_TEST INPUT CHARACTERISTICS Table 6.
AD9524 Data Sheet DISTRIBUTION OUTPUT CHARACTERISTICS (OUT0, OUT0 TO OUT5, OUT5) Duty cycle performance is specified with the invert divider bit set to 1, and the divider phase bits set to 0.5. (For example, for Channel 0, 0x196[7] = 1 and 0x198[7:2] = 000001.) Output Voltage Reference VDD in Table 9 refers to the 3.3 V supply VDD3_OUT[x:y] supply. Table 9.
Data Sheet AD9524 TIMING ALIGNMENT CHARACTERISTICS Table 10.
AD9524 Data Sheet LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL Table 13. Parameter VOLTAGE Input High Input Low INPUT LOW CURRENT CAPACITANCE RESET TIMING Pulse Width Low Inactive to Start of Register Programming SYNC TIMING Pulse Width Low Min Typ Max Unit ±80 0.8 ±250 V V µA 2.0 3 Test Conditions/Comments The minus sign indicates that, due to the internal pull-up resistor, current is flowing out of the AD9524 pF 50 100 ns ns 1.
Data Sheet Parameter SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High, tHIGH Pulse Width Low, tLOW SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CS to SCLK Setup, tS CS to SCLK Setup and Hold, tS, tC CS Minimum Pulse Width High, tPWH AD9524 Min Typ Max Unit 0.4 V V 2.7 25 8 12 3.
AD9524 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 17. Parameter VDD3_PLL1, VDD3_PLL2, VDD3_REF, VDD3_OUT, LDO_VCO to GND REFA, REFA, REFIN, REFB, REFB to GND SCLK/SCL, SDIO/SDA, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, to GND SYNC, RESET, PD to GND STATUS0, STATUS1 to GND SP0, SP1, EEPROM_SEL to GND VDD1.8_OUT, LDO_PLL1, LDO_PLL2 to GND Storage Temperature Range Lead Temperature (10 sec) THERMAL RESISTANCE Rating −0.3 V to +3.
Data Sheet AD9524 48 47 46 45 44 43 42 41 40 39 38 37 VDD3_PLL1 LDO_PLL1 PLL1_OUT REF_SEL ZD_IN ZD_IN NC OUT0 OUT0 VDD3_OUT[0:1] OUT1 OUT1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9524 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 STATUS0/SP0 STATUS1/SP1 VDD1.8_OUT[0:3] OUT2 OUT2 VDD3_OUT[2:3] OUT3 OUT3 EEPROM_SEL PD RESET REF_TEST NOTES 1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND.
AD9524 Data Sheet Pin No. 17 18 Mnemonic SDIO/SDA SDO Type 1 I/O O 19 OUT5 O 20 OUT5 O 21 22 VDD3_OUT[4:5] OUT4 P O 23 OUT4 O 24 25 26 VDD1.8_OUT[4:5] REF_TEST RESET P I I 27 PD 28 EEPROM_SEL I 29 OUT3 O 30 OUT3 O 31 32 VDD3_OUT[2:3] OUT2 P O 33 OUT2 O 34 35 36 37 VDD1.
Data Sheet AD9524 TYPICAL PERFORMANCE CHARACTERISTICS fVCXO = 122.88 MHz, REFA differential at 30.72 MHz, fVCO = 3686.4 MHz, and doubler is off, unless otherwise noted. 60 35 50 30 20pF 25 40 CURRENT (mA) CURRENT (mA) HSTL = 16mA 30 HSTL = 8mA 20 10pF 20 2pF 15 10 10 5 0 400 600 800 1000 1200 FREQUENCY (MHz) 0 500 Figure 6. VDD3_OUT[x:y] Current (Typical) vs. Frequency; CMOS Mode, 20 pF, 10 pF, and 2 pF Load 3.5 45 40 DIFFERENTIAL SWING (V p-p) 3.
AD9524 Data Sheet 1.4 –70 LVDS = 7mA –90 0.8 LVDS = 3.5mA 0.6 0.4 1 –100 –110 –120 –130 3 5 –140 NOISE: ANALYSIS RANGE X: BAND MARKER ANALYSIS RANGE Y: BAND MARKER INTG NOISE: –75.94595dBc/39.99MHz RMS NOISE: 225.539µRAD 12.9224mdeg RMS JITTER: 194.746fsec RESIDUAL FM: 2.81623kHz –150 0.2 –160 0 200 400 1000 800 600 –170 100 09081-009 0 1200 FREQUENCY (MHz) 1k 10k 7 100k 1M 10M FREQUENCY (Hz) Figure 9. Differential Voltage Swing vs. Frequency; LVDS Mode, 7 mA and 3.
Data Sheet AD9524 INPUT/OUTPUT TERMINATION RECOMMENDATIONS 100Ω HIGH IMPEDANCE DOWNSTREAM DEVICE INPUT HSTL OUTPUT 0.1µF 100Ω HIGH IMPEDANCE DOWNSTREAM DEVICE INPUT 0.1µF Figure 15. AC-Coupled LVDS Output Driver Figure 19. AC-Coupled HSTL Output Driver AD9524 AD9524 100Ω HIGH IMPEDANCE DOWNSTREAM DEVICE INPUT HSTL OUTPUT 100Ω HIGH IMPEDANCE DOWNSTREAM DEVICE INPUT 09081-047 09081-143 LVDS OUTPUT 0.1µF 09081-046 LVDS OUTPUT AD9524 0.1µF 09081-142 AD9524 LVPECLCOMPATIBLE OUTPUT 0.
AD9524 Data Sheet TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.
Data Sheet AD9524 THEORY OF OPERATION DETAILED BLOCK DIAGRAM VCXO VDD3_PLL1 LDO_PLL1 LF1_EXT_CAP OSC_CTRL PLL1_OUT OSC_IN STATUS0/ STATUS1/ SP0 SP1 LF2_EXT_CAP LDO_VCO STATUS MONITOR LOCK DETECT/ SERIAL PORT ADDRESS REFA REFA SWITCHOVER CONTROL REF_SEL REFB REFB REF_TEST LOCK DETECT ÷R RESYNCH Δt EDGE OUT5 OUT5 ÷D Δt EDGE OUT4 OUT4 ÷D Δt EDGE OUT3 OUT3 ÷D Δt EDGE OUT2 OUT2 ÷D Δt EDGE OUT1 OUT1 ÷D Δt EDGE OUT0 OUT0 ÷D ÷D1 LOOP FILTER LOCK DETECT ÷R P F D SYNC SIGNAL VDD1
AD9524 Data Sheet COMPONENT BLOCKS—INPUT PLL (PLL1) PLL1 Loop Filter PLL1 General Description The PLL1 loop filter requires the connection of an external capacitor from LF1_EXT_CAP (Pin 5) to ground. The value of the external capacitor depends on the use of an external VCXO, as well as such configuration parameters as input clock rate and desired bandwidth. Normally, a 0.
Data Sheet AD9524 tristates. The device continues operating in this mode until a reference signal becomes available. Then the device exits holdover mode, and PLL1 resynchronizes with the active reference. In addition to tristate, the charge pump can be forced to VCC/2 during holdover (see Table 43, Bit 6 in Register 0x01C). PLL1 Input Dividers Each reference input feeds a dedicated reference divider block. The input dividers provide division of the reference frequency in integer steps from 1 to 1023.
AD9524 Data Sheet Input 2× Frequency Multiplier VCO Divider The 2× frequency multiplier provides the option to double the frequency at the PLL2 input. This allows the user to take advantage of a higher frequency at the input to the PLL (PFD) and, thus, allows for reduced in-band phase noise and greater separation between the frequency generated by the PLL and the modulation spur associated with PFD.
Data Sheet AD9524 CLOCK DISTRIBUTION The clock distribution block provides an integrated solution for generating multiple clock outputs based on frequency dividing the PLL2 VCO divider output. The distribution output consists of six channels (OUT0 to OUT5). Each of the output channels has a dedicated divider and output driver, as shown in Figure 25. The AD9524 also has the capability to route the VCXO output to two of the outputs (OUT0 and OUT1).
AD9524 Data Sheet Clock Distribution Synchronization As indicated, the primary synchronization signal originates from one of the following sources: A block diagram of the clock distribution synchronization functionality is shown in Figure 27. The synchronization sequence begins with the primary synchronization signal, which ultimately results in delivery of a synchronization strobe to the clock distribution logic.
Data Sheet AD9524 The synchronization event is the clearing operation (that is, the Logic 1 to Logic 0 transition of the bit). The dividers are all automatically synchronized to each other when PLL2 is ready. The dividers support programmable phase offsets from 0 to 63 steps, in half periods of the input clock (for example, the VCO divider output clock). The phase offsets are incorporated in the dividers through a preset for the first output clock period of each divider.
AD9524 Data Sheet RESET MODES The AD9524 has a power-on reset (POR) and several other ways to apply a reset condition to the chip. Power-On Reset During chip power-up, a power-on reset pulse is issued when 3.3 V supply reaches ~2.6 V (<2.8 V) and restores the chip either to the setting stored in EEPROM (EEPROM pin = 1) or to the on-chip setting (EEPROM pin = 0). At power-on, the AD9524 executes a SYNC operation, which brings the outputs into phase alignment according to the default settings.
Data Sheet AD9524 SERIAL CONTROL PORT SPI/I²C PORT SELECTION The AD9524 has two serial interfaces, SPI and I2C. Users can select either the SPI or I2C, depending on the states (logic high, logic low) of the two logic level input pins, SP1 and SP0, when power is applied or after a RESET (each pin has an internal 40 kΩ pulldown resistor). When both SP1 and SP0 are low, the SPI interface is active.
AD9524 Data Sheet MSB ACKNOWLEDGE FROM SLAVE-RECEIVER 1 SCL 2 3 TO 7 8 9 1 ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 8 9 S 10 P 09081-162 SDA Figure 32. Acknowledge Bit MSB = 0 1 SCL 2 3 TO 7 8 9 1 ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 8 9 S 10 P 09081-163 ACKNOWLEDGE FROM SLAVE-RECEIVER 10 P 09081-164 SDA Figure 33.
Data Sheet AD9524 Data Transfer Format Send byte format. The send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A RAM Address High Byte A RAM Address Low Byte A P A P A P A P Write byte format. The write byte protocol is used to write a register address to the RAM, starting from the specified RAM address. S Slave Address W A RAM Address High Byte A RAM Address Low Byte A RAM Data 0 RAM Data 1 A RAM Data 2 A Receive byte format.
AD9524 Data Sheet SPI SERIAL PORT OPERATION First Transfers section). CS must be raised at the end of the last byte to be transferred, thereby ending streaming mode. Pin Descriptions SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 40 kΩ resistor to ground.
Data Sheet AD9524 Bit 3. This makes it irrelevant whether LSB first or MSB first is in effect. The default for the AD9524 is MSB first. The default mode of the AD9524 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin. It is also possible to set the AD9524 to unidirectional mode. In unidirectional mode, the readback data appears on the SDO pin.
AD9524 Data Sheet tHIGH tDH SCLK DON'T CARE SDIO DON'T CARE R/W W1 tC tSCLK tLOW CS W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 HIGH-IMEPDANCE 09081-138 tDS tS Figure 38.
Data Sheet AD9524 tS tC CS tCLK tHIGH tLOW tDS SCLK SDIO BIT N BIT N + 1 09081-043 tDH Figure 44. Serial Control Port Timing—Write Table 28.
AD9524 Data Sheet EEPROM OPERATIONS The AD9524 contains an internal EEPROM (nonvolatile memory). The EEPROM can be programmed by the user to create and store a user defined register setting file when the power is off. This setting file can be used for power-up and chip reset as a default setting. The EEPROM size is 512 bytes. Descriptions of the EEPROM registers that control EEPROM operation can be found in Table 58 and Table 59. 4. 5.
Data Sheet AD9524 To ensure that the data transfer has completed correctly, verify that the EEPROM data error bit (Bit 0 in Register 0xB01) is set to 0. A value of 1 in this bit indicates a data transfer error. The next two bytes are the high byte and low byte of the memory address (16 bits) of the first register in this group.
AD9524 Data Sheet Table 29.
Data Sheet AD9524 POWER DISSIPATION AND THERMAL CONSIDERATIONS The AD9524 is a multifunctional, high speed device that targets a wide variety of clock applications. The numerous innovative features contained in the device each consume incremental power. If all outputs are enabled in the maximum frequency and mode that have the highest power, the safe thermal operating conditions of the device may be exceeded.
AD9524 Data Sheet The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient. For this example, a thermal impedance of θJA = 20.1°C/W was used. THERMALLY ENHANCED PACKAGE MOUNTING GUIDELINES Refer to the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), for more information about mounting devices with an exposed paddle. Example 1 (703 mW × 20.1°C/W) = 14.
Data Sheet AD9524 CONTROL REGISTERS CONTROL REGISTER MAP Register addresses that are not listed in Table 31 are not used, and writing to those registers has no effect. Registers that are marked as reserved should never have their values changed. When writing to registers with bits that are marked reserved, the user should take care to always write the default value for the reserved bits. Table 31.
AD9524 Addr (Hex) 0x01D Register Name PLL1 loop filter zero resistor control Output PLL (PLL2) PLL2 charge 0x0F0 pump control PLL2 0x0F1 feedback N divider control 0x0F2 PLL2 control Data Sheet (MSB) Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved A counter PLL2 lock detector powerdown Reserved Reserved Enable frequency doubler Reserved Reserved Enable SPI control of antibacklash pulse width Force release of distribution sync when PLL2 is unlocked Reserved 0x0F4 VCO divider control
Data Sheet AD9524 Addr (Hex) 0x1BA Register Name PLL1 output control (MSB) Bit 7 Reserved 0x1BB PLL1 output channel control Readback 0x22C Readback 0 0x22D Other 0x230 0x231 0x232 0x233 Readback 1 Status signals Power-down control Update all registers EEPROM Buffer EEPROM 0xA00 Buffer Segment Register 1 to 0xA01 EEPROM Buffer Segment 0xA02 Register 3 EEPROM 0xA03 Buffer Segment Register 4 to 0xA04 EEPROM Buffer Segment 0xA05 Register 6 EEPROM 0xA06 Buffer Segment Register 7 to 0xA07 EEPROM Buf
AD9524 Addr (Hex) 0xA0C Register Name EEPROM Buffer Segment 0xA0D Register 13 to EEPROM Buffer Segment 0xA0E Register 15 EEPROM 0xA0F Buffer Segment Register 16 to 0xA10 EEPROM Buffer Segment 0xA11 Register 18 EEPROM 0xA12 Buffer Segment Register 19 to 0xA13 EEPROM Buffer Segment 0xA14 Register 21 EEPROM 0xA15 Buffer Segment Register 22 EEPROM 0xA16 Buffer Segment Register 23 EEPROM Control Status_ 0xB00 EEPROM (read only) EEPROM error 0xB01 checking readback (read only) EEPROM 0xB02 Control 1 EEPROM 0xB03
Data Sheet AD9524 CONTROL REGISTER MAP BIT DESCRIPTIONS Serial Port Configuration (Address 0x000 to Address 0x006) Table 32. SPI Mode Serial Port Configuration Address 0x000 0x004 Bits 7 Bit Name SDO active 6 LSB first/ address increment 5 Soft reset 4 [3:0] Reserved Mirror[7:4] 0 Read back active registers Description Selects unidirectional or bidirectional data transfer mode. This bit is ignored in I2C mode. 0: SDIO pin used for write and read; SDO is high impedance (default).
AD9524 Data Sheet Input PLL (PLL1) (Address 0x010 to Address 0x01D) Table 35. PLL1 REFA R Divider Control Address 0x010 0x011 Bits [7:0] Bit Name REFA R divider [1:0] Description 10-bit REFA R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023. 00000000, 00000001: divide-by-1. 10-bit REFA R divider, Bits[9:8] (MSB) Table 36. PLL1 REFB R Divider Control 1 Address 0x012 0x013 1 Bits [7:0] Bit Name REFB R divider [1:0] Description 10-bit REFB R divider, Bits[7:0] (LSB).
Data Sheet AD9524 Table 41. PLL1 Input Receiver Control Address 0x01A Bits 7 Bit Name REF_TEST input receiver enable 6 REFB differential receiver enable 5 REFA differential receiver enable 4 REFB receiver enable 3 REFA receiver enable 2 Input REFA and REFB receiver power-down control enable 1 OSC_IN single-ended receiver mode enable (CMOS mode) 0 OSC_IN differential receiver mode enable Description 1: enabled. 0: disabled (default). 1: differential receiver mode.
AD9524 Data Sheet Table 43. PLL1 Miscellaneous Control Address 0x01C 1 Bits 7 Bit Name Enable REFB R divider independent division control 6 OSC_CTRL control voltage to VCC/2 when reference clock fails 5 [4:2] Reserved Reference selection mode [1:0] Reserved Description 1: REFB R divider is controlled by Register 0x012 and Register 0x013. 0: REFB R divider is set to the same setting as the REFA R divider (Register 0x010 and Register 0x011).
Data Sheet AD9524 Output PLL (PLL2) (Address 0x0F0 to Address 0x0F9) Table 45. PLL2 Charge Pump Control Address 0x0F0 Bits [7:0] Bit Name PLL2 charge pump control Description These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 μA with a full-scale magnitude of ~900 μA. Table 46.
AD9524 Data Sheet Table 48. VCO Control Address 0x0F3 Bits [7:5] 4 Bit Name Reserved Force release of distribution sync when PLL2 is unlocked 3 2 Reserved Force VCO to midpoint frequency 1 Calibrate VCO (not autoclearing) 0 Reserved Description Reserved. 0 (default): distribution is held in sync (static) until the output PLL locks. Then it is automatically released from sync with all dividers synchronized. 1: overrides the PLL2 lock detector state; forces release of the distribution from sync.
Data Sheet AD9524 Table 50.
AD9524 Data Sheet Clock Distribution (Address 0x196 to Address 0x1A1, Address 0x1AE to Address 0x1B3, Address 0x1BA, and Address 0x1BB) Table 51. Channel 0 to Channel 5 Control (This same map applies to all six channels.) Address 0x196 0x197 Bits 7 6 Bit Name Invert divider output Ignore sync 5 Power-down channel 4 Lower power mode (differential modes only) [3:0] Driver mode [7:0] Channel divider, Bits[7:0] (LSB) Description Inverts the polarity of the divider’s output clock.
Data Sheet Address 0x198 AD9524 Bits [7:2] Bit Name Divider phase [1:0] Channel divider, Bits[9:8] (MSB) Description Divider initial phase after a sync is asserted relative to the divider input clock (from the VCO divider output). LSB = ½ of a period of the divider input clock. Phase = 0: no phase offset. Phase = 1: ½ period offset, … Phase = 63: 31 period offset. 10-bit channel divider, Bits[9:8] (MSB). Table 52.
AD9524 Address 0x22D Data Sheet Bits [7:4] 3 Bit Name Reserved Holdover active 2 Selected reference (in auto mode) 1 0 Reserved VCO calibration in progress Description Reserved 1: holdover is active (both references are missing) 0: normal operation Selected reference (applies only when the device automatically selects the reference; for example, not in manual control mode) 1: REFB 0: REFA Reserved 1: VCO calibration in progress 0: VCO calibration not in progress Other (Address 0x230 to Address 0x23
Data Sheet AD9524 Address 0x231 Bits [7:6] [5:0] Bit Name Reserved Status Monitor 1 control 0x232 [7:5] 4 Reserved Enable Status_EEPROM on STATUS0 pin STATUS1 pin divider enable 3 2 STATUS0 pin divider enable 1 0 Reserved Sync dividers (manual control) Description Reserved.
AD9524 Data Sheet Table 56. Power-Down Control Address 0x233 Bits [7:3] 2 Bit Name Reserved PLL1 power-down 1 PLL2 power-down 0 Distribution powerdown Description Reserved. 1: power-down (default). 0: normal operation. 1: power-down (default). 0: normal operation. Powers down the distribution. 1: power-down (default). 0: normal operation. Table 57. Update All Registers Address 0x234 Bits [7:1] 0 Bit Name Reserved IO_Update Description Reserved.
Data Sheet AD9524 Table 61. EEPROM Control 1 Address 0xB02 Bits [7:2] 1 Bit Name Reserved Soft_EEPROM 0 Enable EEPROM write Description Reserved. When the EEPROM_SEL pin is tied low, setting the Soft_EEPROM bit resets the AD9524 using the settings saved in EEPROM. 1: soft reset with EEPROM settings (self-clearing). Enables the user to write to the EEPROM. 0: EEPROM write protection is enabled. User cannot write to EEPROM (default). 1: EEPROM write protection is disabled. User can write to EEPROM.
AD9524 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 48 1 36 PIN 1 INDICATOR 6.85 6.75 SQ 6.65 0.50 REF 5.25 5.10 SQ 4.95 EXPOSED PAD 25 0.50 0.40 0.30 TOP VIEW 1.00 0.85 0.80 12 13 24 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 12° MAX 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.