Datasheet

ManualsBrandsANALOG DEVICES ManualsLogic ICsLogic IC - Switch Crosspoint switch Dual supply LQFP 184 (20x20)

33 × 17, 3.2 Gbps

Digital Crosspoint Switch

AD8151

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Low cost

33 × 17, fully differential, nonblocking array

3.2 Gbps per port NRZ data rate

Wide power supply range: +3.3 V, –3.3 V

Low power

425 mA (outputs enabled)

35 mA (outputs disabled)

LV PECL- and LV ECL-compatible

CMOS/TTL-level control inputs: 3 V to 5 V

Low jitter

No heat sinks required

Drives a backplane directly

Programmable output current

Optimize termination impedance

User-controlled voltage at the load

Minimize power dissipation

Individual output disable for busing and reducing power

Double row latch

Buffered inputs

184-lead LQFP package

APPLICATIONS

High speed serial backplane routing to Sonet OC-48

applications with FEC

Fiber optic network switching

Fiber channel

LVDS

FUNCTIONAL BLOCK DIAGRAM

OUTP

OUTN

INP INN

UPDATE

RESET

FIRST

RANK

7-BIT

LATCH

SECOND

RANK

7-BIT

LATCH

INPUT

DECODERS

OUTPUT

ADDRESS

DECODER

DIFFERENTIAL

SWITCH

MATRIX

33 33

AD8151

02169-001

Figure 1.

GENERAL DESCRIPTION

The AD8151

is a member of the Xstream line of products,

offering a breakthrough in digital switching and a large switch

array (33 × 17) on very little power—typically less than 1.5 W.

It also operates at data rates in excess of 3.2 Gbps per port,

making it suitable for Sonet OC-48 applications with

8/10-bit forward-error correction (FEC). Furthermore, the

price of the AD8151 makes it affordable enough to be used for

lower data rates. The AD8151’s flexible supply voltages allow

the user to operate with either emitter-coupled logic (ECL) or

positive emitter-coupled logic (PECL) data levels, and with 3.3

V for further power reduction. The control interface is CMOS-

/TTL-compatible (3 V to 5 V).

Its fully differential signal path reduces jitter and crosstalk,

while allowing the use of smaller, single-ended voltage swings.

The AD8151 is offered in a 184-lead LQFP package that

operates over the extended commercial temperature range

of 0°C to 85°C.

02169-002

70ps/DIV

150mV/DIV

Figure 2. Eye Pattern, 3.2 Gbps, PRBS 23

Patent pending.

Summary of content (40 pages)

PAGE 1
33 × 17, 3.2 Gbps Digital Crosspoint Switch AD8151 FEATURES APPLICATIONS Low cost 33 × 17, fully differential, nonblocking array 3.2 Gbps per port NRZ data rate Wide power supply range: +3.3 V, –3.
PAGE 2
AD8151 TABLE OF CONTENTS Features .............................................................................................. 1 Control Interface ............................................................................ 17 Applications....................................................................................... 1 Control Pin Description............................................................ 17 Functional Block Diagram ..............................................................
PAGE 3
AD8151 SPECIFICATIONS @ 25°C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 Ω (see Figure 26), IOUT = 16 mA, unless otherwise noted. Table 1.
PAGE 4
AD8151 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. MAXIMUM POWER DISSIPATION Table 2. The maximum power that can be safely dissipated by the AD8151 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C.
PAGE 5
AD8151 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 180 181 182 179 138 PIN 1 INDICATOR 2 137 3 136 4 135 5 134 6 133 7 132 8 131 9 130 10 129 11 128 12 127 13 126 14 125 15 124 16 123 17 122 18 121 19 120 20 119 21 AD8151 118 22 184L LQFP TOP VIEW (Not to Scale) 117 23 24 116 115 92 91 90 89 88 87
PAGE 6
AD8151 Table 3. Pin Function Descriptions Pin No.
PAGE 7
AD8151 Pin No.
PAGE 8
AD8151 Pin No.
PAGE 9
AD8151 02169-008 02169-005 150mV/DIV 150mV/DIV TYPICAL PERFORMANCE CHARACTERISTICS 100ps/DIV 70ps/DIV Figure 5. Eye Pattern 2.5 Gbps, PRBS 23 Figure 8. Eye Pattern 3.2 Gbps, PRBS 23 p-p = 43ps STD DEV = 8ps 02169-009 02169-006 150mV/DIV 150mV/DIV p-p = 53ps STD DEV = 8ps 20ps/DIV 20ps/DIV Figure 9. Jitter @ 3.2 Gbps, PRBS 23 100 90 90 80 80 70 70 60 50 (CLOCK PERIOD – JITTER p-p) % EYE WIDTH = × 100 CLOCK PERIOD 40 60 50 30 20 20 0 0.5 1.0 1.5 2.0 2.5 DATA RATE (Gbps) 3.
PAGE 10
AD8151 100 90 90 80 80 70 70 60 50 JITTER (ps) JITTER (ps) 100 PEAK-PEAK JITTER 40 60 3.2Gbps JITTER 50 40 30 30 20 20 2.5Gbps JITTER 1.5 2.0 2.5 DATA RATE (Gbps) 3.0 02169-014 STANDARD DEVIATION 0 1.0 3.2Gbps STD DEV 02169-011 10 10 2.5Gbps STD DEV 0 3.5 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 90 Figure 14. Jitter vs. Temperature, PRBS 23 Figure 11. Jitter vs. Data Rate, PRBS 23 p-p = 32ps STD DEV = 4.
PAGE 11
AD8151 p-p = 43ps STD DEV = 8ps 02169-020 02169-017 150mV/DIV 150mV/DIV p-p = 43ps STD DEV = 8ps 1.4ns/DIV 1.1ns/DIV Figure 20. Response, 3.2 Gbps, 32-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011 100 100 90 90 80 80 PEAK-TO-PEAK JITTER (ps) 70 60 2.5Gbps JITTER 50 40 30 3.2Gbps JITTER 60 50 2.5Gbps 40 30 20 02169-018 20 10 0 0.2 3.2Gbps 70 0.3 0.4 0.5 0.6 0.7 INPUT AMPLITUDE (V) 0.8 0.9 02169-021 PEAK-TO-PEAK JITTER (ps) Figure 17. Response, 2.
PAGE 12
AD8151 200 100 90 150 PROPAGATION DELAY (ps) 80 FREQUENCY 70 60 50 40 30 100 50 0 –50 –100 10 0 550 570 590 610 630 650 670 690 PROPAGATION DELAY (ps) 710 730 Figure 23. Variation in Channel-to-Channel Delay, All 561 Points –150 –200 –100 02169-025 02169-023 20 –80 –60 –40 –20 0 20 40 60 NORMALIZED TEMPERATURE (°C) PRBS GENERATOR DATA OUT 1.65kΩ 49.9Ω AD8151 P –6dB VTT 50Ω 105Ω 2.5Gbps 60 DATA OUT HIGH SPEED SAMPLING OSCILLOSCOPE P 70 –6dB IN OUT N N 50Ω 50 3.2Gbps 49.
PAGE 13
AD8151 CONTROL INTERFACE TRUTH TABLES Table 4. Basic Control Functions RESET Control Pins1 CS WE RE UPDATE Function 0 1 X 1 X X X X X X 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 0 0 1 0 Global Reset. Reset all second rank enable bits to zero (disable all outputs). Control Disable. Ignore all logic (but the signal matrix still functions as programmed). D [6:0] are high impedance. Single Output Preprogram.
PAGE 14
AD8151 CONTROL INTERFACE TIMING DIAGRAMS CS INPUTS WE INPUTS A[4:0] INPUTS D[6:0] INPUTS tCSW tCHW tASW tAHW tWP 02169-027 tDSW tDHW Figure 27. First Rank Write Cycle Table 6.
PAGE 15
AD8151 CS INPUTS UPDATE INPUTS WE INPUTS ENABLING OUT[0:16][N:P] OUTPUTS INPUT {DATA 1} INPUT {DATA 0} INPUT {DATA 1} tCSU tCHU tUW tUOT tWOT tUOE tWHU tWOD 02169-029 DISABLING OUT[0:16][N:P] OUTPUTS INPUT {DATA 2} Figure 29. First Rank Write Cycle and Second Rank Update Cycle Table 8.
PAGE 16
AD8151 RESET INPUTS DISABLING OUT[0:16][N:P] OUTPUTS 02169-031 tTOD tTW Figure 31. Asynchronous Reset Table 10. Asynchronous Reset Parameter Disable Time Width of Reset Pulse Mnemonic tTOD tTW Function Output disable from reset Conditions TA = 25°C VDD = 5 V VCC = 3.3 V Min Typ 25 Max 30 15 Unit ns ns CONTROL INTERFACE PROGRAMMING EXAMPLE The following conservative pattern connects all outputs to Input 7, except Output 16, which is connected to Input 32. The vector clock period t0 is 15 ns.
PAGE 17
AD8151 CONTROL INTERFACE 7 UPDATE RESET D[0:6] 7 7 7 7 7 7 7 7 0 0 1 1 2 2 16 16 RANK 1 RANK 2 7 TO 17 × 33 SWITCH MATRIX 33 7 7 7 33 7 7 33 7 7 33 17 ROWS OF 7-BIT LATCHES 1 OF 33 DECODERS To facilitate multiple chip address decoding, there is a chipselect pin. All logic signals except the reset pulse are ignored unless the chip select pin is active. The chip select pin disables only the control logic interface and does not change the operation of the signal matrix.
PAGE 18
AD8151 RE Input Second Rank Read-Enable. Forcing this pin to logic low enables the output drivers on the bidirectional D pins [6:0], entering the readback mode of operation. By selecting an output address with the A pins [4:0] and forcing RE to logic low, the 7-bit data stored in the second rank latch for that output address is written to the D pins [6:0]. Data should not be written to the D pins [6:0] externally while in readback mode.
PAGE 19
AD8151 CIRCUIT DESCRIPTION High Speed Data Inputs (INxxP, INxxN) The AD8151 has 33 pairs of differential voltage-mode inputs. The common-mode input range extends from the positive supply voltage (VCC) down to include standard ECL or PECL input levels (VCC – 2 V). The minimum differential input voltage is 200 mV. Unused inputs may be connected directly to any level within the allowed common-mode input range. A simplified schematic of the input circuit is shown in Figure 33.
PAGE 20
AD8151 To ensure proper operation, all outputs (including unused output) must be pulled high using external pull-up networks to a level within the output compliance range. If outputs from multiple AD8151s are wired together, a single pull-up network can be used for each output bus. The pull-up network should be chosen to keep the output voltage levels within the output compliance range at all times. Recommended pull-up networks to produce PECL/ECL 100 kΩ and 10 kΩ compatible outputs are shown in Figure 36.
PAGE 21
AD8151 Data Path Supplies POWER DISSIPATION The data path supplies have more options for their voltage levels. The choices here affect several other areas, such as power dissipation, bypassing, and common-mode levels of the inputs and outputs. The more positive voltage supply for the data paths is VCC (Pin 41, Pin 98, Pin 149, and Pin 171). The more negative supply is VEE, which appears on many pins that are not listed here. The maximum allowable voltage across these supplies is 5.5 V.
PAGE 22
AD8151 Thus, the power dissipation of the high output can be ignored and the output power dissipation for each output can be assumed to occur in a single static low output that sinks the full output programmed current. The voltage across which this current flows can also vary, depending on the output circuit design and the supplies that are used for the data path circuitry. In general, however, there is a voltage difference between a logic low signal and VEE.
PAGE 23
AD8151 APPLICATIONS INPUT AND OUTPUT BUSING Although the AD8151 is a digital part, in any application that runs at high speed, analog design details have to be given very careful consideration. At high data rates, the design of the signal channels have a strong influence on data integrity and its associated jitter and ultimately bit error rate (BER).
PAGE 24
AD8151 POWER SUPPLIES The AD8151 is designed to work with standard ECL logic levels. This means that VCC is at ground and VEE is at a negative supply. The shells of the I/O SMA connectors are at VCC potential. Thus, when operating in the standard ECL configuration, test equipment can be directly connected to the board, since the test equipment also has its connector shells at ground potential. Operating in PECL mode requires VCC to be at a positive voltage while VEE is at ground.
PAGE 25
AD8151 CONFIGURATION PROGRAMMING The board is configurable by one of two methods. For ease of use, custom software is provided that controls the AD8151 programming via the parallel port of a PC. This requires a standard printer cable that has a DB-25 connector at one end (parallel-port or printer-port interface) and a Centronix connector at the other, which connects to P2 of the AD8151 evaluation board. The programming with this setup is serial, so it is not the fastest way to configure the AD8151 matrix.
PAGE 26
AD8151 SOFTWARE OPERATION Click any button in the matrix to program the input to output connection. This sends the proper programming sequence out the PC parallel port. Since only one input can be programmed to a given output at one time, clicking a button in a horizontal row cancels the other selection that is already selected in that row. However, any number of outputs can share the same input. A shortcut for programming all outputs to the same input is to use the broadcast feature.
PAGE 27
02169-043 AD8151 Figure 43. Component Side Rev.
PAGE 28
02169-044 AD8151 Figure 44. Circuit Side Rev.
PAGE 29
02169-045 AD8151 Figure 45. Silkscreen Top Rev.
PAGE 30
02169-046 AD8151 Figure 46. Solder Mask Top Rev.
PAGE 31
02169-047 AD8151 Figure 47. Silkscreen Bottom Rev.
PAGE 32
02169-048 AD8151 Figure 48. Solder Mask Bottom Rev.
PAGE 33
02169-049 AD8151 Figure 49. INT1 (VEE) Rev.
PAGE 34
02169-050 AD8151 Figure 50. INT2 (VCC) Rev.
PAGE 35
VEE 139 IN13N IN13P 132 8 131 9 130 10 129 11 128 12 127 13 126 14 125 15 124 16 123 17 122 18 121 19 120 20 119 21 AD8151 118 22 184L LQFP TOP VIEW (Not to Scale) 117 23 24 116 115 Figure 51. Bypassing Schematic Rev. B | Page 35 of 40 C60 0.
PAGE 36
AD8151 VCC R19 1.65kΩ VCC IN00P P4 R20 105Ω P5 IN00N R21 1.65kΩ R40 1.65kΩ VCC IN06P VCC IN12P P28 P16 R39 105Ω P17 IN06N R38 1.65kΩ VEE R58 1.65kΩ IN18P R56 1.65kΩ IN12N R90 105Ω P41 VCC IN24P IN24N R92 1.65kΩ VEE R116 1.65kΩ IN30P OUT08P R160 49.9Ω P64 R93 105Ω P53 IN18N R91 1.65kΩ VEE R94 1.65kΩ P52 P40 R57 105Ω P29 VEE VCC R89 1.65kΩ R117 105Ω P65 R118 1.65kΩ VEE OUT08N R162 49.9Ω P30 VEE OUT09P R165 49.9Ω R28 1.65kΩ P8 IN02P R27 105Ω P9 R44 1.
PAGE 37
AD8151 CLK P2 5 A1 4 74HC14 VSS P2 25 5 1 A1 2 6 3 74HC14 4 5 VSS 6 7 VDD 8 9 10 VSS 20 1 19 2 18 3 17 D2 Q2 16 D3 Q3 A2 15 D4 74HC74 Q4 14 D5 Q5 13 D6 Q6 12 D7 Q7 11 CLK GND 4 OUT_EN VCC D0 Q0 D1 Q1 5 OUT_EN VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 20 19 9 VDD VDD VDD VSS 8 74HC14 A1 11 10 18 17 16 74HC14 A1 12 A3 15 D4 74HC74 Q4 7 14 D5 Q5 8 13 D6 Q6 9 12 Q7 D7 10 CLK 11 GND 6 A1 13 74HC14 A4 9 10 74HC132 A4 12 13 R7 49Ω VSS VSS R1 20kΩ VSS VSS A4 3 2 VSS
PAGE 38
AD8151 OUTLINE DIMENSIONS 0.75 0.60 0.45 22.20 22.00 SQ 21.80 1.60 MAX 184 1 139 138 PIN 1 20.20 20.00 SQ 19.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 93 92 46 47 VIEW A 0.40 BSC LEAD PITCH VIEW A 0.23 0.18 0.13 ROTATED 90° CCW Figure 54.
PAGE 39
AD8151 NOTES Rev.