Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches LQFP 100

Audio/Video, 60 MHz, 16 × 8,

Gain of +2 Crosspoint Switch

AD8112

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Low cost, 16 × 8, high speed, nonblocking switch array

Pin-compatible 16 × 16 version available (AD8113)

Serial or parallel programming of switch array

Serial data out allows daisy chaining control of multiple

16 × 8 arrays to create larger switch arrays

Output disable allows connection of multiple devices

without loading the output bus

Complete solution

Buffered inputs

8 output amplifiers

Operates on ±5 V or ±12 V supplies

Low supply current of 54 mA

Excellent audio performance V

= ±12 V

±10 V output swing

0.002% THD at 20 kHz maximum 20 V p-p (R

= 600 Ω)

Excellent video performance V

= ±5 V

0.1 dB gain flatness of 10 MHz

0.1% differential gain error (R

= 1 kΩ)

0.1° differential phase error (R

= 1 kΩ)

Excellent ac performance

−3 dB bandwidth 60 MHz

Low all-hostile crosstalk of −83 dB at 20 kHz

Reset pin allows disabling of all outputs (connected to a

capacitor to ground provides power-on reset capability)

100-lead LQFP (14 mm × 14 mm)

APPLICATIONS

CCTV surveillance/DVR

Analog/digital audio routers

Video routers (NTSC, PAL, S-Video, SECAM)

Multimedia systems

Video conferencing

FUNCTIONAL BLOCK DIAGRAM

06523-001

AD8112

40 40

128

PARALLEL LATCH

CLK

DATA IN

RESET

16 INPUTS

DATA

OUT

8 OUTPUTS

D0 D1 D2 D3 D4

ENABLE/DISABLE

SWITCH

MATRIX

SER/PAR

UPDATE

DECODE

8 × 5:16 DECODERS

80-BIT SHIFT REGISTER

WITH 5-BIT

PARALLEL LOADING

OUTPUT

BUFFER

G = +2

SET INDIVIDUAL OR

RESET ALL OUTPUTS

TO OFF

CONNECT

Figure 1.

GENERAL DESCRIPTION

The AD8112 is a low cost, fully buffered crosspoint switch matrix

that operates on ±12 V for audio applications and ±5 V for

video applications. It offers a −3 dB signal bandwidth greater

than 60 MHz and channel switch times of less than 60 ns with

0.1% settling for use in both analog and digital audio. The

AD8112 operated at 20 kHz has a crosstalk performance of

−83 dB and isolation of 90 dB. In addition, ground/power pins

surround all inputs and outputs to provide extra shielding for

operation in the most demanding audio routing applications.

With a differential gain and differential phase better than 0.1%

and 0.1°, respectively, and a 0.1 dB flatness output of up to 10 MHz,

the AD8112 is suitable for many video applications.

The AD8112 includes eight independent output buffers that can

be placed into a disabled state for paralleling crosspoint outputs

so that off channel loading is minimized. The AD8112 has a gain

of +2. It operates on voltage supplies of ±5 V or ±12 V while

consuming only 34 mA or 31 mA of current, respectively. The

channel switching is performed via a serial digital control (which

can accommodate the daisy chaining of several devices) or via

a parallel control, allowing updating of an individual output

without reprogramming the entire array.

The AD8112 is packaged in a 100-lead LQFP and is available

over the commercial temperature range of 0°C to 70°C.

Summary of content (28 pages)

PAGE 1
Audio/Video, 60 MHz, 16 × 8, Gain of +2 Crosspoint Switch AD8112 FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM SER/PAR D0 D1 D2 D3 D4 A0 A1 A2 CLK 80-BIT SHIFT REGISTER WITH 5-BIT PARALLEL LOADING 40 RESET 40 NO CONNECT DECODE 8 × 5:16 DECODERS AD8112 128 OUTPUT BUFFER G = +2 06523-001 SWITCH MATRIX 8 8 OUTPUTS 40 PARALLEL LATCH CE SET INDIVIDUAL OR RESET ALL OUTPUTS TO OFF UPDATE DATA OUT ENABLE/DISABLE DATA IN 16 INPUTS Low cost, 16 × 8, high speed, nonblocking switch array Pin-com
PAGE 2
AD8112 TABLE OF CONTENTS Features .............................................................................................. 1 Calculation of Power Dissipation............................................. 17 Applications....................................................................................... 1 Short-Circuit Output Conditions............................................. 18 Functional Block Diagram .............................................................. 1 Application Notes .....
PAGE 3
AD8112 SPECIFICATIONS TA = 25°C, VS = ±12 V, RL = 600 Ω, unless otherwise noted. Table 1.
PAGE 4
AD8112 Parameter SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) POWER SUPPLIES Supply Current DYNAMIC PERFORMANCE Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θJA Conditions Min Typ 50% update to 1% settling 80 50 20 AVCC outputs enabled, no load, VS = ±12 V AVCC outputs disabled, VS = ±12 V AVCC outputs enabled, no load, VS = ±5 V AVCC outputs disabled, VS = ±5 V AVEE outputs enabled, no load, VS = ±12 V AVEE outputs disabl
PAGE 5
AD8112 TIMING CHARACTERISTICS (SERIAL) Table 2.
PAGE 6
AD8112 TIMING CHARACTERISTICS (PARALLEL) Table 4. Parameter Data Setup Time CLK Pulse Width Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and Fall Times RESET Time Symbol t1 t2 t3 t4 t5 t6 Limit Max Min 20 100 20 100 0 50 Unit ns ns ns ns ns ns ns ns ns 50 100 200 t2 t4 1 CLK 0 t1 D0 TO D4 A0 TO A2 t3 1 0 t5 t6 06523-003 1 = LATCHED UPDATE 0 = TRANSPARENT Figure 3.
PAGE 7
AD8112 ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION Output Short-Circuit Duration Storage Temperature Range Lead Temperature (Soldering 10 sec) Rating 26.0 V 6V ±0.5 V 3.1 W Maintain linear output DVCC (AVCC − 1.5 V) to (AVEE + 1.5 V) Momentary −65°C to +125°C 300°C 1 Specification is for device in free air (TA = 25°C): 100-lead plastic LQFP (ST): θJA = 40°C/W.
PAGE 8
AD8112 Table 7. Operation Truth Table CE UPDATE 1 0 X 1 0 1 0 0 X X X X PARALLEL DATA (OUTPUT ENABLE) CLK X DATA IN X Data i DATA OUT X Data i-80 D0 ... D4, A0 ... A2 X N/A in Parallel Mode X X X RESET SER/PAR X 1 X 0 1 1 1 X 0 X Operation/Comment No change in logic. The data on the serial DATA IN line is loaded into serial register. The first bit clocked into the serial register appears at DATA OUT 80 clocks later.
PAGE 9
AD8112 DATA OUT CLK DATA IN UPDATE SER/PAR NC NC NC NC NC NC NC NC NC A0 A1 A2 DGND D0 D1 D2 D3 D4 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DVCC 1 DGND 2 AGND 3 73 AGND IN08 4 72 IN07 AGND 5 71 AGND IN09 6 70 IN06 AGND 7 69 AGND IN05 PIN 1 75 DVCC 74 DGND IN10 8 68 AGND 9 67 AGND IN11 10 66 IN04 AGND 11 IN12 12 AGND 13 IN13 65 AGND 64 IN03 63 AGND 14 62 IN02 AGND 15 61 AGND IN14
PAGE 10
AD8112 Pin No. 21, 22, 26, 30, 34, 38, 55 54 Mnemonic AVCC AVCCxx 50, 46, 42 AVCCxx/yy1 52, 48, 44, 40 AVEExx/yy1 84 83 82 80 79 78 77 76 23, 25, 27, 29, 31, 33, 35, 37, 85 to 93 A0 A1 A2 D0 D1 D2 D3 D4 NC 1 Description 5 V for Inputs and Switch Matrix. 5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy. Must be connected. 5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy. Must be connected. −5 V for Output Amplifier.
PAGE 11
AD8112 I/O SCHEMATICS VCC VCC ESD ESD INPUT INPUT 06523-007 AVEE 06523-010 ESD ESD DGND Figure 7. Analog Input Figure 10. Logic Input VCC VCC 2kΩ ESD ESD OUTPUT OUTPUT 06523-008 ESD AVEE DGND Figure 8. Analog Output Figure 11. Logic Output VCC ESD 20kΩ RESET DGND 06523-009 ESD Figure 9. Reset Input Rev.
PAGE 12
AD8112 TYPICAL PERFORMANCE CHARACTERISTICS 3 0 0 GAIN (dB) GAIN (dB) 3 –3 0.1 1 FREQUENCY (MHz) 10 –6 0.1 100 Figure 12. Small-Signal Bandwidth, VS = ±5 V, RL = 150 Ω, VOUT = 200 mV p-p 06523-047 06523-013 –6 0.01 –3 1 10 FREQUENCY (MHz) 100 Figure 15. Small-Signal Bandwidth, VS = ±12 V, RL = 600 Ω, VOUT = 200 mV p-p 0.3 0.3 0.2 GAIN FLATNESS (dB) GAIN FLATNESS (dB) 0.2 0.1 0 –0.1 0.1 0 –0.1 06523-048 –0.2 –0.3 0.1 06523-014 –0.2 1 10 FREQUENCY (MHz) –0.3 0.
PAGE 13
AD8112 0.3 0.3 0.2 GAIN FLATNESS (dB) 0.1 0 –0.1 0.1 0 –0.1 –0.2 06523-016 –0.2 –0.3 0.1 1 10 FREQUENCY (MHz) 06523-050 GAIN FLATNESS (dB) 0.2 –0.3 0.1 100 Figure 18. Large-Signal Gain Flatness, VS = ±5 V, RL = 150 Ω, VOUT = 2 V p-p 1 FREQUENCY (MHz) 10 Figure 21. Large-Signal Gain Flatness, VS = ±12 V, RL = 600 Ω, VOUT = 8 V p-p –30 –40 ALL HOSTILE –40 –50 ALL HOSTILE CROSSTALK (dB) ADJACENT –70 –80 –90 –50 –60 ADJACENT –70 06523-017 –80 –100 0.
PAGE 14
AD8112 300 CAPACITIVE LOAD (pF) 250 INPUT 0.1%/DIV 200 VS = ±12V RL = 600Ω 150 OUTPUT – INPUT 2 VS = ±5V RL = 150Ω 100 OUTPUT 06523-019 06523-022 50 0 5 10 15 20 25 SERIES RESISTANCE (Ω) 30 0 35 1k 1k IMPEDANCE (Ω) 20 25 30 35 40 45 50 100 10 100 06523-020 10 1 10 FREQUENCY (MHz) 100 1 0.1 1k Figure 25. Disabled Output Impedance vs. Frequency, VS = ±5 V 06523-053 IMPEDANCE (Ω) 10k 1 10 FREQUENCY (MHz) 100 1k Figure 28. Disabled Output Impedance vs.
PAGE 15
AD8112 0 0 –10 –20 –20 –40 PSRR (dB) +PSRR –50 –PSRR –40 +PSRR –60 –PSRR –60 –70 –80 06523-023 –80 –90 0.01 0.1 1 FREQUENCY (MHz) –100 0.01 10 Figure 30. PSRR vs. Frequency, VS = ±5 V 06523-055 PSRR (dB) –30 0.1 1 FREQUENCY (MHz) 10 Figure 33. PSRR vs. Frequency, VS = ±12 V 160 0 140 –20 OFF ISOLATION (dB) NOISE (nV/ Hz) 120 100 80 60 –40 –60 VS = ±12V RL = 600Ω VOUT = 8V p-p –80 40 100 1k 10k 100k FREQUENCY (Hz) 1M –120 0.1 10M Figure 31. Noise vs.
PAGE 16
AD8112 500mV/DIV 06523-057 06523-027 5V/DIV 100ns/DIV 100ns/DIV Figure 36. Large-Signal Pulse Response, VS = ±5 V, RL = 150 Ω Figure 39. Large-Signal Pulse Response, VS = ±12 V, RL = 600 Ω UPDATE UPDATE 2V/DIV 2V/DIV VOUT VOUT INPUT 1 10V/DIV INPUT 1 INPUT 0 06523-058 06523-028 INPUT 0 100ns/DIV 100ns/DIV Figure 37. Switching Time, VS = ±5 V, RL = 150 Ω Figure 40.
PAGE 17
AD8112 THEORY OF OPERATION Features of the AD8112 facilitate the construction of larger switch matrices. The unused outputs can be disabled, leaving only a feedback network resistance of 4 kΩ on the output. This allows multiple ICs to be bused together, provided the output load impedance is greater than the minimum allowed values. Because no additional input buffering is necessary, high input resistance and low input capacitance are easily achieved without additional signal degradation.
PAGE 18
AD8112 2. When calculating on-chip power dissipation, it is necessary to include the rms current being delivered to the load multiplied by the rms voltage drop on the AD8112 output devices. The dissipation of the on-chip, 4 kΩ feedback resistor network must also be included.
PAGE 19
AD8112 APPLICATION NOTES The AD8112 has two options for changing the programming of the crosspoint matrix. In the first option, a serial word of 80 bits is provided to update the entire matrix. The serial data needs to be prefixed with 40 zeros because there are 40 unconnected bits. The second option allows for changing a single output’s programming via a parallel interface.
PAGE 20
AD8112 low. This technique should be used when programming the device for the first time after power-up when using parallel programming. Because P = V2/R, the voltage required to create 1 mW into 600 Ω is 0.775 V rms. This is the voltage reference (0 dB) used for dBu measurements without regard to the impedance. POWER-ON RESET The AD8112 operates as a voltage-in/voltage-out device.
PAGE 21
AD8112 The basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to wire-OR the outputs together in the vertical direction. The meaning of horizontal and vertical can best be understood by looking at Figure 46, which illustrates this concept for a 32 × 16 crosspoint array that uses four AD8112s. IN00 TO IN15 The AD8112 outputs are very low impedance and do not properly terminate the source end of a 75 Ω transmission line.
PAGE 22
AD8112 RANK 1 (8 × AD8112) 128:16 IN00 TO IN15 1kΩ AD8112 16 4 1kΩ 4 1kΩ RTERM 4 1kΩ IN16 TO IN31 1kΩ AD8112 16 4 1kΩ RTERM 4 1kΩ IN32 TO IN47 1kΩ AD8112 16 4 1kΩ RANK 2 16:8 NONBLOCKING (16:16 BLOCKING) RTERM 4 1kΩ IN48 TO IN63 1kΩ AD8112 16 4 4 1kΩ 4 1kΩ RTERM 4 1kΩ IN64 TO IN79 1kΩ AD8112 16 4 1kΩ RTERM 1kΩ AD8112 16 4 OUT00 TO OUT07 NONBLOCKING 4 AD8112 1kΩ 4 ADDITIONAL EIGHT OUTPUTS (SUBJECT TO BLOCKING) 4 1kΩ RTERM 4 1kΩ IN96 TO IN111 1kΩ 4 4 1kΩ 4 1kΩ 4
PAGE 23
AD8112 MULTICHANNEL VIDEO AND AUDIO The video specifications of the AD8112 make it an ideal candidate for creating composite video crosspoint switches. These can be made quite dense by taking advantage of the AD8112’s high level of integration and the fact that composite video requires only one crosspoint channel per system video channel. There are, however, other video formats that can be routed with the AD8112, requiring more than one crosspoint channel per video channel.
PAGE 24
AD8112 All these sources of crosstalk are vector quantities; therefore the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in parallel in a given configuration can reduce the crosstalk. Areas of Crosstalk A practical AD8112 circuit must be mounted to some sort of circuit board to connect it to power supplies and measurement equipment.
PAGE 25
AD8112 For output crosstalk measurement, a single input channel is driven (IN00, for example) and all outputs other than a given output (IN07 in the middle) are programmed to connect to IN00. OUT07 is programmed to connect to IN15 (not in close proximity to IN00), which is terminated to ground. Therefore, OUT07 should not have a signal present because it is listening to a quiet input. Any signal measured at the OUT07 can be attributed to the output crosstalk of the other seven hostile outputs.
PAGE 26
AD8112 PCB LAYOUT Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas that must be carefully designed are grounding, shielding, signal routing, and supply bypassing. The packaging of the AD8112 is designed to help minimize crosstalk. Each input is separated from each other input by an analog ground pin. All of these AGNDs should be directly connected to the ground plane of the circuit board.
PAGE 27
AD8112 AVEE AGND AVCC P1-4 NC P1-6 P1-7 + DVCC + 0.1µF 10µF AVCC 0.01µF 0.1µF 66 INPUT 04 75Ω 67 68 INPUT 05 75Ω 69 70 INPUT 06 75Ω 71 72 INPUT 07 75Ω 3, 73 4 INPUT 08 75Ω 5 6 INPUT 09 75Ω 7 8 INPUT 10 75Ω 9 10 INPUT 11 75Ω 11 12 INPUT 12 75Ω 13 14 INPUT 13 75Ω 15 16 INPUT 14 75Ω 17 18 INPUT 15 75Ω 19 98 96 R R 53 0.
PAGE 28
AD8112 OUTLINE DIMENSIONS 16.20 16.00 SQ 15.80 1.60 MAX 0.75 0.60 0.45 100 1 76 75 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 51 50 25 26 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BED 051706-A 1.45 1.40 1.35 Figure 49.