Datasheet

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325 MHz, 8 × 8 Buffered Video

Crosspoint Switches

AD8108/AD8109

Rev. B

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EATURES

8 × 8 high speed nonblocking switch arrays

AD8108: G = 1

AD8109: G = 2

Serial or parallel programming of switch array

Serial data out allows daisy-chaining of multiple 8 × 8 arrays

to create larger switch arrays

Output disable allows connection of multiple devices

Pin-compatible with AD8110/AD8111 16 × 8 switch arrays

For 16 × 16 arrays see AD8116

Complete solution

Buffered inputs

Eight output amplifiers

AD8108 (G = 1)

AD8109 (G = 2)

Drives 150 Ω loads

Excellent video performance

60 MHz 0.1 dB gain flatness

0.02%/0.02° differential gain/differential phase error

= 150 Ω)

Excellent ac performance

−3 dB bandwidth: 325 MHz (AD8108), 250 MHz (AD8109)

Slew rate: 400 V/μs (AD8108), 480 V/μs (AD8109)

Low power of 45 mA

Low all hostile crosstalk of −83 dB @ 5 MHz

Reset pin allows disabling of all outputs (connected through

a capacitor to ground provides power-on reset capability)

Excellent ESD rating: exceeds 4000 V human body model

80-lead LQFP (12 mm × 12 mm)

APPLICATIONS

Routing of high speed signals including

Composite video (NTSC, PAL, S, SECAM)

Component video (YUV, RGB)

Compressed video (MPEG, Wavelet)

3-level digital video (HDB3)

GENERAL DESCRIPTION

The AD8108/AD8109 are high speed 8 × 8 video crosspoint

switch matrices. They offer a −3 dB signal bandwidth greater than

250 MHz and channel switch times of less than 25 ns with 1%

settling. With −83 dB of crosstalk and −98 dB isolation (@5 MHz),

the AD8108/AD8109 are useful in many high speed applications.

The differential gain and differential phase of better than 0.02%

FUNCTIONAL BLOCK DIAGRAM

AD8108/AD8109

SWITCH

MATRIX

OUTPUT

BUFFER

G = +1

G = +2

32-BIT SHIFT REGISTER

WITH 4-BIT

PARALLEL LOADING

PARALLEL LATCH

DECODE

8  4:8 DECODERS

CLK

DATA IN

UPDATE

RESET

8 INPUTS

DATA

OUT

8 OUTPUTS

SET INDIVIDUAL

OR RESET ALL

OUTPUTS

TO "OFF"

SER/PAR

D0 D1 D2 D3

ENABLE/DISABLE

01068-001

Figure 1. Functional Block Diagram

and 0.02°, respectively, along with 0.1 dB flatness out to 60 MHz,

make the AD8108/AD8109 ideal for video signal switching.

The AD8108 and AD8109 include eight independent output

buffers that can be placed into a high impedance state for paral-

leling crosspoint outputs so that off channels do not load the

output bus. The AD8108 has a gain of 1, while the AD8109

offers a gain of 2. They operate on voltage supplies of ±5 V

while consuming only 45 mA of idle current. The channel

switching is performed via a serial digital control (which can

accommodate daisy-chaining of several devices) or via a parallel

control allowing updating of an individual output without

re-programming the entire array.

The AD8108/AD8109 is packaged in an 80-lead LQFP package

and is available over the extended industrial temperature range

of −40°C to +85°C.

Summary of content (33 pages)

PAGE 1
325 MHz, 8 × 8 Buffered Video Crosspoint Switches AD8108/AD8109 FUNCTIONAL BLOCK DIAGRAM EATURES APPLICATIONS Routing of high speed signals including Composite video (NTSC, PAL, S, SECAM) Component video (YUV, RGB) Compressed video (MPEG, Wavelet) 3-level digital video (HDB3) GENERAL DESCRIPTION The AD8108/AD8109 are high speed 8 × 8 video crosspoint switch matrices. They offer a −3 dB signal bandwidth greater than 250 MHz and channel switch times of less than 25 ns with 1% settling.
PAGE 2
Powered by TCPDF (www.tcpdf.org) IMPORTANT LINKS for the AD8108_8109* Last content update 08/23/2013 02:21 pm PARAMETRIC SELECTION TABLES DESIGN COLLABORATION COMMUNITY Find Similar Products By Operating Parameters High Speed Switches Collaborate Online with the ADI support team and other designers about select ADI products.
PAGE 3
AD8108/AD8109 TABLE OF CONTENTS AD8108/AD8109—Specifications ................................................. 3 Power-On RESET....................................................................... 19 Timing Characteristics (Serial) .................................................. 5 Gain Selection............................................................................. 19 Timing Characteristics (Parallel) ............................................... 6 Creating Larger Crosspoint Arrays........
PAGE 4
AD8108/AD8109 AD8108/AD8109—SPECIFICATIONS VS = ±5 V, TA = +25°C, RL = 1 kΩ, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Unit Reference 325/250 MHz 2 V p-p, RL = 150 Ω 140/160 MHz Figure 1, Figure 13 Figure 1, Figure 13 Propagation Delay Slew Rate Settling Time 2 V p-p, RL = 150 Ω 2 V Step, RL = 150 Ω 0.1%, 2 V Step, RL = 150 Ω 5 400/480 40 ns V/µs ns Gain Flatness 0.05 dB, 200 mV p-p, RL = 150 Ω 60/50 MHz 0.05 dB, 2 V p-p, RL = 150 Ω 60/50 MHz 0.
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AD8108/AD8109 Parameter INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) POWER SUPPLIES Supply Current Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θJA Conditions Min Typ Max Unit Reference Worst case (all configurations) 5 20 mV Temperature coefficient 12 µV/°C Figure 35, Figure 41 Figure 36, Figure 42
PAGE 6
AD8108/AD8109 TIMING CHARACTERISTICS (SERIAL) Table 2. Timing Characteristics Parameter Serial Data Setup Time CLK Pulse Width Serial Data Hold Time CLK Pulse Separation, Serial Mode CLK to UPDATE Delay UPDATE Pulse Width CLK to DATA OUT Valid, Serial Mode Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz, Serial Mode CLK, UPDATE Rise and Fall Times RESET Time Symbol t1 t2 t3 t4 t5 t6 t7 – – – – Min 20 100 20 100 0 50 Typ Max 180 8 6.
PAGE 7
AD8108/AD8109 TIMING CHARACTERISTICS (PARALLEL) Table 4. Timing Characteristics Parameter Data Setup Time CLK Pulse Width Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and Fall Times RESET Time Symbol t1 t2 t3 t4 t5 t6 – – – Min 20 100 20 100 0 50 Typ Max 8 100 200 Unit ns ns ns ns ns ns ns ns ns Table 5.
PAGE 8
AD8108/AD8109 Table 6. Operation Truth Table UPDATE X 1 SER/ PAR X 0 NA in parallel mode X 1 1 1 X X 0 X X 1 CLK X f DATA IN X Datai DATA OUT X Datai-32 0 1 f 0 0 X D0 … D3, A0 … A2 X… X X X X RESET Operation/Comment No change in logic. The data on the serial DATA IN line is loaded into serial register. The first bit clocked into the serial register appears at DATA OUT 32 clocks later.
PAGE 9
AD8108/AD8109 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Supply Voltage Internal Power Dissipation1 AD8108/AD8109 80-Lead Plastic LQFP (ST) Input Voltage Output Short-Circuit Duration Storage Temperature Range2 2 2.6 W ±VS Observe power derating curves −65°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 10
AD8108/AD8109 RESET DGND DVCC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC DVCC DGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 IN00 1 60 CE 59 DATA OUT IN01 3 58 CLK AGND 4 57 DATA IN IN02 5 56 UPDATE AGND 6 55 SER/PAR IN03 7 54 A0 53 A1 52 A2 AGND 10 51 D0 IN05 11 50 D1 AGND 12 49 D2 IN06 13 48 D3 AGND 14 47 NC IN07 15 46 AGND AGND 16 45 AVEE AVEE 17 44 AVCC AVCC 18 43 AVCC
PAGE 11
AD8108/AD8109 Table 8. Pin Function Descriptions Pin No. 1, 3, 5, 7, 9, 11, 13, 15 57 58 59 56 Mnemonic INxx DATA IN CLK DATA OUT UPDATE 61 60 55 41, 38, 35, 32, 29, 26, 23, 20 2, 4, 6, 8, 10, 12, 14, 16, 46 63, 79 62, 80 17, 45 18, 44 42, 39, 36, 33, 30, 27, 24, 21 43, 37, 31, 25, 19 40, 34, 28, 22 54 53 52 51 50 49 48 47, 64 to 78 RESET CE SER/PAR OUTyy AGND DVCC DGND AVEE AVCC AGNDxx AVCCxx/yy AVEExx/yy A0 A1 A2 D0 D1 D2 D3 NC Description Analog Inputs. xx = Channels 00 through 07.
PAGE 12
AD8108/AD8109 TYPICAL PERFORMANCE CHARACTERISTICS 5 0.4 RL = 150Ω 0.3 0.2 2 0.1 +50mV FLATNESS 0 1 200mV p-p 0 –0.1 GAIN 25mV/DIV 3 FLATNESS (dB) GAIN (dB) 4 +25mV 0 –25mV –50mV –0.2 –1 –3 100k 1M 10M FREQUENCY (Hz) 100M 01068-012 –0.3 –2 01068-015 2V p-p –0.4 1G 10ns/DIV Figure 10. AD8108 Step Response, 100 mV Step Figure 7. AD8108 Frequency Response –10 RL = 1kΩ –20 –30 +1.0V 500mV/DIV CROSSTALK (dB) –40 –50 ALL HOSTILE –60 –70 +0.5V 0 –0.5V –1.
PAGE 13
AD8108/AD8109 5 0.4 4 0.3 3 0.2 +50mV 200mV p-p 1 0 –0.1 0 GAIN +25mV 0 –25mV –50mV –0.3 2V p-p –2 –3 100k 1M 10M FREQUENCY (Hz) –0.4 1G 100M 01068-021 –0.2 –1 01068-018 GAIN (dB) FLATNESS 25mV/DIV 0.1 2 FLATNESS (dB) 2V p-p 10ns/DIV Figure 16. AD8109 Step Response, 100 mV Step Figure 13. AD8109 Frequency Response –20 RL = 1kΩ –30 –40 0.5V/DIV CROSSTALK (dB) +1.0V –50 –60 ADJACENT –70 +0.5V 0 –0.5V –80 –1.
PAGE 14
AD8108/AD8109 –30 5 SWITCHING BETWEEN TWO INPUTS 1V/DIV 4 –50 3 UPDATE INPUT 2 1 –60 0 –70 10mV/DIV 10 –90 10k 100k 1M FREQUENCY (Hz) 0 TYPICAL VIDEO OUT (RTO) –10 01068-027 –80 01068-024 POWER SUPPLY REJECTION (dB) RL = 150Ω –40 50ns/DIV 10M Figure 19. AD8108 PSRR vs. Frequency Figure 22. AD8108 Switching Transient (Glitch) 100 –40 –50 56.3 VIN = 2V p-p RL = 150Ω OFF ISOLATION (dB) –60 17.
PAGE 15
AD8108/AD8109 –30 5 1V/DIV –50 3 0 –70 –80 100k 1M FREQUENCY (Hz) 0 TYPICAL VIDEO OUT (RTO) –10 01068-033 10mV/DIV 10 50ns/DIV 10M Figure 25. AD8109 PSRR vs. Frequency Figure 28. AD8109 Switching Transient (Glitch) 100.0 –40 –50 56.3 VOUT = 2V p-p RL = 150Ω OFF ISOLATION (dB) –60 31.6 17.8 10.0 –70 –80 –90 –100 –110 01068-031 3.16 10 100 1k 100k 10k FREQUENCY (Hz) 1M –130 –140 100k 10M Figure 26. AD8109 Voltage Noise vs.
PAGE 16
AD8108/AD8109 1M 1V/DIV VOUT INPUT IMPEDANCE (Ω) 100k 1 INPUT 1 AT +1V 0 –1 INPUT 0 AT –1V 10k 2V/DIV 5 1k UPDATE 01068-036 100 30k 01068-039 0 100k 1M 10M FREQUENCY (Hz) 100M 50ns/DIV 500M Figure 34. AD8108 Switching Time Figure 31. AD8108 Input Impedance vs. Frequency 900 VIN = 200mV RL = 150Ω CL = 18pF 800 6 700 FREQUENCY 2 CL = 12pF 0 –2 600 500 400 –4 300 –6 200 01068-037 GAIN (dB) 4 –8 30k 100k 1M 10M 100M FREQUENCY (Hz) 1G 100 0 –0.020 3G –0.010 0.
PAGE 17
AD8108/AD8109 1M 1V/DIV VOUT INPUT IMPEDANCE (Ω) 100k 1 INPUT 1 AT +1V 0 –1 INPUT 0 AT –1V 10k 2V/DIV 5 1k UPDATE 01068-042 100 30k 01068-045 0 100k 1M 10M FREQUENCY (Hz) 100M 50ns/DIV 500M Figure 40. AD8109 Switching Time Figure 37. AD8109 Input Impedance vs.
PAGE 18
AD8108/AD8109 I/O SCHEMATICS VCC VCC ESD ESD INPUT INPUT ESD AVEE 01068-009 01068-006 ESD DGND Figure 43. Analog Input Figure 46. Logic Input VCC VCC ESD 2kΩ ESD OUTPUT OUTPUT DGND Figure 44. Analog Output Figure 47. Logic Output VCC ESD 20kΩ DGND 01068-008 ESD Figure 45. Reset Input Rev.
PAGE 19
AD8108/AD8109 THEORY OF OPERATION The AD8108 (G = 1) and AD8109 (G = 2) share a common core architecture consisting of an array of 64 transconductance (gm) input stages organized as eight 8:1 multiplexers with a common 8-line analog input bus. Each multiplexer is basically a foldedcascode, high impedance voltage feedback amplifier with eight input stages.
PAGE 20
AD8108/AD8109 AD8108/AD8109. When taken low, the RESET signal will only set each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs will not be active at the same time. After initial power-up, the internal registers in the device will generally have random data, even though the RESET signal was asserted.
PAGE 21
AD8108/AD8109 8 The first consideration in constructing a larger crosspoint is to determine the minimum number of devices required. The 8 × 8 architecture of the AD8108/AD8109 contains 64 points, which is a factor of 16 greater than a 4 × 1 crosspoint. The PC board area and power consumption savings are readily apparent when compared to using these smaller devices. For a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs.
PAGE 22
AD8108/AD8109 Using additional crosspoint devices in the design can lower the number of outputs that must be wire-OR’ed together. Figure 51 shows a block diagram of a system using eight AD8108s and two AD8109s to create a nonblocking, gain-of-2, 64 × 8 crosspoint that restricts the wire-OR’ing at the output to only four outputs. The rank 1 wire-OR’ed devices are AD8108s, which have higher disabled output impedance than the AD8109.
PAGE 23
AD8108/AD8109 CROSSTALK Many systems, such as broadcast video, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the others in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. When there are many signals in proximity in a system, as will undoubtedly be the case in a system that uses the AD8108/ AD8109, the crosstalk issues can be quite complex.
PAGE 24
AD8108/AD8109 quickly grow to astronomical proportions. If a larger crosspoint array of multiple AD8108/AD8109s is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure all hostile crosstalk. This term means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel.
PAGE 25
AD8108/AD8109 PCB LAYOUT The packaging of the AD8108/AD8109 is designed to help keep the crosstalk to a minimum. Each input is separated from each other input by an analog ground pin. All of these AGNDs should be directly connected to the ground plane of the circuit board. These ground pins provide shielding, low impedance return paths, and physical separation for the inputs. All of these help to reduce crosstalk.
PAGE 26
01068-053 AD8108/AD8109 01068-054 Figure 53. Component Side Silkscreen Figure 54. Board Layout (Component Side) Rev.
PAGE 27
01068-055 AD8108/AD8109 01068-056 Figure 55. Board Layout (Signal Layer) Figure 56. Board Layout (Power Plane) Rev.
PAGE 28
01068-057 AD8108/AD8109 Figure 57. Board Layout (Bottom Layer) Rev.
PAGE 29
AD8108/AD8109 EVALUATION BOARD A 4-layer evaluation board for the AD8108/AD8109 is available. The exact same board and external components are used for each device. The only difference is the device itself, which offers a selection of a gain of unity or gain of 2 through the analog channels. This board has been carefully laid out and tested to demonstrate the specified high speed performance of the device. Figure 60 shows the schematic of the evaluation board. Figure 53 shows the component side silk-screen.
PAGE 30
AD8108/AD8109 AVEE AGND AVCC P1-4 P1-5 NC P1-7 P1-6 + DVCC + 0.1µF 10µF AVCC DVCC 0.01µF 0.01µF AVCC 0.01µF AVEE 0.01µF 0.01µF 0.1µF 10µF 0.
PAGE 31
AD8108/AD8109 OUTLINE DIMENSIONS 0.75 0.60 0.45 14.00 BSC SQ 1.60 MAX 80 61 60 1 PIN 1 12.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 20 41 21 VIEW A VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW 40 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BDD Figure 61.
PAGE 32
AD8108/AD8109 NOTES Rev.