Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD1938WBSTZ

4 ADC/8 DAC with PLL,

192 kHz, 24-Bit Codec

Data Sheet

AD1938

Rev. E Document Feedback

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FEATURES

PLL generated or direct master clock

Low EMI design

108 dB DAC/107 dB ADC dynamic range and SNR

−94 dB THD + N

3.3 V single supply

Tolerance for 5 V logic inputs

Supports 24 bits and 8 kHz to 192 kHz sample rates

Differential ADC input

Single-ended DAC output

Log volume control with autoramp function

SPI controllable for flexibility

Software-controllable clickless mute

Software power-down

Right-justified, left-justified, I

S-justified, and TDM modes

Master and slave modes up to 16-channel input/output

48-lead LQFP package

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Home Theater Systems

Set-top boxes

Digital audio effects processors

GENERAL DESCRIPTION

The AD1938 is a high performance, single-chip codec that pro-

vides four analog-to-digital converters (ADCs) with input and

eight digital-to-analog converters (DACs) with single-ended output

using the Analog Devices, Inc., patented multibit sigma-delta (Σ-Δ)

architecture. An SPI port is included, allowing a microcontroller

to adjust volume and many other parameters.

The AD1938 operates from 3.3 V digital and analog supplies.

The AD1938 is available in a 48-lead (single-ended output)

LQFP package. Other members of this family include a diffe-

rential DAC output and I

C® control port version.

The AD1938 is designed for low EMI. This consideration is

apparent in both the system and circuit design architectures.

By using the on-board PLL to derive the master clock from

the LR clock or from an external crystal, the AD1938 elimi-

nates the need for a separate high frequency master clock and

can also be used with a suppressed bit clock. The DACs and

ADCs are designed using the latest Analog Devices continuous

time architectures to further minimize EMI. By using 3.3 V

supplies, power consumption is minimized, further reducing

emissions.

FUNCTIONAL BLOCK DIAGRAM

DIGITAL

FILTER

SERIAL DATA PORT

DIGITAL AUDIO

INPUT/OUTPUT

PRECISION

VOLTAGE

REFERENCE

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL)

SPI CONTROL PORT

CONTROL DATA

INPUT/OUTPUT

AD1938

ADC

ANALOG

AUDIO

INPUTS

ANALOG

AUDIO

OUTPUTS

DAC

DIGITAL

FILTER

AND

VOLUME

CONTROL

SDATA

OUT

SDATA

CLOCKS

05582-001

Figure 1.

Summary of content (32 pages)

PAGE 1
4 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec AD1938 Data Sheet FEATURES GENERAL DESCRIPTION PLL generated or direct master clock Low EMI design 108 dB DAC/107 dB ADC dynamic range and SNR −94 dB THD + N 3.
PAGE 2
AD1938 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog-to-Digital Converters (ADCs) .................................... 13 Applications ....................................................................................... 1 Digital-to-Analog Converters (DACs) .................................... 13 General Description .........................................................................
PAGE 3
Data Sheet AD1938 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages (AVDD, DVDD) Temperature range1 Master clock Input sample rate Measurement bandwidth Word width Load capacitance (digital output) Load current (digital output) Input voltage high Input voltage low 1 3.3 V as specified in Table 1 and Table 2 12.
PAGE 4
AD1938 Parameter Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output Data Sheet Conditions Min Typ 100 0 0.375 95 Max ±0.6 100 FILTR pin FILTR pin CM pin 1.32 1.50 1.50 1.50 Min Typ 1.68 Unit dB Degrees dB dB dB Ω V V V Specifications measured at a case temperature of 125°C. Table 2.
PAGE 5
Data Sheet AD1938 DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < TC < +125°C, DVDD = 3.3 V ± 10%. Table 4. Parameter High Level Input Voltage (VIH) High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Input Leakage High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Input Capacitance Conditions/Comments MCLKI/XI pin IIH @ VIH = 2.4 V IIL @ VIL = 0.8 V IOH = 1 mA IOL = 1 mA Min 2.0 2.2 Typ Max 0.4 5 Unit V V V µA µA V V pF 0.8 10 10 DVDD − 0.60 POWER SUPPLY SPECIFICATIONS Table 5.
PAGE 6
AD1938 Data Sheet DIGITAL FILTERS Table 6. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode All modes, typical @ 48 kHz Factor Min 0.4375 fS Typ Max 21 ±0.015 24 27 0.5 fS 0.5625 fS kHz dB kHz kHz dB µs 79 22.
PAGE 7
Data Sheet AD1938 TIMING SPECIFICATIONS −40°C < TC < +125°C, DVDD = 3.3 V ± 10%. Table 7. Parameter INPUT MASTER CLOCK (MCLK) AND RESET tMH Condition Comments Min Max Unit MCLK duty cycle DAC/ADC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, and 768 fS DAC/ADC clock source = direct MCLK @ 512 fS (bypass on-chip PLL) PLL mode, 256 fS reference Direct 512 fS mode 40 60 % 40 60 % 6.9 13.8 27.
PAGE 8
AD1938 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +3.6 V ±20 mA –0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −40°C to +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 9
Data Sheet AD1938 ADC2LP ADC1RN ADC1RP ADC1LN ADC1LP CM AVDD 46 45 44 43 42 41 40 39 38 37 AGND 1 36 AGND MCLKI/XI 2 35 FILTR MCLKO/XO 3 34 AGND AGND 4 33 AVDD AVDD 5 AD1938 32 AGND OL3 6 31 OR2 OR3 TOP VIEW (Not to Scale) 7 30 OL2 OL4 8 29 OR1 OR4 9 28 OL1 PD/RST 10 27 CLATCH DSDATA4 11 26 CCLK DGND 12 25 DGND 18 19 20 21 22 23 24 ASDATA1 ABCLK ALRCLK CIN COUT DSDATA1 17 ASDATA2 16 DBCLK 15 DLRCLK 14 DSDATA2 DVDD 13 DSD
PAGE 10
AD1938 Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 In/Out I I O O O O I I I O I I O I I I I I I I I O I Data Sheet Mnemonic CCLK CLATCH OL1 OR1 OL2 OR2 AGND AVDD AGND FILTR AGND AVDD CM ADC1LP ADC1LN ADC1RP ADC1RN ADC2LP ADC2LN ADC2RP ADC2RN LF AVDD Description Control Clock Input (SPI). Latch Input for Control Data (SPI). DAC 1 Left Output. DAC 1 Right Output. DAC 2 Left Output. DAC 2 Right Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply.
PAGE 11
Data Sheet AD1938 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0 0.08 0.06 MAGNITUDE (dB) MAGNITUDE (dB) 0.04 0.02 0 –0.02 –0.04 –50 –100 –0.08 –0.10 0 05582-006 05582-003 –0.06 –150 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 12 24 36 48 FREQUENCY (kHz) FREQUENCY (Hz) Figure 3. ADC Pass-Band Filter Response, 48 kHz Figure 6. DAC Stop-Band Filter Response, 48 kHz 0.10 0 –10 –20 0.05 MAGNITUDE (dB) MAGNITUDE (dB) –30 –40 –50 –60 –70 0 –0.
PAGE 12
AD1938 Data Sheet 0.5 0 0.4 0.3 –2 MAGNITUDE (dB) 0.1 0 –0.1 –4 –6 –0.2 –0.4 –0.5 0 8 16 32 64 –10 48 05582-010 –8 –0.3 05582-009 MAGNITUDE (dB) 0.2 64 80 FREQUENCY (kHz) FREQUENCY (kHz) Figure 10. DAC Stop-Band Filter Response, 192 kHz Figure 9. DAC Pass-Band Filter Response, 192 kHz Rev.
PAGE 13
Data Sheet AD1938 THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCS) There are four ADC channels in the AD1938 configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs include on-board digital antialiasing filters with 79 dB stopband attenuation and linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes).
PAGE 14
AD1938 Data Sheet the reference clock is attenuated above a certain frequency depending on the loop filter. RESET AND POWER-DOWN The function of the RST pin sets all the control registers to their default settings. To avoid pops, reset does not power down the analog outputs. After RST is deasserted, and the PLL acquires lock condition, an initialization routine runs inside the AD1938. This initialization lasts for approximately 256 master clock cycles.
PAGE 15
Data Sheet AD1938 All digital inputs are compatible with TTL and CMOS levels. All outputs are driven from the 3.3 V DVDD supply and are compatible with TTL and 3.3 V CMOS levels. The ADC and DAC internal voltage reference (VREF) is brought out on FILTR and should be bypassed as close as possible to the chip, with a parallel combination of 10 μF and 100 nF. Any external current drawn should be limited to less than 50 μA.
PAGE 16
AD1938 Data Sheet Table 12.
PAGE 17
Data Sheet AD1938 ALRCLK ABCLK 8 ON-CHIP DAC CHANNELS DSDATA1 (TDM_IN) DAC L1 ASDATA1 (TDM_OUT) ADC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 ADC R2 AUX L1 AUX R1 4 ON-CHIP ADC CHANNELS ADC R1 ADC L2 DAC L4 DAC R4 4 AUX ADC CHANNELS AUX L2 AUX R2 32 BITS MSB DLRCLK (AUX PORT) LEFT RIGHT DSDATA2 (AUX1_IN) MSB MSB DSDATA3 (AUX2_IN) MSB MSB 05582-015 DBCLK (AUX PORT) Figure 15.
PAGE 18
AD1938 Data Sheet ALRCLK ABCLK UNUSED SLOTS DSDATA1 (TDM_IN) EMPTY ASDATA1 (TDM_OUT) ADC L1 DLRCLK (AUX PORT) EMPTY EMPTY EMPTY 4 ON-CHIP ADC CHANNELS ADC R1 ADC L2 AUXILIARY DAC CHANNELS APPEAR AT AUX DAC PORTS 8 ON-CHIP DAC CHANNELS ADC R2 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 AUXILIARY ADC CHANNELS AUX L1 AUX R1 AUX L2 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2 UNUSED SLOTS AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED LEFT RIGHT DSDATA2 (AUX1_IN)
PAGE 19
Data Sheet AD1938 There are two configurations for the ADC port to work in daisy-chain mode. The first one is with an ABCLK at 256 fS shown in Figure 21. The second configuration is shown in Figure 22. Note that in the 512 fS ABCLK mode, the ADC channels occupy the first eight slots; the second eight slots are empty. The TDM_IN of the first AD1938 must be grounded in all modes of operation.
PAGE 20
AD1938 Data Sheet DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 (IN) DAC L1 DAC R1 DAC L2 8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN DAC R2 DSDATA2 (OUT) DSDATA3 (IN) DAC L3 DAC R3 DAC L4 DAC R4 DSDATA4 (OUT) DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4 32 BITS FIRST AD193x SECOND AD193x 05582-019 MSB DSP Figure 19.
PAGE 21
Data Sheet AD1938 ALRCLK ABCLK 4 ADC CHANNELS OF SECOND IC IN THE CHAIN 4 ADC CHANNELS OF FIRST IC IN THE CHAIN ASDATA1 (TDM_OUT OF THE SECOND AD193x IN THE CHAIN) ADC L1 ADC R1 ADC L2 ADC R2 ASDATA2 (TDM_IN OF THE SECOND AD193x IN THE CHAIN) ADC L1 ADC R1 ADC L2 ADC R2 ADC L1 ADC R1 ADC L2 ADC R2 32 BITS SECOND AD193x DSP 05582-022 FIRST AD193x MSB Figure 22.
PAGE 22
AD1938 Data Sheet tDBH tDBP DBCLK tDBL tDLH tDLS DLRCLK tDDS DSDATAx LEFT-JUSTIFIED MODE MSB MSB–1 tDDH tDDS DSDATAx I2S-JUSTIFIED MODE MSB tDDH tDDS tDDS MSB LSB tDDH tDDH 05582-024 DSDATAx RIGHT-JUSTIFIED MODE Figure 24. DAC Serial Timing tABH ABCLK tABL tALH tALS ALRCLK tABDD ASDATAx LEFT-JUSTIFIED MODE MSB MSB–1 tABDD ASDATAx I2S-JUSTIFIED MODE MSB ASDATAx RIGHT-JUSTIFIED MODE MSB Figure 25. ADC Serial Timing Rev.
PAGE 23
Data Sheet AD1938 Table 13.
PAGE 24
AD1938 Data Sheet CONTROL REGISTERS DEFINITIONS The global address for the AD1938 is 0x04, shifted left one bit due to the R/W bit. All registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 14. Register Format Bit Global Address R/W Register Address Data 23:17 16 15:8 7:0 Table 15.
PAGE 25
Data Sheet AD1938 Table 17. PLL and Clock Control Register 1 Bit 0 1 2 3 7:4 Value 0 1 0 1 0 1 0 1 0000 Function PLL clock MCLK PLL clock MCLK Enabled Disabled Not locked Locked Reserved Description DAC clock source select ADC clock source select On-chip voltage reference PLL lock indicator (read-only) DAC CONTROL REGISTERS Table 18. DAC Control Register 0 Bit 0 2:1 5:3 7:6 Value 0 1 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 Function Normal Power-down 32 kHz/44.
PAGE 26
AD1938 Data Sheet Table 20. DAC Control Register 2 Bit 0 2:1 4:3 5 7:6 Value 0 1 00 01 10 11 00 01 10 11 0 1 00 Function Unmute Mute Flat 48 kHz curve 44.1 kHz curve 32 kHz curve 24 20 Reserved 16 Noninverted Inverted Reserved Description Master mute De-emphasis (32 kHz/44.1 kHz/48 kHz mode only) Word width DAC output polarity Table 21.
PAGE 27
Data Sheet AD1938 ADC CONTROL REGISTERS Table 23. ADC Control Register 0 Bit 0 1 2 3 4 5 7:6 Value 0 1 0 1 0 1 0 1 0 1 0 1 00 01 10 11 Function Normal Power down Off On Unmute Mute Unmute Mute Unmute Mute Unmute Mute 32 kHz/44.1 kHz/48 kHz 64 kHz/88.2 kHz/96 kHz 128 kHz/176.4 kHz/192 kHz Reserved Description Power-down High-pass filter ADC L1 mute ADC R1 mute ADC L2 mute ADC R2 mute Output sample rate Table 24.
PAGE 28
AD1938 Data Sheet Table 25. ADC Control Register 2 Bit 0 1 2 3 5:4 6 7 Value 0 1 0 1 0 1 0 1 00 01 10 11 0 1 0 1 Function 50/50 (allows 32, 24, 20, or 16 bit clocks (BCLKs) per channel) Pulse (32 BCLKs per channel) Drive out on falling edge (DEF) Drive out on rising edge Left low Left high Slave Master 64 128 256 512 Slave Master ABCLK pin Internally generated Rev.
PAGE 29
Data Sheet AD1938 ADDITIONAL MODES The AD1938 offers several additional modes for board level design enhancements. To reduce the EMI in board level design, serial data can be transmitted without an explicit BCLK. See Figure 27 for an example of a DAC TDM data transmission mode that does not require high speed DBCLK. This configuration is applicable when the AD1938 master clock is generated by the PLL with the DLRCLK as the PLL reference frequency.
PAGE 30
AD1938 Data Sheet APPLICATIONS CIRCUITS Typical applications circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended loop filters for LR clock and master clock as the PLL reference are shown in Figure 30. Output filters for the DAC outputs are shown in Figure 31 and Figure 32 for the noninverting and inverting cases. 120pF 5.76kΩ 5.76kΩ 3 – 1 OP275 + + 120pF 6 5 OP275 ADCxN 1nF NPO DAC OUT 100pF 5.76kΩ – 240pF NPO 4.7µF 237Ω 5.
PAGE 31
Data Sheet AD1938 OUTLINE DIMENSIONS 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY SEATING PLANE VIEW A (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH 24 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 051706-A 0.75 0.60 0.45 Figure 33.