Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) LQFP 48

8-Channel DAC with PLL and

Single-Ended Outputs, 192 kHz, 24 Bits

Data Sheet

AD1934

Rev. D Document Feedback

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FEATURES

PLL generated or direct master clock

Low EMI design

108 dB DAC dynamic range and SNR

−94 dB THD + N

Single 3.3 V supply

Tolerance for 5 V logic inputs

Supports 24 bits and 8 kHz to 192 kHz sample rates

Single-ended DAC output

Log volume control with autoramp function

SPI® controllable for flexibility

Software-controllable clickless mute

Software power-down

Right-justified, left-justified, I

S, and TDM modes

Master and slave modes up to 16-channel in/out

48-lead LQFP

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Home theater systems

Set-top boxes

Digital audio effects processors

GENERAL DESCRIPTION

The AD1934 is a high performance, single chip that provides

eight digital-to-analog converters (DACs) with single-ended

output using the Analog Devices, Inc., patented multibit sigma-

delta (Σ-Δ) architecture. An SPI port is included, allowing a

microcontroller to adjust volume and many other parameters.

The AD1934 operates from 3.3 V digital and analog supplies.

The AD1934 is available in a 48-lead (single-ended output)

L Q F P. Other members of this family include a differential DAC

output version.

The AD1934 is designed for low EMI. This consideration is

apparent in both the system and circuit design architectures.

By using the on-board PLL to derive the master clock from the

LR clock or from an external crystal, the AD1934 eliminates the

need for a separate high frequency master clock and can also be

used with a suppressed bit clock. The DACs are designed using

the latest Analog Devices continuous time architectures to further

minimize EMI. By using 3.3 V supplies, power consumption is

minimized, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

06106-001

SERIAL

DATA

PORT

PRECISION

VOLTAGE

REFERENCE

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL)

CONTROL PORT

SPI

CONTROL DATA

INPUT/OUTPUT

AD1934

DIGITAL AUDIO

INPUT/OUTPUT

SDATAIN

CLOCKS

ANALOG

AUDIO

OUTPUTS

6.144MHz

DAC

DIGITAL

FILTER

AND

VOLUME

CONTROL

Figure 1.

Summary of content (28 pages)

PAGE 1
8-Channel DAC with PLL and Single-Ended Outputs, 192 kHz, 24 Bits AD1934 Data Sheet FEATURES GENERAL DESCRIPTION PLL generated or direct master clock Low EMI design 108 dB DAC dynamic range and SNR −94 dB THD + N Single 3.
PAGE 2
AD1934 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital-to-Analog Converters (DACs) .................................... 13 Applications ....................................................................................... 1 Clock Signals ............................................................................... 13 General Description ....................................................................
PAGE 3
Data Sheet AD1934 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply Voltages (AVDD, DVDD) Temperature Range 1 Master Clock Input Sample Rate Measurement Bandwidth Word Width Load Capacitance (Digital Output) Load Current (Digital Output) Input Voltage HI Input Voltage LO 1 3.3 V As specified in Table 1 and Table 2 12.
PAGE 4
AD1934 Data Sheet Specifications measured at 125°C (case). Table 2.
PAGE 5
Data Sheet AD1934 POWER SUPPLY SPECIFICATIONS Table 5. Parameter SUPPLIES Voltage Digital Current Normal Operation Power-Down Analog Current Normal Operation Power-Down DISSIPATION Operation All Supplies Digital Supply Analog Supply Power-Down, All Supplies POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins Test Conditions/Comments Min Typ Max Unit DVDD AVDD MCLK = 256 fS fS = 48 kHz fS = 96 kHz fS = 192 kHz fS = 48 kHz to 192 kHz 3.0 3.0 3.3 3.3 3.6 3.6 V V 56 65 95 2.
PAGE 6
AD1934 Data Sheet DIGITAL FILTERS Table 6.
PAGE 7
Data Sheet AD1934 Parameter DAC SERIAL PORT tDBH tDBL tDLS tDLH tDLS tDDS tDDH AUXTDM SERIAL PORT tABH tABL tALS tALH tALS tDDS tDDH Condition AUXTDMBCLK high AUXTDMBCLK low AUXTDMLRCLK setup AUXTDMLRCLK hold AUXTDMLRCLK skew DSDATA setup DSDATA hold AUXILIARY INTERFACE tDXDD tXBH tXBL tDLS tDLH AUXDATA delay AUXBCLK high AUXBCLK low AUXLRCLK setup AUXLRCLK hold DBCLK high DBCLK low DLRCLK setup DLRCLK hold DLRCLK skew DSDATA setup DSDATA hold Comments See Figure 16 Slave mode Slave mode To DBCLK ri
PAGE 8
AD1934 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range THERMAL RESISTANCE Rating −0.3 V to +3.6 V −0.3 V to +3.6 V ±20 mA −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −40°C to +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 9
Data Sheet AD1934 LF NC NC NC NC NC NC NC NC CM AVDD 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 MCLKI/XI 2 35 AGND FILTR MCLKO/XO 3 34 AGND AVDD AGND 4 33 AVDD 5 AD1934 32 AGND OL3 6 31 OR2 OR3 TOP VIEW (Not to Scale) 7 OL4 8 OR4 9 28 OL1 PD/RST 10 27 CLATCH SINGLE-ENDED OUTPUT 30 OL2 29 OR1 17 18 19 20 21 22 23 24 NC AUXTDMBCLK AUXTDMLRCLK CIN COUT 16 AUXDATA1 15 DLRCLK 14 DSDATA1 NC = NO CONNECT 13 DBCLK DGND DSDATA
PAGE 10
AD1934 Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 to 46 47 48 Input/Output I I O O O O I I I O I I O O I Data Sheet Mnemonic CCLK/SCL CLATCH/ADR1 OL1 OR1 OL2 OR2 AGND AVDD AGND FILTR AGND AVDD CM NC LF AVDD Description Control Clock Input (SPI). Latch Input for Control Data (SPI). DAC 1 Left Output. DAC 1 Right Output. DAC 2 Left Output. DAC 2 Right Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Analog Ground. Voltage Reference Filter Capacitor Connection.
PAGE 11
Data Sheet AD1934 TYPICAL PERFORMANCE CHARACTERISTICS 0.06 0 MAGNITUDE (dB) MAGNITUDE (dB) 0.04 0.02 0 –0.02 –50 –100 –150 0 8 16 24 FREQUENCY (kHz) 0 06106-004 –0.06 24 48 72 96 FREQUENCY (kHz) 06106-007 –0.04 Figure 6. DAC Stop-Band Filter Response, 96 kHz Figure 3. DAC Pass-Band Filter Response, 48 kHz 0.5 0 0.4 0.2 MAGNITUDE (dB) MAGNITUDE (dB) 0.3 –50 –100 0.1 0 –0.1 –0.2 –0.3 –0.4 12 24 36 48 FREQUENCY (kHz) –0.
PAGE 12
AD1934 Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTERS (DACs) The AD1934 DAC channels are arranged as single-ended, four stereo pairs giving eight analog outputs for minimum external components. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode).
PAGE 13
Data Sheet AD1934 SERIAL CONTROL PORT The AD1934 has an SPI control port that permits programming and reading back of the internal control registers for the ADCs, DACs, and clock system. A standalone mode is also available for operation without serial control; standalone is configured at reset by connecting CIN, CCLK, and CLATCH to ground. In standalone mode, all registers are set to default, except the internal MCLK enable, which is set to 1.
PAGE 14
AD1934 Data Sheet POWER SUPPLY AND VOLTAGE REFERENCE The AD1934 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 μF should also be provided on the same PC board as the DAC.
PAGE 15
Data Sheet AD1934 Table 12.
PAGE 16
AD1934 Data Sheet DAISY-CHAIN MODE The dual-line, DAC TDM mode can also be used to send data at a 192 kHz sample rate into the AD1934, as shown in Figure 14. The I/O pins of the serial ports are defined according to the serial mode selected. See Table 13 for a detailed description of the function of each pin. See Figure 18 for a typical AD1934 configuration with two external stereo DACs. Figure 15 and Figure 16 show the serial mode formats.
PAGE 17
Data Sheet AD1934 DLRCLK DBCLK DSDATA1 DAC L1 DAC R1 DAC L2 DAC R2 DSDATA2 DAC L3 DAC R3 DAC L4 DAC R4 06106-058 32 BITS MSB Figure 14.
PAGE 18
AD1934 Data Sheet tDBH DBCLK tDBL tDLH tDLS DLRCLK tDDS DSDATA LEFT-JUSTIFIED MODE MSB MSB–1 tDDH tDDS DSDATA I2S-JUSTIFIED MODE MSB tDDH tDDS MSB LSB tDDH tDDH 06106-014 tDDS DSDATA RIGHT-JUSTIFIED MODE Figure 16. DAC Serial Timing tABH AUXTDMBCLK tABL tALH tALS AUXTDMLRCLK DSDATA1 I2S-JUSTIFIED MODE MSB MSB–1 MSB DSDATA1 RIGHT-JUSTIFIED MODE MSB Figure 17. AUXTDM Serial Timing Rev.
PAGE 19
Data Sheet AD1934 Table 13.
PAGE 20
AD1934 Data Sheet CONTROL REGISTERS DEFINITIONS The global address for the AD1934 is 0x04, shifted left 1 bit due to the R/W bit. All registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 14. Register Format Bit Global Address R/W Register Address Data 23:17 16 15:8 7:0 Table 15.
PAGE 21
Data Sheet AD1934 Table 17. PLL and Clock Control 1 Bit 0 1 2 3 7:4 Value 0 1 0 1 0 1 0 1 0000 Function PLL clock MCLK PLL clock MCLK Enabled Disabled Not locked Locked Reserved Description DAC clock source select Clock source select On-chip voltage reference PLL lock indicator (read-only) DAC CONTROL REGISTERS Table 18. DAC Control 0 Bit 0 2:1 5:3 7:6 Value 0 1 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 Function Normal Power-down 32 kHz/44.1 kHz/48 kHz 64 kHz/88.
PAGE 22
AD1934 Data Sheet Table 20. DAC Control 2 Bit 0 2:1 4:3 5 7:6 Value 0 1 00 01 10 11 00 01 10 11 0 1 00 Function Unmute Mute Flat 48 kHz curve 44.1 kHz curve 32 kHz curve 24 20 Reserved 16 Noninverted Inverted Reserved Description Master mute De-emphasis (32 kHz/44.1 kHz/48 kHz mode only) Word width DAC output polarity Table 21.
PAGE 23
Data Sheet AD1934 AUXILIARY TDM PORT CONTROL REGISTERS Table 23. Auxiliary TDM Control 0 Bit 1:0 4:2 6:5 7 Value 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 0 1 Function 24 20 Reserved 16 1 0 8 12 16 Reserved Reserved Reserved Reserved Reserved DAC aux mode Reserved Latch in midcycle (normal) Latch in at end of cycle (pipeline) Description Word width SDATA delay (BCLK periods) Serial format BCLK active edge (TDM in) Table 24.
PAGE 24
AD1934 Data Sheet DLRCLK 32 BITS INTERNAL DBCLK DSDATA DLRCLK 06106-059 INTERNAL DBCLK TDM-DSDATA Figure 19. Serial DAC Data Transmission in TDM Format Without DBCLK (Applicable Only If PLL Locks to DLRCLK) DLRCLK DBCLK 06106-060 DATA MUST BE VALID AT THIS BCLK EDGE MSB DSDATA 2 Figure 20. I S Pipeline Mode in DAC Serial Data Transmission (Applicable in Stereo and TDM Useful for High Frequency TDM Transmission) Rev.
PAGE 25
Data Sheet AD1934 APPLICATION CIRCUITS LRCLK 2 270pF NPO MCLK + 1 604Ω 4.7µF 4.99kΩ + 3.3nF NPO OP275 – AUDIO OUTPUT 49.9kΩ 4.99kΩ 5.6nF 39nF Figure 22. Typical DAC Output Filter Circuit (Single-Ended, Noninverting) 390pF 2.2nF 562Ω 3.32kΩ AVDD2 3 4.75kΩ 4.75kΩ AVDD2 Figure 21. Recommended Loop Filters for LRCLK or MCLK PLL Reference 11kΩ DAC OUT 68pF NPO 2 11kΩ 3.01kΩ CM 270pF NPO 0.1µF 3 – OP275 + 1 604Ω 4.7µF + 2.2nF NPO AUDIO OUTPUT 49.9kΩ Figure 23.
PAGE 26
AD1934 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 7.20 7.00 SQ 6.80 TOP VIEW 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY SEATING PLANE (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH VIEW A 24 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 051706-A 1.45 1.40 1.35 Figure 24.
PAGE 27
Data Sheet AD1934 NOTES Rev.