AMN12310 WHDITM Receiver Module Datasheet Version 0.5 Version 0.
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Revision History Revision History Version Date Description 0.1 - Initial Release 0.2 15.6.08 Revision 0.3 20.7.08 Board Mechanical size Reset and Wake-up Timer modified RF frame modified Power switch on RF removed Operating Conditions and Electrical Characteristics modified AMN11310 Block Diagram modified Unhide Certification & Compliance Power requirements Mini-MAC changed to MAC.
Table of Contents S S Table of Contents Important Notice......................................................................................................2 Revision History ......................................................................................................3 Table of Contents ....................................................................................................4 List of Figures .............................................................................................
Table of Contents 2 3.4 3.5 3.3.1 I S Bus Specification ....................................................................................................................... 18 Management Buses and Connectors ...................................................................................................21 3.4.1 Two-Wire Serial Bus Interface......................................................................................................... 21 3.4.2 Interrupts....................................
List of Figures List of Figures Figure 1: AMN12310 Block Diagram....................................................................................................................... 11 Figure 2: WHDI Baseband Receiver Chipset .......................................................................................................... 12 Figure 3: Video Data Receiver Path........................................................................................................................
List of Tables Table 13: Electrical Characteristics over Recommended Range of Supply Voltage and Operating Conditions........................................................................................................................................... 30 Table 14: Digital Layout Recommendation ............................................................................................................. 32 Version 0.
Introduction Chapter 1 Introduction TM The AMN12310 is the second generation of WHDI receiver board. It is based on AMIMON's WHDI receiver chipset: the AMN2210 baseband receiver and the AMN3210 RFIC receiver. TM The AMN12310 WHDI wireless receiver module, together with the AMN11310 wireless transmitter module, presents the ultimate solution for converting any High Definition (HD) system into a wireless one.
Introduction • Small mechanical footprint: • • With PCB integrated antennas RF characteristics: MIMO technology, using 5GHz unlicensed band, 18MHz bandwidth. Coexists with 802.11a/n and 5.8GHz cordless devices. Support for Automatic Transmission Power Control (ATPC). No line of sight needed between transmitter and receiver. It has a range of over 30 meters, suitable for almost any room. 14mW typical transmission power of the uplink channel.
Introduction • Caution: The module should be positioned so that personnel in the area for prolonged periods may safely remain at least 20 cm (8 in) in an uncontrolled environment from the module. Version 0.
Overview Chapter 2 Overview The AMN12310 WHDI Video Display Unit (VDU) is designed to be at the receiver end of the WHDI downstream. The AMN12310 receives wireless downstream transmission, demodulates it and regenerates the video, audio and control content transmitted by the AMN11310 WHDI transmitter. The receiver works at the 5GHz unlicensed band. Figure 1 displays a block diagram of the AMN12310.
Overview The main building blocks of the AMN12310 are as follows: • AMN2210 WHDI Baseband Receiver, as briefly described on page 12 • STM32F MAC µController, as briefly described on page 12 • AMN3210 WHDI TM 5GHz Transceiver, as briefly described on page 13 • Power Amplifier (PA), as briefly described on page 13 • Board Connector (WHDI • Clock enable switch for input 40M clock to AMN2110, as described on page 13 TM Connector), as described on page 13 • 40MHz Crystal Oscillator, as described
Overview 2.3 AMN3210 WHDITM 5GHz Transceiver The VDU uses AMN3210 WHDI receiver chip. The AMN3210 is a fully integrated Zero-IF MIMO receiver specifically designed for WHDI applications using OFDM modulation for single-band 4.9GHz to 5.9GHz.
Overview 2.7 CY22150 External Video PLL An external PLL is used for re-generating the video clock. The PLL receives a lower speed clock (generally limited to 10 MHz), which is generated inside the AMN2210 according to the video parameters. The PLL multiplies the clock to the desired speed dictated by the incoming video format (for example: 74.25Mhz for 720p or 1080i). Version 0.
Interfaces Chapter 3 Interfaces 3.1 Video Data Input and Conversions Figure 3: Video Data Receiver Path Figure 3 shows the basic control over the video data output. Essentially the receiver mirrors the video format of the transmitter end and so most of the configurations are done on the transmitter end. The video output data is uncompressed digital video up to 3*10 bits in width.
Interfaces Common Video Output Format Table 2 lists the common supported video output resolutions. Table 2: Common Supported Video Input Resolutions Color Space Input Pixel Clock (MHz) Video Format Bus Width 480i 480p XGA 720p 1080i 4:4:4 24 27 27 65 74.25 74.
Interfaces EDGE = 0 EDGE = 1 3.2.1.1 Timing Diagram Figure 4: Timing Diagram 3.3 Audio Data Capture AMN12310 audio processing logic block receives the audio stream from the WHDI wireless link and regenerates the appropriate clock and data. If the transmitter end was configured to SPDIF audio interface, then the audio is 2 output on the receiver side through the SPDIF. The same is true for the I S interface.
Interfaces 3.3.1 I2S Bus Specification 2 The AMN12310 supports a standardized communication structure inter-IC sound (I S) bus. As shown in Figure 5, the bus has three lines: continuous serial clock (SCK), word select (WS) and serial data (SD). In addition, it has a MCLK signal which is synchronized to and a multiple of the WS. The external device generating SCK and WS is the AMN12310.
Interfaces 3.3.1.2 Timing Requirements Table 5: Audio Interface Output Timing Symbol Parameter MIN TYP MAX Units TSCKCYC SCK period 325 976 ns TSCKFREQ SCK frequency 1.024 3.072 MHz TSCKDUTY SCK duty cycle 40 60 % TDCKPDR Propagation delay after SCK rising edge 25 ns TDCKPDF Propagation delay after SCK falling edge 25 ns 3.3.1.
Interfaces Table 6: MCLK timing. Symbol Parameter MIN TYP MAX Units TMCKCYC MCK period 244.14 81.38 ns TMCKFREQ MCK frequency 4.096* 12.288** MHz TMCKDUTY MCK duty cycle 40 60 % TDCKPDR Propagation delay after MCK rising edge 25 ns TDCKPDF Propagation delay after MCK falling edge 25 ns TJITTER-CYC- Cycle-to-cycle jitter*** 5 ns CYC * The minimum frequency is obtained by using the minimum audio sampling frequency of 32 KHz and the minimum clock rate multiplication of 128.
Interfaces 3.4 Management Buses and Connectors 3.4.1 Two-Wire Serial Bus Interface The WHDI application observes and controls the AMN12310 via a Two-Wire interface and an interrupt line connecting the application microcontroller and the AMN12310 MAC microcontroller. The protocol of the TwoWire-bus for the WHDI application / MAC interface is described in the following sections.
Interfaces 3.4.1.3 MAC uC Write Operation Figure 8 demonstrates a write transaction which sends 2 data bytes and which ends with the master stop bit. Each write transaction sends one or more data bytes to the MAC, beginning at an explicit 2 bytes long address. Multiple data bytes may be written as the MAC stores the received register data until the master sends a stop bit. The MAC updates the register value upon a successful termination of a write transaction. Two-Wire Slave address START I6 I5 ...
Interfaces 3.4.3 WHDI Module Configuration In order to distinguish between boards and by the SW, there is an on board ID that can be read by the STM32F. WHDI_MODULE_ID (Details) Amimon Project Part Number Tx="0", Rx="1" Interrupt Polarity: "0"=falling, "1"=rising I2C Address: "00"=0x62, "01"=0x72, 10"=0x60, 11"=0x70 Comments MODULE_ID [7] [6] [5] [4] [3] [2] [1] [0] AMN11310 Rev. 2.0 1 0 0 0 0 0 0 0 AMN12310 Rev. 2.0 1 0 1 0 0 0 1 0 3.
Interfaces The following table specifies the timing parameters Table 8: Reset Timing Requirements Symbol Parameter Condition TRST-CLK Time from assertion of the HW reset until valid clock is generated TST,RST Time from assertion of the HW reset until the STM32F completes the internal initialization TINIT Time from assertion of the HW/SW reset until the AMN2210 completes the internal initialization MIN TYP MAX Units 40 MHz clock is valid – few us after power up 300 ns Power is stable 4.
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WHDI Connector Pins Chapter 4 WHDI Connector Pins 4.
WHDI Connector Pins 4.2 Connector Schematics Figure 12: WHDI Connector Version 0.
WHDI Connector Pins 4.3 Pin List Table 10: Rx WHDI Connector Pin List Pin Number Signal Pin Number Signal Pin Number Signal Pin Number Signal 1 3.3V 2 3.3V 41 WHDI_D26 42 WHDI_D27 3 3.3V 4 3.3V 43 WHDI_D24 44 WHDI_D25 5 3.3V 6 3.3V 45 WHDI_D22 46 WHDI_D23 7 3.3V 8 3.3V 47 WHDI_D20 48 WHDI_D21 9 3.3V 10 3.3V 49 WHDI_D18 50 WHDI_D19 11 3.3V 12 3.3V 51 WHDI_D16 52 WHDI_D17 13 3.3V 14 3.
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Electrical Specifications Chapter 5 Electrical Specifications 5.1 Operating Conditions and Electrical Characteristics The following tables describe the operating conditions and electrical characteristics required for working with the AMN12310. Table 11: Absolute Maximum Ratings over Operating Case Temperature Range Supply input-voltage range, VI 0 to 3.6 V Ambient temperature range 0°C to 70°C Storage temperature range, Tstg -40°C to 125°C Table 12: Recommended Operating Conditions Parameter Min.
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Design Guidelines Chapter 6 Design Guidelines 6.1 Digital Layout Recommendation To better understand the layout guidelines, please refer to the AMN12310 Schematics which are part of the HDK package. 6.1.1 Stack Up Recommended stack up for six layers design: • Total thickness: 1.15mm • Tolerance thickness: 10% Table 14: Digital Layout Recommendation Lay. No. 1 Layer Name Layer Stack-up Component side 1-1.
Design Guidelines 6.1.2 • General Guidelines Keep traces as short as possible. • Traces should be routed over full solid reference plans. • Sensitive lines like reset and clocks should be routed with special care. • These lines should be routed over full solid power plans (ground or power). Traces should be routed at least two times the trace width away from other lines in the same routing layer. Place a series resistor ~30 ohm at the clock source.
Design Guidelines 6.3 Test Points and Jumpers Reference Name Type Functionality Reference Name Type Functionality TP1 SMD RXHP_3 TP28 TH 3.3V TP2 SMD RXHP_4 TP29 SMD 3.3V TP3 SMD RFSPI_CLK TP30 SMD MAC_TRST TP4 SMD RFSPI_DOUT TP31 SMD MAC_TDI TP5 SMD RSSI_DETECT TP32 SMD MAC_TCK TP6 SMD LD TP33 SMD GND TP7 SMD SPI_CS TP34 SMD GND TP8 TH GND TP35 SMD 3.
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Mechanical Dimensions Chapter 7 Mechanical Dimensions The following shows the mechanical dimensions for the AMN12310: Figure 13: Mechanical Dimensions Top View Version 0.
Mechanical Dimensions Figure 14: Mechanical Dimensions Bottom View Version 0.
Mechanical Dimensions 7.1 RF Shield frame and cover Figure 15: RF-Shield Frame Figure 16: RF-Shield Cover Version 0.
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