AMN12100 WHDITM Receiver Module Datasheet Version 1.0 Version 1.
Version 1.
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Table of Contents Table of Contents Chapter 1, Introduction ................................................................................... 1 1.1 Features......................................................................................................................................................... 1 Chapter 2, Overview........................................................................................ 3 2.1 2.2 2.3 2.4 2.5 2.6 2.7 AMN2210 WHDI Baseband Receiver .........................
Table of Contents Chapter 6, Design Guidelines ........................................................................ 21 6.1 Digital Layout Recommendation............................................................................................................... 21 6.1.1 Stuck Up ..................................................................................................................................................... 21 6.1.2 General Guidelines................................................
List of Figures List of Figures Figure 1: AMN12100 Block Diagram......................................................................................................................... 3 Figure 2: WHDI Baseband Receiver Chipset ............................................................................................................ 4 Figure 3: Video Data Receiver Path..........................................................................................................................
Revision History Revision History Version Date 0.1 - 0.5 19-Jun-07 Description Initial Release Added Design Guidelines Updated Reset Mechanism Updated Two-Wire Serial Bus Protocol Definition 0.6 19-June-07 1.0 06-Nov-07 Added Mechanical Dimensions Added FCC certification and compliance Added Table 2 Updated Table 4 Version 1.
Revision History Version 1.
Introduction Chapter 1 Introduction The AMN12100 is the first generation of WHDITM receiver module based on AMIMON's AMN2210 baseband receiver chip. The AMN12100 WHDITM wireless receiver module, together with the AMN11100 WHDITM wireless transmitter module, presents the ultimate solution for converting any High Definition (HD) system into a wireless one. This add-on module enables wireless A/V applications that can easily fit into the living room and eliminate traditional A/V wiring.
Introduction • Small mechanical footprint: With PCB integrated antennas. Optional external antennas. • RF characteristics: MIMO technology, using 5GHz unlicensed band, 18MHz bandwidth. Coexists with 802.11a/n and 5.8GHz cordless devices. Support for Automatic Transmission Power Control (ATPC). No line of sight needed between transmitter and receiver. It has a range of over 30 meters, suitable for almost any room. 14mW typical transmission power. Maximum 45mW transmission power.
Overview Chapter 2 Overview The AMN12100 WHDI Video Display Unit (VDU) is designed to be at the receiver end of the WHDI downstream. The AMN12100 receives wireless downstream transmission, demodulates it and regenerates the video, audio and control content transmitted by the AMN11100 WHDI transmitter. The receiver works at the 5GHz unlicensed band. Figure 1 displays a block diagram of the AMN12100.
Overview The main building blocks of the AMN12100 are as follows: • AMN2210 WHDI Baseband Transmitter, as briefly described on page 4 • LPC2103 Mini-MAC µController, as briefly described on page 4 • MAX2828 5GHz (802.11a) Transceiver, as briefly described on page 5 • Power Amplifier (PA), as briefly described on page 5 • Board Connector (WHDITM Connector), as described on page 5 • E2PROM, as described on page 5 • 40MHz Clock Gen, as described on page 5 2.
Overview 2.3 MAX2828 5GHz (802.11a) Transceiver The VDU has five MAX2828 chips embedded in it. The MAX2828 is a single-chip, RF transceiver IC designed specifically for single-band 4.9GHz to 5.875GHz, OFDM, 802.11 WLAN applications. It includes all the circuitry necessary to implement the RF transceiver function, providing a fully integrated receive path, transmit path, VCO, frequency synthesizer and baseband/control interface.
Overview Version 1.
Interfaces Chapter 3 Interfaces 3.1 Video Data Input and Conversions Figure 3: Video Data Receiver Path Figure 3 shows the basic control over the video data output. Essentially the receiver mirrors the video format of the transmitter end and so most of the configurations are done on the transmitter end. The video output data is uncompressed digital video up to 3*10 bits in width.
Interfaces Common Video Output Format Table 1 lists the common supported video output resolutions. Table 1: Common Supported Video Input Resolutions Input Pixel Clock (MHz) Color Space Video Format Bus Width 480i 480p XGA 720p 1080i RGB/YCbCr 4:4:4 24 27 27 65 74.25 74.
Interfaces EDGE = 0 EDGE = 1 3.1.1.2 Timing Diagram Figure 4: Timing Diagram 3.2 Audio Data Capture AMN12100 audio processing logic block receives the audio stream from the WHDI wireless link and regenerates the appropriate clock and data. If the transmitter end was configured to SPDIF audio interface, then the audio is output on the receiver side through the SPDIF. The same is true for the I2S interface.
Interfaces 3.2.1 I2S Bus Specification The AMN12100 supports a standardized communication structure inter-IC sound (I2S) bus. As shown in Figure 5, the bus has three lines: continuous serial clock (SCK), word select (WS) and serial data (SD). In addition, it has a MCLK signal which is synchronized to and a multiple of the WS. The external device generating SCK and WS is the AMN12100.
Interfaces 3.2.1.2 Timing Requirements Table 4: Audio Interface Ouput Timing Symbol Parameter MAX Units 325 976 ns SCK frequency 1.024 3.072 MHz SCK duty cycle 40 60 % Propagation delay after SCK rising edge 25 ns Propagation delay after SCK falling edge 25 ns TSCKCYC SCK period TSCKFREQ TSCKDUTY TDCKPDR TDCKPDF MIN TYP EDGE = 0 EDGE = 1 3.2.1.3 Timing Diagram Figure 6: I2S Output Timings Version 1.
Interfaces 3.3 Management Buses and Connectors 3.3.1 Two-Wire Serial Bus Interface The WHDI application observes and controls the AMN12100 via a Two-Wire interface and an interrupt line connecting the application microcontroller and the AMN12100 MiniMAC microcontroller. The protocol of the TwoWire-bus for the WHDI application / MiniMAC interface is described in the following sections.
Interfaces 3.3.1.3 MiniMAC uC Read Operation This operation reads from a specific 2- byte address. The read transaction is divided into two parts. In the first part, the Two-Wire master sends a write command to the slave containing only the required start address. (The address is always 2 bytes long.) In the second part, multiple bytes may be read from consecutive addresses. The MiniMAC puts the appropriate data on the Two-Wire bus and the internal address is automatically incremented.
Interfaces 3.4 Reset and Wake-up Timer The AMN12100 has one hard RESET input pin connected directly to the AMN2110 and through a MicroPower circuit to the LPC2103 uC, as described in Figure 10. Upon power up, the MicroPower circuit asserts the uC reset pin for about 150msec.
WHDI Connector Pin-Outs Chapter 4 WHDI Connector Pin-Outs 4.
WHDI Connector Pin-Outs 4.2 Connector Schematics WHDI Connector 3.3V Note: For AMN11100 and AMN12100 boards connect to 3.3V power rail 3.
WHDI Connector Pin-Outs 4.3 Pin List Table 7: Rx WHDI Connector Pin List Pin Number Signal Pin Number Signal Pin Number Signal 1 3.3V 31 1.8V(*) 61 D12 2 3.3V 32 1.8V(*) 62 D7 3 3.3V 33 RESET 63 D10 4 3.3V 34 SCL 64 D5 5 3.3V 35 INT 65 D8 6 3.3V 36 SDA 66 D3 7 3.3V 37 N.C 67 D6 8 3.3V 38 MUTE 68 D1 9 3.3V_OR_5V(**) 39 D28 69 D4 10 3.3V_OR_5V(**) 40 D29 70 D0 11 3.3V_OR_5V(**) 41 D26 71 D2 12 3.3V_OR_5V(**) 42 D27 72 DE 13 3.
WHDI Connector Pin-Outs Version 1.
Electrical Specifications Chapter 5 Electrical Specifications 5.1 Operating Conditions and Electrical Characteristics The following tables describe the operating conditions and electrical characteristics required for working with the AMN12100. Table 8: Absolute Maximum Ratings over Operating Case Temperature Range Supply input-voltage range, VI 0 to 3.6 V Ambient temperature range 0°C to 70°C Storage temperature range, Tstg -40°C to 125°C Table 9: Recommended Operating Conditions Parameter Min.
Electrical Specifications Version 1.
Design Guidelines Chapter 6 Design Guidelines 6.1 Digital Layout Recommendation To better understand the layout guidelines, please refer to the AMN12100 schematics which are part of the HDK package. 6.1.1 Stuck Up Recommended stuck up for 10 layers design: • Total thickness 1.6mm • Tolerance: 10% Table 11: Digital Layout Recommendation Conductor Width [mil] StuckUp thickness Title Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Des. Before Scale Oz/mil 0.
Design Guidelines 6.1.2 General Guidelines • Keep traces as short as possible. • Traces should be routed over full solid reference plans. • Sensitive lines like reset and clocks should be routed with special care. These lines should be routed over full solid power plans (ground or power). Traces should be routed at least 2 times the trace width away from other lines in the same routing layer. Place a series resistor ~30 ohm at the clock source.
Design Guidelines • Digital: 1.2 Volt: Pins names: VDD_0 to VDD_9 (total 10 pins) 3.3 Volt: Pins: VDD_IO_0 to VDD_IO_8 (total 9 pins) 6.2 RF Design Recommendation 6.2.1 RF Components All passive components must have compatible performance with components used in the Amimon reference design. 6.2.2 Power Management The power management is divided such that each channel has an independent filtered power supply of 2.85Vdc. Figure 1 shows the power scheme of the RF section of the receiver. 3.
Design Guidelines Version 1.
Mechanical Dimensions Chapter 7 Mechanical Dimensions The following shows the mechanical dimensions for the AMN12100: Figure 13: Mechanical Dimensions Version 1.
Mechanical Dimensions Version 1.
