AMN11100 WHDITM Transmitter Module Datasheet Version 1.0 Version 1.
Version 1.
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Table of Contents Table of Contents Chapter 1, Introduction .................................................................................. 1 1.1 Features......................................................................................................................................................... 1 Chapter 2, Overview........................................................................................ 3 2.1 2.2 2.3 2.4 2.5 2.6 2.7 AMN2110 WHDI Baseband Transmitter........................
Table of Contents Chapter 6, Design Guidelines ........................................................................ 21 6.1 Digital Layout Recommendation............................................................................................................... 21 6.1.1 Stuck up...................................................................................................................................................... 21 6.1.2 General Guidelines................................................
List of Figures List of Figures Figure 1: AMN11100 Block Diagram .....................................................................................................................................3 Figure 2: WHDI Baseband Transmitter Chipset ..................................................................................................................4 Figure 3: Video Data Processing Path ..................................................................................................................
Revision History Revision History Version Date 0.1 - 0.5 19-Jun-07 Description Initial Release Added Design Guidelines Updated Reset Mechanism Updated Two-Wire Serial Bus Protocol Definition 0.6 19-June-07 1.0 06-Nov-07 Added Mechanical Dimensions Added FCC certification and compliance Added Table 2 Updated Table 4 Version 1.
Revision History Version 1.
Introduction Chapter 1 Introduction The AMN11100 is the first generation of WHDITM transmitter board based on AMIMON's AMN2110 baseband transmitter chip. The AMN11100 WHDITM wireless transmitter module, together with the AMN12100 wireless receiver module, presents the ultimate solution for converting any High Definition (HD) system into a wireless one. This add-on module enables wireless A/V applications that easily fit into the living room and eliminate traditional A/V wiring.
Introduction • RF characteristics: MIMO technology, using 5GHz unlicensed band, 18MHz bandwidth. Coexists with 802.11a/n and 5.8GHz cordless devices. Support for Automatic Transmission Power Control (ATPC). No line of sight needed between transmitter and receiver. It has a range of over 30 meters, suitable for almost any room. 14mW typical transmission power. Maximum 45mW transmission power. • Power requirements: 3.3V (±5%), ~5.
Overview Chapter 2 Overview The AMN11100 WHDI Video Source Unit (VSU) is designed to modulate and transmit downstream video and audio content over the wireless medium and receive a control channel over the wireless upstream. The modulation uses 18MHz bandwidth and is carried over the 5GHz unlicensed band. Figure 1 displays a block diagram of the AMN11100. The inputs to the VSU are digital uncompressed video, digital audio and control, all via the WHDI connector.
Overview The main building blocks of the AMN11100 are as follows: • AMN2110 WHDI Baseband Transmitter, as briefly described on page 4 • LPC2103 Mini-MAC µController, as briefly described on page 4 • MAX2828 5GHz (802.11a) Transceiver, as briefly described on page 5 • Power Amplifier (PA), as briefly described on page 5 • Board Connector (WHDI Connector), as described on page 5 • E2PROM, as described on page 5 • 40MHz Clock Gen, as described on page 5 2.
Overview 2.3 MAX2828 5GHz (802.11a) Transceiver The VSU has four MAX2828 chips embedded in it. The MAX2828 is a single-chip, RF transceiver IC designed specifically for single-band 4.9GHz to 5.875GHz, OFDM, 802.11 WLAN applications. It includes all the circuitry necessary to implement the RF transceiver function, providing a fully integrated receive path, transmit path, VCO, frequency synthesizer and baseband/control interface.
Overview Version 1.
Interfaces Chapter 3 Interfaces 3.1 Video Data Input and Conversions Figure 3: Video Data Processing Path Figure 3 shows the stages for processing video data through the AMN2110. The HSYNC and the VSYNC input signals are mandatory. The DE input signal is optional and can be created with the DE generator using the HSYNC and the VSYNC pulses. The video input data is uncompressed digital video up to 3*10 bits in width. Important: When connected to a 3*8 bits source, connect the appropriate LSBs to GND.
Interfaces Common Video Input Format Table 1 describes the common supported video input resolutions. Table 1: Common Supported Video Input Resolutions Input Pixel Clock (MHz) Color Space Video Format Bus Width 480i 480p XGA 720p 1080i RGB/YCbCr 4:4:4 24 27 27 65 74.25 74.25 3.1.
Interfaces 3.1.2.2 Timing Diagram Figure 4: Timing Diagram 3.2 Audio Data Capture AMN11100 transports an explicit audio master clock with appropriate data-over-the-wireless link. No constraints exist for a coherent video and audio clock, where coherent means that the audio and the video clock must have been created from the same clock source. The AMN11100 can accept digital audio from either SPDIF or I2S inputs.
Interfaces 3.2.1 I2S Bus Specification The AMN11100 supports a standardized communication structure inter-IC sound (I2S) bus. As shown in Figure 5, the bus has three lines: continuous serial clock (SCK), word select (WS) and serial data (SD). The external device generating SCK and WS is the audio source. Figure 5: I2S Simple System Configurations and Basic Interface Timing The AMN11100 supports an I2S format of up to 32 bits for each channel (left and right).
Interfaces 3.2.1.2 Timing Diagram TSCKCYC T SCKDUTY SCK 50% TDCKSETUP TDCKHOLD SD ,WS Figure 6: I2S Input Timings 3.2.2 S/PDIF Bus 3.2.2.1 Timing Requirements The AMN11100 does not require the SPDIF clock. The clock is produced internally by sampling the SPDIF data input at a high clock rate and processing it. Table 5: Audio Interface Timing Requirements Symbol Parameter MAX Units TSPCYC SPDIF data sampling rate Condition MIN 162 TYP 488 ns TSPFREQ SPDIF data sampling freq 2.048 6.
Interfaces 3.3 Management Buses and Connectors 3.3.1 Two-Wire Serial Bus Interface The WHDI application observes and controls the AMN11100 via a Two-Wire interface and an interrupt line connecting the application microcontroller and the AMN11100 MiniMAC microcontroller. The protocol of the TwoWire bus for the WHDI application / MiniMAC interface is described in the following sections.
Interfaces 3.3.1.3 MiniMAC uC Read Operation This operation reads from a specific 2-byte address. The read transaction is divided into two parts. In the first part, the Two-Wire master sends a write command to the slave containing only the required start address. (The address is always 2 bytes long.) In the second part, multiple bytes may be read from consecutive addresses. The MiniMAC puts the appropriate data on the Two-Wire bus and the internal address is automatically incremented.
Interfaces 3.4 Reset and Wake-up Timer The AMN11100 has one hard RESET input pin connected directly to the AMN2110 and through a MicroPower circuit to the LPC2103 uC, as described in Figure 10. Upon power up, the MicroPower circuit asserts the uC reset pin for about 150msec.
WHDI Connector Pin-Outs Chapter 4 WHDI Connector Pin-Outs 4.
WHDI Connector Pin-Outs 4.2 Connector Schematics WHDI Connector 3.3V Note: For AMN11100 and AMN12100 boards connect to 3.3V power rail 3.
WHDI Connector Pin-Outs 4.3 Pin List Table 8: Tx WHDI Connector Pin List Pin Number Signal Pin Number Signal Pin Number Signal 1 3.3V 31 1.8V(*) 61 D12 2 3.3V 32 1.8V(*) 62 D7 3 3.3V 33 RESET 63 D10 4 3.3V 34 SCL 64 D5 5 3.3V 35 INT 65 D8 6 3.3V 36 SDA 66 D3 7 3.3V 37 N.C 67 D6 8 3.3V 38 N.C 68 D1 9 3.3V_OR_5V(**) 39 D28 69 D4 10 3.3V_OR_5V(**) 40 D29 70 D0 11 3.3V_OR_5V(**) 41 D26 71 D2 12 3.3V_OR_5V(**) 42 D27 72 DE 13 3.
WHDI Connector Pin-Outs Version 1.
Electrical Specifications Chapter 5 Electrical Specifications 5.1 Operating Conditions and Electrical Characteristics The following tables describe the operating conditions and electrical characteristics required for working with the AMN11100. Table 9: Absolute Maximum Ratings over Operating Case Temperature Range Supply input-voltage range, VI 0 to 3.6 V Ambient temperature range 0°C to 70°C Storage temperature range, Tstg -40°C to 125°C Table 10: Recommended Operating Conditions Parameter Min.
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Design Guidelines Chapter 6 Design Guidelines 6.1 Digital Layout Recommendation To better understand the layout guidelines, please refer to the AMN11100 schematics which are part of the HDK package. 6.1.1 Stuck up Recommended stuck up for 10 layers design: • Total thickness 1.6mm • Tolerance: 10% Table 12: Digital Layout Recommendation Conductor Width [mil] StuckUp thickness Title Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Des. Before Scale Oz/mil 0.
Design Guidelines 6.1.2 General Guidelines • Keep traces as short as possible. • Traces should be routed over full solid reference plans. • Sensitive lines like reset and clocks should be routed with special care. These lines should be routed over full solid power plans (ground or power). Traces should be routed at least 2 times the trace width away from other lines in the same routing layer. Place a series resistor ~30 ohm at the clock source. • Keep digital signals away from the analog side.
Design Guidelines 6.1.4.1 Power Rails/Pins Summary for AMN2110 Chip: • Analog: 1.2 Volt: Pins names: DA10_0_AVDD1V2 DA10_1_AVDD1V2 DA10_2_AVDD1V2 DA10_3_AVDD1V2 AD8_AVDD1V2 AD10_AVDD1V2_0 AD10_AVDD1V2_1 PLL_AVDD 3.3 Volt: Pins: DA10_0_AVDD3V3_0 DA10_0_AVDD3V3_1 DA10_1_AVDD3V3_0 DA10_1_AVDD3V3_1 DA10_2_AVDD3V3_0 DA10_2_AVDD3V3_1 DA10_3_AVDD3V3_0 DA10_3_AVDD3V3_1 • Digital: 1.2 Volt: Pins names: VDD_0 to VDD_9 (total 10 pins) 3.
Design Guidelines 6.2 RF Design Recommendation 6.2.1 RF Components All passive components must have compatible performance with components used in the Amimon reference design. 6.2.2 Power Management The power management is divided such that each channel has independent filtered power supply of 2.85Vdc. Figure 1 shows the power scheme of the RF section of the transmitter. LDO 300mA LDO 300mA LDO 300mA LDO 300mA LDO 120mA/Low Noise Vcc 120mA Vcc 120mA Vcc 120mA Vcc 120mA MAX2828 Synth.
Mechanical Dimensions Chapter 7 Mechanical Dimensions The following shows the mechanical dimensions for the AMN11100: Figure 13: Mechanical Dimensions Version 1.
Mechanical Dimensions Version 1.
