L9N-7880 UHF DATA TRANSCEIVERS . PLL SYNTHESIZED Service Manual HEC HERMES ELECTRONICS CO., LTD.
1. SPECIFICATION GENERAL SPECIFICATIONS POWER SOURCE … … … … … … … … … … … … … … … +5VD.C. TEMPERATURE RANGE STORAGE … … … … … … … … … … … … … … … .80℃ maximum -40℃ min. 25℃ nominal OPERATING … … … … … … … … … … … … … … .60℃ maximum -20℃ min. ANTENNA IMPEDANCE … … … … … … … … … … … … ...50Ω FREQUENCY CONTROL … … … … … … … … … … FREQUENCIES OF OPERATION … … … … … … FREQUENCY TOLERANCE AND STABILITY HIGH HUMIDITY … … … … … … … … … … … … … … … … … … … ...PLL SYNTHESISER … … ..402MHZ-470MHZ … … … ± 2.
14.7456 MHz VCTCXO An external clock signal from VCTCXO X1 is connect to CC1020 XOSC_Q1 , This VCTCXO is only 5x3.2x1.4(H) mm, and is manufactured with a ceramic base and metal lid to assure very good aging characteristics and reliability. This device offers an in ±2.5PPM over -30 to +75 Celsius. The VR1 is used to adjust the frequency is as close as possible to the exact required transmit frequency. Ideally it should be within 100 Hz at room temperature.
Configuration interface The microcontroller interface is shown in figure 5. The microcontroller uses 3 or 4 I/O pins for the configuration interface(PDI, PDO, PCLK and PSEL). PDO should be connected to an input at the microcontroller. PDI, PCLK and PSEL muse be microcontroller outputs. One I/O pin can be saved if PDI and PDO are connected together and a bi-directional pin is used at the microcontroller.
4-wire serial configuration interface CC1020 is configured via a simple 4-wire SPI-compatible (PDI, PDO, PCLK and PSEL). There are 8-bit configuration register, each addressed by a 7-bit address. A Read/Write bit initiates a read or write operation. A full configuration of CC1020 requires sending 33 data frames of 16 bits each (7 address bits, R?W bit and 8 data bits). The time needed for a full configuration depends on the PCLK frequency.
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Signal Interface The CC1020 can be used with NRZ (Non-Return-to-Zero) data or Manchester (also known as bi-phase-level) encoded data.CC1020 can also synchronize the data from the demodulator and provide the data clock at DCLK. The data format is controlled by the DATA_FORMAT[1:0] bits in the MODEM register. CC1020 can be configured for three different data formats: Synchronous NRZ mode. In transmit mode CC1020 provides the data clock at DCLK, and DIO is used as data input.
If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in receive mode and data input in transmit mode. The DCLK pin is not active and can be set to a high or low level by DATA_FORMAT[0]. If SEP_DI_DO = 1 in the INTERFACE register, the DCLK pin is the data output in receive mode and the DIO pin is the data input in transmit mode. In TX mode the DCLK pin is not active and can be set to a high or low level by DATA_FORMAT[0]. See Figure 10.
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4. PERFORMANCE TEST AND ALIGNMENT The alignment and performance test procedures assume the use of the following equipment. Discrete test equipment Volt Meter RF Power Meter.
Federal Communication Commission Interference Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
This device is intended only for OEM Integrators. The OEM integrator should be aware of the following important issues. Labeling of the End Product The end product integrate this module has to be clearly identified on the label that this end product contain an FCC approved RF module. The format of such statement could containTx FCC ID: L9N-7880 Integration Note a) This module is authorized under limited module approval specified to mobile host equipment.
