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Document Number: 322910-003

Intel

Core™ i5-600, i3-500 Desktop

Processor Series and Intel

Pentium

Desktop Processor 6000

Series

Datasheet – Volume 2

January 2011

Summary of content (360 pages)

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Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet – Volume 2 January 2011 Document Number: 322910-003
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents 1 Introduction ............................................................................................................ 13 2 Processor Configuration Registers ........................................................................... 15 2.1 Register Terminology ......................................................................................... 15 2.2 System Address Map ......................................................................................... 17 2.2.
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2.7.12 2.7.13 2.7.14 2.7.15 2.7.16 2.7.17 2.7.18 2.7.19 2.7.20 2.7.21 2.7.22 2.7.23 2.7.24 2.7.25 2.7.26 2.7.27 2.7.28 2.7.29 2.8 4 MCHBAR—MCH Memory Mapped Register Range Base Register ..................52 GGC—Graphics Control Register ............................................................53 DEVEN—Device Enable Register.............................................................54 DMIBAR—Root Complex Register Range Base Address Register..................55 LAC—Legacy Access Control Register......
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2.9 2.10 2.8.37 SSKPD—Sticky Scratchpad Data Register ............................................... 94 2.8.38 TSC1—Thermal Sensor Control 1 Register .............................................. 94 2.8.39 TSS1—Thermal Sensor Status 1 Register................................................ 95 2.8.40 TR1—Thermometer Read 1 Register ...................................................... 95 2.8.41 TOF1—Thermometer Offset 1 Register ................................................... 96 2.8.
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2.11 2.12 2.13 6 2.10.31 MC—Message Control Register............................................................. 137 2.10.32 MA—Message Address Register............................................................ 138 2.10.33 MD—Message Data Register ................................................................ 138 2.10.34 PEG_CAPL—PCI Express-G Capability List Register ................................. 138 2.10.35 PEG_CAP—PCI Express-G Capabilities Register ......................................
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2.13.8 2.13.9 2.13.10 2.14 2.15 2.16 MLT2—Master Latency Timer Register .................................................. 178 HDR2—Header Type Register .............................................................. 178 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address Register ........................................................................................... 179 2.13.11 GMADR—Graphics Memory Range Address Register ............................... 180 2.13.
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2.17 2.18 8 2.16.6 RTADDR_REG—Root-Entry Table Address Register ................................. 231 2.16.7 CCMD_REG—Context Command Register .............................................. 232 2.16.8 FSTS_REG—Fault Status Register ........................................................ 234 2.16.9 FECTL_REG—Fault Event Control Register ............................................. 235 2.16.10 FEDATA_REG—Fault Event Data Register .............................................. 236 2.16.
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2.19 2.20 2.18.27 IVA_REG—Invalidate Address Register ................................................. 283 2.18.28 IOTLB_REG—IOTLB Invalidate Register ................................................ 284 2.18.29 FRCD_REG—Fault Recording Registers ................................................. 286 2.18.30 VTPOLICY—VT Policy Register ............................................................. 287 PCI Device 6 Registers ...................................................................................
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2.21 3 10 2.20.5 VC0RCTL—VC0 Resource Control Register ............................................. 331 2.20.6 VC0RSTS—VC0 Resource Status Register.............................................. 332 Intel® Trusted Execution Technology (Intel® TXT) Specific Registers ...................... 332 2.21.1 TXT.DID—TXT Device ID Register ........................................................ 333 2.21.2 TXT.DPR—DMA Protected Range Register.............................................. 333 2.21.3 TXT.PUBLIC.KEY.
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Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 System Address Range ..................................................................................... 18 DOS Legacy Address Range ................................................................................ 19 Main Memory Address Range .............................................................................. 21 PCI Memory Address Range ................................................................................
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Revision History Revision Number -001 January 2010 Initial release • -002 Revision Date Description • • • -003 • Added the MCSAMPML—Memory Configuration, System Address Map and Pre-allocated Memory Lock Register. See Section 2.7.28. Added the PEG_TC—PCI Express Completion Timeout Register. See Section 2.11.7. Updated the system address map section, and main memory address space for better clarification Added the series designation “Intel® Pentium® desktop processor 6000 series”.
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Introduction 1 Introduction This is Volume 2 of the Datasheet for the Intel® Core™ i5-600, i3-500 Desktop processor series and Intel® Pentium® desktop processor 6000 series. The processor contains one or more PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket. This document describes these configuration space registers or device-specific control and status registers (CSRs) only.
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Introduction 14 Datasheet, Volume 2
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Processor Configuration Registers 2 Processor Configuration Registers 2.1 Register Terminology Table 2-1 shows the register-related terminology that is used in this chapter. Table 2-1. Register Terminology (Sheet 1 of 2) Item Description RO Read Only bit(s). Writes to these bits have no effect. These are static values only. RO-V Read Only/Volatile bit(s). Writes to these bits have no effect. These are status bits only. The value to be read may change based on internal events.
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Processor Configuration Registers Table 2-1. Register Terminology (Sheet 2 of 2) Item 16 Description RW-V-L Read/Write/Volatile/Lockable bit(s). These bits can be read and written by software. Hardware may set or clear the bit based upon internal events, possibly sooner than any subsequent software read could retrieve the value written. Additionally, there is a bit (which is marked RW-K or RW-L-K) that, when set, prohibits this bit field from being writable (bit field becomes Read Only).
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Processor Configuration Registers 2.2 System Address Map Note: The processor’s Multi Chip Package (MCP) conceptually consists of the processor and the north bridge chipset (GMCH) combined together in a single package. Hence, this section will have references to the processor as well as GMCH (or MCH) address mapping. The MCP supports 64 GB (36 bit) of addressable memory space and 64 KB+3 of addressable I/O space.
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Processor Configuration Registers Figure 2-1 represents system memory address map in a simplified form. Figure 2-1.
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Processor Configuration Registers 2.2.1 Legacy Address Range This area is divided into the following address regions: • 0 – 640 KB — DOS Area • 640 – 768 KB — Legacy Video Buffer Area • 768 – 896 KB in 16 KB sections (total of 8 sections) — Expansion Area • 896 – 960 KB in 16 KB sections (total of 4 sections) — Extended System BIOS Area • 960 KB – 1 MB Memory — System BIOS Area Figure 2-2.
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Processor Configuration Registers Non-SMM-mode processor accesses to this range are considered to be to the Video Buffer Area as described above. The processor will route these accesses on the noncoherent (NCS or NCB) channels. The processor always positively decodes internally mapped devices, namely the IGD and PCI-Express. Subsequent decoding of regions mapped to PCI Express or the DMI Interface depends on the Legacy VGA configuration bits (VGA Enable and MDAP).
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Processor Configuration Registers 2.2.2 Main Memory Address Range (1MB – TOLUD) This address range extends from 1 MB to the top of Low Usable physical memory that is permitted to be accessible by the GMCH (as programmed in the TOLUD register). The processor will route all addresses within this range as HOM accesses, which will be forwarded by the GMCH to the DRAM unless it falls into the optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory. Figure 2-3.
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Processor Configuration Registers 2.2.2.2 TSEG The TSEG register was moved from the GMCH to the processor. The GMCH will have no direct knowledge of the TSEG size. For processor initiated transactions, the processor will perform necessary decode and route appropriately on HOM (to DRAM) or NCS/NCB. TSEG is below IGD stolen memory, which is at the Top of Low Usable physical memory (TOLUD).
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Processor Configuration Registers Once the protected low/high memory region registers are configured, bus master protection to these regions is enabled through the Protected Memory Enable register. For platforms with multiple DMA-remapping hardware units, each of the DMAremapping hardware units must be configured with the same protected memory regions and enabled. 2.2.2.4 DRAM Protected Range (DPR) This protection range only applies to DMA accesses and GMADR translations.
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Processor Configuration Registers 2.2.2.6.3 Shadow GTT Stolen Space (SGSM) Shadow GSM will be only used once internal GFX and VT-d translations are enabled. The purpose of shadow GSM is to provide a physical space to hardware, where VT-d translation for PTE updates can be made on the fly and re-written back into physical memory. 2.2.2.7 Intel® Management Engine (Intel® ME) UMA ME (the iAMT Manageability Engine) can be allocated UMA memory. ME memory is “stolen” from the top of the host address map.
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Processor Configuration Registers There are sub-ranges within the PCI Memory address range defined as APIC Configuration Space, MSI Interrupt Space, and High BIOS Address Range. The exceptions listed above for internal graphics and the PCI Express ports MUST NOT overlap with these ranges. Figure 2-4.
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Processor Configuration Registers 2.2.2.9 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the PCH portion of the chipset, but may also exist as stand-alone components like PXH. The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be populated in the system.
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Processor Configuration Registers 2.2.3 Main Memory Address Space (4 GB to TOUUD) The processor will support 36 bit addressing. The maximum main memory size supported is 16 GB total DRAM memory. A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger. As a result, TOM, and TOUUD registers and REMAPBASE/REMAPLIMIT registers become relevant. The remap configuration registers exist to remap lost main memory space.
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Processor Configuration Registers 2.2.3.1 Programming Model The memory boundaries of interest are: • Bottom of Logical Address Remap Window defined by the REMAPBASE register, which is calculated and loaded by BIOS. • Top of Logical Address Remap Window defined by the REMAPLIMIT register, which is calculated and loaded by BIOS. • Bottom of Physical Remap Memory defined by the existing TOLUD register.
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Processor Configuration Registers 2.2.3.1.1 Case 1 — Less than 4 GB of Physical Memory (no remap) Figure 2-5.
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Processor Configuration Registers 2.2.3.1.2 Case 2 — Greater than 4 GB of Physical Memory Note: Internal graphics is not supported on the Intel Xeon processor L3406. Figure 2-6.
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Processor Configuration Registers 2.2.3.1.3 Case 3 — 4 GB or less of Physical Memory Note: Internal graphics is not supported on the Intel Xeon processor L3406. Figure 2-7.
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Processor Configuration Registers 2.2.3.1.4 Case 4 — Greater than 4 GB of Physical Memory, Remap Note: Internal graphics is not supported on the Intel Xeon processor L3406. Figure 2-8.
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Processor Configuration Registers 2.2.4 PCI Express* Configuration Address Space PCIEXBAR has moved to the processor. The processor now detects memory accesses targeting PCIEXBAR and the processor converts that access to QPI configuration accesses. BIOS must assign this address range such that it will not conflict with any other address ranges. 2.2.5 PCI Express* Graphics Attach (PEG) The processor can be programmed to direct memory accesses to a PCI Express interface.
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Processor Configuration Registers 2.2.6 Graphics Memory Address Ranges The processor can be programmed to direct memory accesses to IGD when addresses are within any of five ranges specified using registers in the processor Device 2 configuration space. 1. The Graphics Memory Aperture Base Register (GMADR) is used to access graphics memory allocated using the graphics translation table. 2.
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Processor Configuration Registers 2.2.7 System Management Mode (SMM) The processor handles all SMM mode transaction routing. The processor has no direct knowledge of SMM mode. The processor will never allow I/O devices access to CSEG/TSEG/HSEG ranges. DMI Interface and PCI Express masters are not allowed to access the SMM space. Table 2-2. 2.2.
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Processor Configuration Registers locations can be accessed only during I/O address wrap-around when address bit 16 is asserted. Address bit 16 is asserted on the processor bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. Address bit 16 is also asserted when an I/O access is made to 2 bytes from address 0FFFFh. A set of I/O accesses are consumed by the internal graphics device if it is enabled.
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Processor Configuration Registers Note that the processor Device 1 I/O address range registers defined above are used for all I/O space allocation for any devices requiring such a window on PCI-Express. The PCICMD1 register can disable the routing of I/O cycles to PCI-Express. 2.3 Configuration Process and Registers 2.3.1 Platform Configuration Structure The DMI physically connects the processor and the Intel PCH; so, from a configuration standpoint, the DMI is logically PCI Bus 0.
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Processor Configuration Registers Table 2-3. Device Number Assignment for Internal Processor Devices Processor Function 2.4 Device Number Host Bridge/DRAM Controller Device 0 Host-to-PCI Express* Bridge (virtual P2P) Device 1 Internal Graphics Device Device 2 Secondary Host-to-PCI Express Bridge (Device 6 is not supported on all SKUs.) Device 6 Configuration Mechanisms The GMCH is the originator of configuration cycles.
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Processor Configuration Registers 2.4.2 PCI Express* Enhanced Configuration Mechanism PCI Express extends the configuration space to 4096 bytes per device/function as compared to 256 bytes allowed by the latest PCI Local Bus Specification. PCI Express configuration space is divided into a PCI 3.0 compatible region, which consists of the first 256B of a logical device’s configuration space and a PCI Express extended region which consists of the remaining configuration space.
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Processor Configuration Registers Just the same as with PCI devices, each device is selected based on decoded address information that is provided as a part of the address portion of Configuration Request packets. A PCI Express device will decode all address information fields (bus, device, function and extended address numbers) to provide access to the correct register. To access this space (step 1 is done only once by BIOS), First determine the maximum bus number using the following algorithm. 1.
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Processor Configuration Registers Figure 2-10.
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Processor Configuration Registers 2.4.5 Bridge Related Configuration Accesses Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs.
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Processor Configuration Registers 2.4.5.2 DMI Configuration Accesses Accesses to disabled processor internal devices, bus numbers not claimed by the HostPCI Express bridge, or PCI Bus 0 devices not part of the processor will subtractively decode to the PCH and consequently be forwarded over the DMI using a PCI Express configuration TLP. If the Bus Number is zero, the processor will generate a Type 0 Configuration cycle TLP on DMI.
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Processor Configuration Registers positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, and write operation for the Configuration Address Register. In addition to reserved bits within a register, the processor contains address locations in the configuration space of the Host Bridge entity that are marked either "Reserved" or “Intel Reserved”.
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Processor Configuration Registers 2.7 PCI Express* Device 0 Registers Table 2-4 shows the PCI Express Device 0 register address map. Detailed register bit descriptions follow Table 2-4. Table 2-4.
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Processor Configuration Registers 2.7.1 VID—Vendor Identification Register This register combined with the Device Identification register uniquely identifies any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: 2.7.2 0/0/0/PCI 0–1h 8086h RO Bit Attr Reset Value 15:0 RO 8086h Description Vendor Identification Number (VID) PCI standard identification for Intel.
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Processor Configuration Registers 2.7.3 PCICMD—PCI Command Register Since processor Device 0 does not physically reside on PCI_A many of the bits are not implemented. B/D/F/Type: Address Offset: Reset Value: Access: 0/0/0/PCI 4–5h 0006h RO, RW Bit Attr Reset Value 15:10 RO 00h 9 RO 0b Fast Back-to-Back Enable (FB2B) This bit controls whether or not the master can do fast back-to-back write. Since device 0 is strictly a target this bit is not implemented and is hardwired to 0.
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Processor Configuration Registers 2.7.4 PCISTS—PCI Status Register This status register reports the occurrence of error events on Device 0's PCI interface. Since the processor Device 0 does not physically reside on PCI_A, many of the bits are not implemented. B/D/F/Type: Address Offset: Reset Value: Access: 48 0/0/0/PCI 6–7h 0090h RW1C, RO Bit Attr Reset Value 15 RW1C 0b Detected Parity Error (DPE) This bit is set when this device receives a Poisoned TLP.
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Processor Configuration Registers 2.7.5 RID—Revision Identification This register contains the revision number of the processor. The Revision ID (RID) is a traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function. B/D/F/Type: Address Offset: Reset Value: Access: Bit 7:0 2.7.
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Processor Configuration Registers 2.7.8 HDR—Header Type Register This register identifies the header layout of the configuration space. No physical register exists at this location. B/D/F/Type: Address Offset: Reset Value: Access: 2.7.9 0/0/0/PCI Eh 00h RO Bit Attr Reset Value Description 7:0 RO 00h PCI Header (HDR) This field always returns 0 to indicate that the processor is a single function device with standard header layout. Reads and writes to this location have no effect.
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Processor Configuration Registers 2.7.10 SID—Subsystem Identification Register This value is used to identify a particular subsystem. B/D/F/Type: Address Offset: Reset Value: Access: 2.7.11 0/0/0/PCI 2E–2Fh 0000h RW-O Bit Attr Reset Value Description 15:0 RW-O 0000h Subsystem ID (SUBID) This field should be programmed during BIOS initialization. After it has been written once, it becomes read only.
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Processor Configuration Registers 2.7.12 MCHBAR—MCH Memory Mapped Register Range Base Register This is the base address for the processor memory mapped configuration space. There is no physical memory within this 16 KB window that can be addressed. The 16 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the processor MMIO memory mapped configuation space is disabled and must be enabled by writing a 1 to MCHBAREN [Device 0, offset48h, bit 0].
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Processor Configuration Registers 2.7.13 GGC—Graphics Control Register All the bits in this register are Intel TXT lockable. B/D/F/Type: Address Offset: Reset Value: Access: 0/0/0/PCI 52–53h 0030h RW-L, RO Bit Attr Reset Value 15:12 RO 0h Reserved 0h GTT Graphics Memory Size (GGMS) This field is used to select the amount of main memory that is pre-allocated to support the Internal Graphics Translation Table. The BIOS ensures that memory is pre-allocated only when internal graphics is enabled.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: 2.7.14 0/0/0/PCI 52–53h 0030h RW-L, RO Bit Attr Reset Value 3:2 RO 00b Description Reserved 1 RW-L 0b IGD VGA Disable (IVD): 0 = Enable. Device 2 (IGD) claims VGA memory and IO cycles, the SubClass Code within Device 2 Class Code register is 00. 1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and IO), and the Sub- Class Code field within Device 2 function 0 Class Code register is 80.
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Processor Configuration Registers 2.7.15 DMIBAR—Root Complex Register Range Base Address Register This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the processor. There is no physical memory within this 4 KB window that can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space.
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Processor Configuration Registers 2.7.16 LAC—Legacy Access Control Register This 8-bit register controls steering of MDA cycles. There can only be at most one MDA device in the system. BIOS must not program bits 1:0 to 11b.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: BIOS Optimal Reset Value Bit 0 Datasheet, Volume 2 Attr RW 0/0/0/PCI 97h 00h RW 00h Reset Value Description 0b PEG0 MDA Present (MDAP0) This bit works with the VGA Enable bits in the BCTRL register of Device 1 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if device 1's VGA Enable bit is not set.
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Processor Configuration Registers 2.7.17 TOUUD—Top of Upper Usable DRAM Register This 16 bit register defines the Top of Upper Usable DRAM. Configuration software must set this value to TOM minus all EP pre-allocated memory if reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit + 1byte, 64 MB aligned, since reclaim limit is 64 MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison.
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Processor Configuration Registers 2.7.19 BGSM—Base of GTT Pre-allocated Memory Register This register contains the base address of DRAM memory pre-allocated for the GTT. BIOS determines the base of pre-allocated GTT memory by subtracting the GTT graphics memory pre-allocated size (PCI Device 0, offset 52h, bits 11:8) from the Base of memory pre-allocated for graphics (PCI Device 0, offset A4h, bits 31:20). This register is locked and becomes Read Only when CMD.LOCK.
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Processor Configuration Registers 2.7.21 TOLUD—Top of Low Usable DRAM Register This 16-bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics memory, and Memory pre-allocated for graphics are within the usable DRAM space defined. Programming Example: C1DRB3 is set to 5 GB BIOS knows the OS requires 1 GB of PCI space. BIOS also knows the range from 0_FEC0_0000h to 0_FFFF_FFFFh is not usable by the system.
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Processor Configuration Registers 2.7.22 PBFC—Primary Buffer Flush Control Register B/D/F/Type: Address Offset: Reset Value: Access: 2.7.23 0/0/0/PCI C0–C3h 0000_0000h RO, W Bit Attr Reset Value 31:1 RO 0h Reserved 0 W 0b Primary CWB Flush Control (PCWBFLSH) A processor write to this bit flushes the PCWB of all writes. The data associated with the write to this register is discarded.
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Processor Configuration Registers 2.7.24 ERRSTS—Error Status Register This register is used to report various error conditions using the SERR DMI messaging mechanism. An SERR DMI message is generated on a zero to one transition of any of these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated.
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Processor Configuration Registers 2.7.25 ERRCMD—Error Command Register This register controls the processor responses to various system errors. Since the processor does not have an SERR# signal, SERR messages are passed from the processor to the PCH over DMI. When a bit in this register is set, a SERR message will be generated on DMI whenever the corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for Device 0 using the PCI Command register.
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Processor Configuration Registers 2.7.26 SMICMD—SMI Command Register This register enables various errors to generate an SMI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers, respectively. Note that one and only one message type can be enabled. B/D/F/Type: Address Offset: Reset Value: Access: 2.7.
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Processor Configuration Registers 2.7.28 CAPID0—Capability Identifier Register This register is used to report various processor capabilities. B/D/F/Type: Address Offset: Reset Value: Access: 2.7.29 0/0/0/PCI E0–EBh SKU dependent RO Reset Value Bit Attr Description 96:35 RO Reserved 34:32 RO DMFC: DDR3 Maximum Frequency Capability This field controls which values may be written to the Memory Frequency Select field 6:4 of the Clocking Configuration registers (MCHBAR Offset C00h).
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Processor Configuration Registers 2.8 MCHBAR Registers Table 2-5.
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Processor Configuration Registers Table 2-5.
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Processor Configuration Registers 2.8.1 CSZMAP—Channel Size Mapping Register This register indicates the total memory that is mapped to Interleaved and Asymmetric operation respectively (1 MB granularity) used for Channel address decode.
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Processor Configuration Registers 2.8.2 CHDECMISC—Channel Decode Miscellaneous Register This register provides enhanced addressing configuration bits.
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Processor Configuration Registers 2.8.3 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 Register The DRAM Rank Boundary Registers define the upper boundary address of each DRAM rank with a granularity of 64 MB. Each rank has its own single-word DRB register. These registers are used to determine which chip select will be active for a given address.
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Processor Configuration Registers 2.8.4 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 Register See C0DRB0 register description for details. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 15:10 RO 00h 9:0 2.8.
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Processor Configuration Registers 2.8.6 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 Register See C0DRB0 register description for details.
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Processor Configuration Registers 2.8.7 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute Register The DRAM Rank Attribute Registers define the page sizes/number of banks to be used when accessing different ranks. These registers should be left with their Reset Value (all zeros) for any rank that is unpopulated, as determined by the corresponding CxDRB registers. Each byte of information in the CxDRA registers describes the page size of a pair of ranks.
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Processor Configuration Registers 2.8.8 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute Register See C0DRA01 register description for programming details. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.8.9 Attr 0/0/0/MCHBAR 20A–20Bh 0000h RW-L Reset Value Description 15:8 RW-L 00h Channel 0 DRAM Rank-3 Attributes (C0DRA3) This register defines DRAM page size/number-of-banks for rank 3 for given channel. This register is locked by Memory pre-allocated for ME lock.
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Processor Configuration Registers 2.8.10 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG Register B/D/F/Type: Address Offset: Reset Value: Access: 0/0/0/MCHBAR 250-251h 0000h RO, RW Bit Attr Reset Value 15:11 RO 00h Reserved Datasheet, Volume 2 Description 10:6 RW 00h Write To Precharge Delay (C0sd_cr_wr_pchg) This field indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the same rank-bank. This value corresponds to the tWR parameter in the DDR3 Specification.
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Processor Configuration Registers 2.8.11 C0CYCTRKACT—Channel 0 CYCTRK ACT Register B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 31:30 RO 00b 29 28 76 0/0/0/MCHBAR 252–255h 0000_0000h RW, RO RW RW Description Reserved 0b FAW Windowcnt Bug Fix Disable (FAWWBFD) This bit disables the CYCTRK FAW windowcnt bug fix.
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Processor Configuration Registers 2.8.12 C0CYCTRKWR—Channel 0 CYCTRK WR Register B/D/F/Type: Address Offset: Reset Value: Access: 2.8.13 0/0/0/MCHBAR 256–257h 0000h RW Bit Attr Reset Value Description 15:12 RW 0h Activate To Write Delay (C0sd_cr_act_wr) This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the same rank-bank. This value corresponds to the tRCD_wr parameter in the DDR3 specification.
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Processor Configuration Registers 2.8.14 C0CYCTRKREFR—Channel 0 CYCTRK REFR Register This register provides Channel 0 CYCTRK Refresh control. B/D/F/Type: Address Offset: Reset Value: Access: 2.8.15 0/0/0/MCHBAR 25B–25Ch 0000h RO, RW Bit Attr Reset Value 15:13 RO 000b 12:9 RW 0h Same Rank Precharge All to Refresh Delay (C0sd_cr_pchgall_rfsh) This field indicates the minimum allowed spacing (in DRAM clocks) between the PRE-ALL and REF commands to the same rank.
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Processor Configuration Registers 2.8.16 C0REFRCTRL—Channel 0 DRAM Refresh Control Register This register provides settings to configure the DRAM refresh controller.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 21:20 19:18 17:16 15:14 13:0 80 Attr RW RW RW RW RW 0/0/0/MCHBAR 269–26Eh 241830000C30h RW, RO Reset Value Description 00b DRAM Refresh Hysterisis (REFHYSTERISIS) Hysterisis level — useful for dref_high watermark cases. The dref_high flag is set when the dref_high watermark level is exceeded, and is cleared when the refresh count is less than the hysterisis level.
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Processor Configuration Registers 2.8.17 C0JEDEC—Channel 0 JEDEC Control Register This is the Channel 0 JEDEC Control Register. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value Description 7 RW 0b Functional Loopback Mode Enable (FLME) This configuration setting indicates that the chip is placed in FME (Functional Loopback Mode Enable) mode. 6 RW 0b Write Levelization Mode (WRLVLMDE) This configuration bit indicates that memory controller is in write levelization mode.
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Processor Configuration Registers 2.8.18 C0ODT—Channel 0 ODT Matrix Register This is an ODT related configuration register. It is BIOS responsibility to program these bits to turn on/off the DRAM ODT signals according to how the system is populated; that is, 2r/2r, 2r/1r, 1r/2r, 1r/1r, 2r/nc, nc/2r, 1r/nc, nc/1r. This software approach has the benefit of simplifying the hardware, helping PV and increasing greater flexibility in ODT choices (especially when multiple ODT are required to be turned on).
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Reset Value Description 9 RW 0b DODTRD0R1 (sd0_cr_rdrank0_r1odt) Assert rank1 ODT during Reads from RANK0. 1 = ON 0 = OFF 8 RW 0b DODTRD0R0 (sd0_cr_rdrank0_r0odt) Assert rank0 ODT during Reads from RANK0. 1 = ON 0 = OFF 7 RW 0b DODTWR1R3 (sd0_cr_wrrank1_r3odt) Assert rank3 ODT during Writes to RANK1. 1 = ON 0 = OFF 6 RW 0b DODTWR1R2 (sd0_cr_wrrank1_r2odt) Assert rank2 ODT during Writes to RANK1.
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Processor Configuration Registers 2.8.19 C0ODTCTRL—Channel 0 ODT Control Register B/D/F/Type: Address Offset: Reset Value: Access: 2.8.20 0/0/0/MCHBAR 29C–29Fh 0000_0000h RW, RO Bit Attr Reset Value 31:12 RO 00000h 11:8 RW 0h DRAM ODT for Read Commands (sd0_cr_odt_duration_rd) Specifies the duration in mb2clks to assert DRAM ODT for Read Commands. The Async value should be used when the Dynamic Powerdown bit is set. Otherwise, use the Sync value.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Reset Value Description Time Constant (TC) 000 = 2^28 Clocks 001 = 2^29 Clocks 010 = 2^30 Clocks 011 = 2^31 Clocks Others = Reserved 18:16 RW-L 000b 15:8 RW-L 00h Weighted Average Bandwidth Limit (WAB) Average weighted bandwidth allowed per clock during bandwidth based throttling.
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Processor Configuration Registers 2.8.22 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 Register The operation of this register is detailed in the description for register C0DRB0. B/D/F/Type: Address Offset: Reset Value: Access: 2.8.23 0/0/0/MCHBAR 600–601h 0000h RW-L, RO Bit Attr Reset Value 15:10 RO 000000b 9:0 RW-L 000h Description Reserved Channel 1 DRAM Rank Boundary Address 0 (C1DRBA0) See C0DRB0 register description. This register is locked by Memory pre-allocated for ME lock.
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Processor Configuration Registers 2.8.25 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 Register The operation of this register is detailed in the description for register C0DRB0. B/D/F/Type: Address Offset: Reset Value: Access: 2.8.26 0/0/0/MCHBAR 606–607h 0000h RW-L, RO Bit Attr Reset Value 15:10 RO 000000b 9:0 RW-L 000h Description Reserved Channel 1 DRAM Rank Boundary Address 3 (C1DRBA3) See C0DRB3 register description. This register is locked by Memory pre-allocated for ME lock.
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Processor Configuration Registers 2.8.28 C1WRDATACTRL—Channel 1 Write Data Control Register This register provides Channel 1 Write Data Control. B/D/F/Type: Address Offset: Reset Value: Access: BIOS Optimal Reset Value 2.8.
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Processor Configuration Registers 2.8.30 C1CYCTRKACT—Channel 1 CYCTRK ACT Register This register provides Channel 1 CYCTRK ACT control. B/D/F/Type: Address Offset: Reset Value: Access: 0/0/0/MCHBAR 652–655h 0000_0000h RW, RO Bit Attr Reset Value 31:30 RO 0h Reserved 0b FAW Windowcnt Bug Fix Disable (FAWWBFD) This bit disables the CYCTRK FAW windowcnt bug fix.
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Processor Configuration Registers 2.8.31 C1CYCTRKWR—Channel 1 CYCTRK WR Register This register provides Channel 1 CYCTRK WR control. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.8.32 Attr 0/0/0/MCHBAR 656–657h 0000h RW Reset Value Description 15:12 RW 0h ACT To Write Delay (C1sd_cr_act_wr) This field indicates the minimum allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the same rank-bank. This field corresponds to tRCD_wr in the DDR specification.
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Processor Configuration Registers 2.8.33 C1CKECTRL—Channel 1 CKE Control Register This register provides Channel 1 CKE Control. B/D/F/Type: Address Offset: Reset Value: Access: 0/0/0/MCHBAR 660–663h 0000_0800h RW, RW-L, RO Bit Attr Reset Value 31:28 RO 0h Reserved 27 RW 0b start the self-refresh exit sequence (sd1_cr_srcstart) This bit indicates the request to start the self-refresh exit sequence.
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Processor Configuration Registers 2.8.34 C1PWLRCTRL—Channel 1 Partial Write Line Read Control Register This register is to configure the DRAM controller's partial write policies. B/D/F/Type: Address Offset: Reset Value: Access: 2.8.
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Processor Configuration Registers 2.8.36 C1DTC—Channel 1 DRAM Throttling Control Register Programmable Event weights are input into the averaging filter. Each Event weight is an normalized 8 bit value that the BIOS must program. The BIOS must account for burst length and 1N/2N rule considerations. It is also possible for BIOS to take into account loading variations of memory caused as a function of memory types and population of ranks.
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Processor Configuration Registers 2.8.37 SSKPD—Sticky Scratchpad Data Register This register holds 64 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. B/D/F/Type: Address Offset: Reset Value: Access: 2.8.38 0/0/0/MCHBAR C20–C27h 0000_0000_0000_0000h RW/P Bit Attr Reset Value 63:0 RW-S 00..
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Processor Configuration Registers 2.8.39 TSS1—Thermal Sensor Status 1 Register This read only register provides trip point and other status of the thermal sensor. B/D/F/Type: Address Offset: Reset Value: Access: 2.8.
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Processor Configuration Registers 2.8.41 TOF1—Thermometer Offset 1 Register This register is used for programming the thermometer offset. B/D/F/Type: Address Offset: Reset Value: Access: Bit 7:0 2.8.42 Attr RW 0/0/0/MCHBAR 1007h 00h RW Reset Value Description 00h Thermometer Offset (TOF) This value is used to adjust the current thermometer reading so that the TR value is not relative to a specific trip or calibration point, and is positive going for positive increases in temperature.
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Processor Configuration Registers 2.8.43 TSTTPA1—Thermal Sensor Temperature Trip Point A1 Register This register sets the target values for some of the trip points in thermometer mode. See also TST [Direct DAC Connect Test Enable]. This register also reports the relative thermal sensor temperature. See also TSTTPB.
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Processor Configuration Registers 2.8.44 TSTTPB1—Thermal Sensor Temperature Trip Point B1 Register This register sets the target values for some of the trip points in the Thermometer mode. See also TSTTPA1. B/D/F/Type: Address Offset: Reset Value: Access: 2.8.45 0/0/0/MCHBAR 1014–1017h 0000_0000h RW-L Bit Attr Reset Value 31:24 RW-L 00h Aux 3 Trip Point Setting (A3TPS) Sets the target value for the Aux3 trip point Lockable by TSTTPA1[31].
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Processor Configuration Registers 2.8.46 HWTHROTCTRL1—Hardware Throttle Control 1 Register B/D/F/Type: Address Offset: Reset Value: Access: Bit Reset Value Description 7 RW-L 0b Internal Thermal Hardware Throttling Enable (ITHTE) This bit is a master enable for internal thermal sensor-based hardware throttling: 0 = Hardware actions using the internal thermal sensor are disabled. 1 = Hardware actions using the internal thermal sensor are enabled.
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Processor Configuration Registers 2.8.47 TIS1—Thermal Interrupt Status 1 Register This register is used to report which specific error condition resulted in the D2F0 or D2F1 ERRSTS[Thermal Sensor event for SMI/SCI/SERR] or memory mapped IIR Thermal Event. Software can examine the current state of the thermal zones by examining the TSS. Software can distinguish internal or external Trip Event by examining TSS.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 3 2 1 0 Datasheet, Volume 2 Attr RW1C RW1C RW1C RW1C 0/0/0/MCHBAR 101E–101Fh 0000h RO, RW1C Reset Value Description 0b Aux 3 Thermal Sensor Interrupt Event (A3TSIE) 1 = Aux 3 Thermal Sensor trip event occurred based on a lower to higher temperature transition through the trip point. 0 = No trip for this event. Software must write a 1 to clear this status bit.
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Processor Configuration Registers 2.8.48 TERATE—Thermometer Mode Enable and Rate Register This common register helps select between the analog and the thermometer mode and also helps select the DAC settling timer.
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Processor Configuration Registers 2.8.49 TERRCMD—Thermal Error Command Register This register select which errors are generate a SERR DMI interface special cycle, as enabled by ERRCMD [SERR Thermal Sensor event]. The SERR and SCI must not be enabled at the same time for the thermal sensor event.
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Processor Configuration Registers 2.8.50 TSMICMD—Thermal SMI Command Register This register selects specific errors to generate a SMI DMI cycle, as enabled by the SMI Error Command Register[SMI on Thermal Sensor Trip]. B/D/F/Type: Address Offset: Reset Value: Access: 104 0/0/0/MCHBAR 10E5h 00h RO, RW Bit Attr Reset Value 7:6 RO 00b 5 RW 0b SMI on Catastrophic Thermal Sensor Trip (CATSMI) 1 = Does not mask the generation of an SMI DMI cycle on a catastrophic thermal sensor trip.
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Processor Configuration Registers 2.8.51 TSCICMD—Thermal SCI Command Register This register selects specific errors to generate a SCI DMI cycle, as enabled by the SCI Error Command Register[SCI on Thermal Sensor Trip]. The SCI and SERR must not be enabled at the same time for the thermal sensor event.
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Processor Configuration Registers 2.8.52 TINTRCMD—Thermal INTR Command Register This register selects specific errors to generate a INT DMI cycle.
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Processor Configuration Registers 2.8.53 EXTTSCS—External Thermal Sensor Control and Status Register B/D/F/Type: Address Offset: Reset Value: Access: Bit Reset Value Description 15 RW-O 0b External Sensor Enable (ESE) Setting this bit to 1 locks the lockable bits in this register. This bit may only be set to a zero by a hardware reset. Once locked, writing a 0 to bit has no effect. EXTTS0 and EXTTS1 input signal pins are dedicated for external thermal sensor use.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 6 5 4 3 108 Attr RW-L RW-L RW-L RO 0/0/0/MCHBAR 10EC–10EDh 0000h RO, RW-O, RW-L Reset Value Description 0b Throttling Type Select (TTS) Lockable by EXTTSCS [External Sensor Enable].
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Processor Configuration Registers 2.8.54 DDRMPLL1—DDR PLL BIOS Register This register is for DDR PLL register programming. B/D/F/Type: Address Offset: Reset Value: Access: 0/0/0/MCHBAR 2C20–2C22h 00000Ch RO, RW, RW-S Bit Attr Reset Value 23:12 RO 00b 11 Datasheet, Volume 2 RW-S Description Reserved 0b Alternative VCO Select (VCOSEL) 0 = Use VCO A 1 = Use VCO B VCO A is recommended Default value. 10 RW-S 0b Post Divide For DDR 800 Mode (DIVSEL) Post Divider value 1 versus 2.
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Processor Configuration Registers 2.9 EPBAR Registers 2.9.1 EPPVCCAP1—EP Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with this port. B/D/F/Type: Address Offset: Reset Value: Access: 2.9.2 0/0/0/PXPEPBAR 4–7h 0000_0001h RO, RWO Bit Attr Reset Value 31:12 RO 00000h 11:10 RO 00b Port Arbitration Table Entry Size (PATES) This field indicates that the size of the Port Arbitration table entry is 1 bit.
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Processor Configuration Registers 2.9.3 EPVC0RCTL—EP VC 0 Resource Control Register This register controls the resources associated with Egress Port Virtual Channel 0. B/D/F/Type: Address Offset: Reset Value: Access: 0/0/0/PXPEPBAR 14–17h 8000_00FFh RO, RW Bit Attr Reset Value 31 RO 1b VC0 Enable (VC0E) For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
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Processor Configuration Registers 2.9.4 EPVC0RCAP—EP VC 0 Resource Capability Register B/D/F/Type: Address Offset: Reset Value: Access: 112 0/0/0/PXPEPBAR 10–13h 0000_0001h RO Bit Attr Reset Value 31:24 RO 00h 23 RO 0b 22:16 RO 00h Description Reserved for Port Arbitration Table Offset No VC0 port arbitration necessary. Reserved Reserved for Maximum Time Slots No VC0 port arbitration necessary.
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Processor Configuration Registers 2.9.5 EPVC1RCTL—EP VC 1 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 1. B B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr 0/0/0/PXPEPBAR 20–23h 0100_0000h RW, RO Reset Value Description 31 RW 0b VC1 Enable (VC1E) This bit will be ignored by the hardware.
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Processor Configuration Registers 2.9.6 EPVC1RSTS—EP VC 1 Resource Status Register B/D/F/Type: Address Offset: Reset Value: Access: 114 0/0/0/PXPEPBAR 26–27h 0000h RO Bit Attr Reset Value 15:2 RO 0000h Description Reserved and zero 1 RO 0b VC1 Negotiation Pending (VC1NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling). For this non-default Virtual Channel, software may use this bit when enabling or disabling the VC.
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Processor Configuration Registers 2.10 PCI Device 1 Registers Table 2-7.
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Processor Configuration Registers Table 2-7.
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Processor Configuration Registers 2.10.1 VID1—Vendor Identification Register This register combined with the Device Identification register uniquely identify any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: 2.10.2 0/1/0/PCI 0–1h 8086h RO Bit Attr Reset Value 15:0 RO 8086h Description Vendor Identification (VID1) PCI standard identification for Intel.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 118 Attr 0/1/0/PCI 4–5h 0000h RO, RW Reset Value Description 8 RW 0b SERR# Message Enable (SERRE1) This bit controls Device 1 SERR# messaging. The processor communicates the SERR# condition by sending an SERR message to the PCH. This bit, when set, enables reporting of non-fatal and fatal errors detected by the device to the Root Complex.
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Processor Configuration Registers 2.10.4 PCISTS1—PCI Status Register This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge embedded within the processor. B/D/F/Type: Address Offset: Reset Value: Access: Datasheet, Volume 2 0/1/0/PCI 6–7h 0010h RO, RW1C Bit Attr Reset Value Description 15 RO 0b Detected Parity Error (DPE) Not Applicable or Implemented. Hardwired to 0.
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Processor Configuration Registers 2.10.5 RID1—Revision Identification Register This register contains the revision number of the processor device 1. These bits are read only and writes to this register have no effect. This register contains the revision number of the processor. The Revision ID (RID) is a traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function.
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Processor Configuration Registers 2.10.7 CL1—Cache Line Size Register B/D/F/Type: Address Offset: Reset Value: Access: 2.10.8 0/1/0/PCI Ch 00h RW Bit Attr Reset Value 7:0 RW 00h Description Cache Line Size (Scratch pad) Implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no impact on any PCI Express device functionality. HDR1—Header Type Register This register identifies the header layout of the configuration space.
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Processor Configuration Registers 2.10.10 SBUSN1—Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the "virtual" bridge (that is, to PCI Express-G). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express-G. B/D/F/Type: Address Offset: Reset Value: Access: 2.10.
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Processor Configuration Registers 2.10.12 IOBASE1—I/O Base Address Register This register controls the processor to PCI Express-G I/O access routing based on the following formula: IO_BASE  address  IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4 KB boundary. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.10.
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Processor Configuration Registers 2.10.14 SSTS1—Secondary Status Register SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI bridge embedded within processor.
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Processor Configuration Registers 2.10.15 MBASE1—Memory Base Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are readonly and return zeroes when read. This register must be initialized by the configuration software.
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Processor Configuration Registers 2.10.16 MLIMIT1—Memory Limit Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are readonly and return zeroes when read. This register must be initialized by the configuration software.
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Processor Configuration Registers 2.10.17 PMBASE1—Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
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Processor Configuration Registers 2.10.18 PMLIMIT1—Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
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Processor Configuration Registers 2.10.20 PMLIMITU1—Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation.
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Processor Configuration Registers 2.10.22 INTRLINE1—Interrupt Line Register This register contains interrupt line routing information. The device itself does not use this value, rather it is used by device drivers and operating systems to determine priority and vector information. B/D/F/Type: Address Offset: Reset Value: Access: Bit 7:0 2.10.
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Processor Configuration Registers 2.10.24 BCTRL1—Bridge Control Register This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The BCTRL provides additional control for the secondary interface (that is, PCI Express-G) as well as some bits that affect the overall behavior of the "virtual" HostPCI Express bridge embedded within the processor, such as, VGA compatible address ranges mapping.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 1 0 2.10.25 Attr RW RW 0/1/0/PCI 3E–3Fh 0000h RO, RW Reset Value Description 0b SERR Enable (SERREN) 0 = No forwarding of error messages from secondary side to primary side that could result in an SERR. 1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register.
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Processor Configuration Registers 2.10.26 PM_CAPID1—Power Management Capabilities Register B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr 0/1/0/PCI 80–83h C8039001h RO Reset Value Description PME Support (PMES) This field indicates the power states in which this device may indicate PME wake using PCI Express messaging. D0, D3hot, and D3cold. This device is not required to do anything to support D3hot and D3cold, it simply must report that those states are supported.
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Processor Configuration Registers 2.10.27 PM_CS1—Power Management Control/Status Register B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 31:16 RO 0000h 15 RO 0b 14:13 RO 00b Data Scale (DSCALE) Indicates that this device does not support the power management data register. 12:9 RO 0h Data Select (DSEL) Indicates that this device does not support the power management data register.
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Processor Configuration Registers 2.10.28 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. However, it is necessary because Microsoft will test for its presence. B/D/F/Type: Address Offset: Reset Value: Access: 2.10.
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Processor Configuration Registers 2.10.30 MSI_CAPID—Message Signaled Interrupts Capability ID Register When a device supports MSI, it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability.
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Processor Configuration Registers 2.10.31 MC—Message Control Register System software can modify bits in this register, but the device is prohibited from doing so. If the device writes the same message multiple times, only one of those messages is ensured to be serviced. If all of them must be serviced, the device must not generate the same message again until the driver services the earlier one.
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Processor Configuration Registers 2.10.32 MA—Message Address Register B/D/F/Type: Address Offset: Reset Value: Access: 2.10.33 0/1/0/PCI 94–97h 0000_0000h RW, RO Bit Attr Reset Value Description 31:2 RW 0000_000 0h Message Address (MA) This field is used by system software to assign an MSI address to the device. The device handles an MSI by writing the padded contents of the MD register to this address.
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Processor Configuration Registers 2.10.35 PEG_CAP—PCI Express-G Capabilities Register This register indicates PCI Express device capabilities. B/D/F/Type: Address Offset: Reset Value: Access: 2.10.36 0/1/0/PCI A2–A3h 0142h RO, RW-O Bit Attr Reset Value 15 RO 0b Reserved 14 RO 0b Reserved: Reserved for TCS Routing Supported. 13:9 RO 00h Description Interrupt Message Number (IMN) Not Applicable or Implemented. Hardwired to 0.
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Processor Configuration Registers 2.10.37 DCTL—Device Control Register This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register.
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Processor Configuration Registers 2.10.38 DSTS—Device Status Register This register reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value Description 15:6 RO 000h Reserved and Zero: Reserved for future R/WC/S implementations; software must use 0 for writes to bits.
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Processor Configuration Registers 2.10.39 LCAP—Link Capabilities Register This register indicates PCI Express device specific capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value Description 31:24 RO 02h Port Number (PN) This bit indicates the PCI Express port number for the given PCI Express link. Matches the value in Element Self Description[31:24].
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr 0/1/0/PCI AC–AFh 02214D02h RO, RW-O Reset Value Description L0s Exit Latency (L0SELAT) This field indicates the length of time this Port requires to complete the transition from L0s to L0.
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Processor Configuration Registers 2.10.40 CTL—Link Control Register This register allows control of PCI Express link.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 5 RW-SC Reset Value Description 0b Retrain Link (RL) 0 = Normal operation. 1 = Full Link retraining is initiated by directing the Physical Layer LTSSM from L0, L0s, or L1 states to the Recovery state. This bit always returns 0 when read. This bit is cleared automatically (no need to write a 0). 4 RW 0b Link Disable (LD) 0 = Normal operation 1 = Link is disabled.
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Processor Configuration Registers 2.10.41 LSTS—Link Status Register This register indicates PCI Express link status.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 9:4 3:0 Datasheet, Volume 2 Attr RO RO 0/1/0/PCI B2–B3h 1000h RW1C, RO Reset Value Description 00h Negotiated Link Width (NLW) This field indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed). 00h = Reserved 01h = X1 02h = X2 04h = X4 08h = X8 10h = X16 All other encodings are reserved.
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Processor Configuration Registers 2.10.42 SLOTCAP—Slot Capabilities Register Note: Hot Plug is not supported on the platform. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 31:19 RW-O 0000h Physical Slot Number (PSN) Indicates the physical slot number attached to this Port. BIOS Requirement: This field must be initialized by BIOS to a value that assigns a slot number that is globally unique within the chassis.
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Processor Configuration Registers 2.10.43 SLOTCTL—Slot Control Register Note: Hot Plug is not supported on the platform. B/D/F/Type: Address Offset: Reset Value: Access: 0/1/0/PCI B8–B9h 0000h RO, RW Bit Attr Reset Value 15:13 RO 000b Reserved 12 RO 0b Reserved for Data Link Layer State Changed Enable (DLLSCE) If the Data Link Layer Link Active capability is implemented, when set to 1b, this field enables software notification when Data Link Layer Link Active field is changed.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 7:6 5 RO RO Reset Value Description 00b Reserved for Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.
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Processor Configuration Registers 2.10.44 SLOTSTS—Slot Status Register Note: Hot Plug is not supported on the platform. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value Description 15:9 RO 0000000b Reserved and Zero: Reserved for future R/WC/S implementations; software must use 0 for writes to bits. 0b Reserved for Data Link Layer State Changed (DLLSC) This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: 152 0/1/0/PCI BA–BBh 0000h RO, RW1C Bit Attr Reset Value Description 2 RO 0b Reserved for MRL Sensor Changed (MSC) If an MRL sensor is implemented, this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented, this bit must not be set.
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Processor Configuration Registers 2.10.45 RCTL—Root Control Register Allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link. Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register.
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Processor Configuration Registers 2.10.46 RSTS—Root Status Register This register provides information about PCI Express Root Complex specific parameters. B/D/F/Type: Address Offset: Reset Value: Access: 2.10.47 0/1/0/PCI C0–C3h 0000_0000h RO, RW1C Bit Attr Reset Value Description 31:18 RO 0000h Reserved and Zero: Reserved for future R/WC/S implementations; software must use 0 for writes to bits.
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Processor Configuration Registers 2.10.48 LSTS2—Link Status 2 Register B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 15:1 RO 0000h 0 2.10.49 0/1/0/PCI D2–D3h 0000h RO RO 0b Description Reserved Current De-emphasis Level (CURDELVL) 1 = 3.5 dB 0 = 6 dB When the link is operating at 2.5 GT/s speed, this bit is 0b. PEGLC—PCI Express* Legacy Control Register This register controls functionality that is needed by Legacy (non-PCI Express aware) OS's during run time.
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Processor Configuration Registers 2.11 Device 1 Extended Configuration Registers Table 2-8. Device 1 Extended Configuration Register Address Map Address Offset 2.11.
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Processor Configuration Registers 2.11.2 PVCCAP2—Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.11.3 Attr 0/1/0/MMR 108–10Bh 0000_0000h RO Reset Value Description VC Arbitration Table Offset (VCATO) This field indicates the location of the VC Arbitration Table.
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Processor Configuration Registers 2.11.4 VC0RCAP—VC0 Resource Capability Register B/D/F/Type: Address Offset: Reset Value: Access: Attr Reset Value 31:24 RO 00h 23 RO 0b 22:16 RO 00h Bit 2.11.5 0/1/0/MMR 110–113h 0000_0001h RO 15 RO 0b 14:8 RO 00h Description Reserved for Port Arbitration Table Offset Reserved Reserved for Maximum Time Slots Reject Snoop Transactions (RSNPT) 0 = Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: 2.11.6 0/1/0/MMR 114–117h 8000_00FFh RO, RW Bit Attr Reset Value 15:8 RO 00h Reserved Description 7:1 RW 7Fh TC/VC0 Map (TCVC0M) This field indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource.
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Processor Configuration Registers 2.11.7 PEG_TC—PCI Express Completion Timeout Register This register reports PCI Express configuration control of PCI Express Completion Timeout related parameters that are not required by the PCI Express specificaiton.
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Processor Configuration Registers 2.12 DMIBAR Registers Table 2-9. DMI Register Address Map 2.12.
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Processor Configuration Registers 2.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1 Describes the configuration of PCI Express Virtual Channels associated with this port. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 31:7 RO 0000000h 6:4 RO 000b 3 RO 0b 2:0 2.12.
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Processor Configuration Registers 2.12.4 DMIPVCCTL—DMI Port VC Control Register B/D/F/Type: Address Offset: Reset Value: Access: 2.12.5 0/0/0/DMIBAR C–Dh 0000h RO, RW Bit Attr Reset Value 15:4 RO 000h Reserved VC Arbitration Select (VCAS) This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field. The value 000b when written to this field will indicate the VC arbitration scheme is hardware fixed (in the root complex).
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Processor Configuration Registers 2.12.6 DMIVC0RCTL0—DMI VC0 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type: Address Offset: Reset Value: Access: 164 0/0/0/DMIBAR 14–17h 8000_00FFh RW, RO Bit Attr Reset Value 31 RO 1b Virtual Channel 0 Enable (VC0E) For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
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Processor Configuration Registers 2.12.7 DMIVC0RSTS—DMI VC0 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: 2.12.8 0/0/0/DMIBAR 1A–1Bh 0002h RO Bit Attr Reset Value Description 15:2 RO 0000h Reserved: Reserved and Zero for future R/WC/S implementations. Software must use 0 for writes to these bits. 1 RO 1b Virtual Channel 0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete.
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Processor Configuration Registers 2.12.9 DMIVC1RCTL1—DMI VC1 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 1. B/D/F/Type: Address Offset: Reset Value: Access: Bit 166 Attr 0/0/0/DMIBAR 20–23h 0100_0000h RO, RW Reset Value Description 31 RW 0b Virtual Channel Enable (VCE) 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled. See exceptions below.
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Processor Configuration Registers 2.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Datasheet, Volume 2 0/0/0/DMIBAR 26–27h 0002h RO Bit Attr Reset Value 15:2 RO 0000h Description Reserved 1 RO 1b Virtual Channel 1 Negotiation Pending (VC1NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
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Processor Configuration Registers 2.12.11 DMIVCPRCTL—DMI VCp Resource Control Register This register controls the resources associated with the DMI Private Channel. B/D/F/Type: Address Offset: Reset Value: Access: Bit 168 Attr 0/0/0/DMIBAR 2C–2Fh 0000_0000h RW, RO Reset Value Description 31 RW 0b Virtual Channel Enable (VCE) 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled. See exceptions below.
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Processor Configuration Registers 2.12.12 DMIVCPRSTS—DMI VCp Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: 2.12.13 0/0/0/DMIBAR 32–33h 0002h RO Bit Attr Reset Value Description 15:2 RO 0000h Reserved: Reserved and Zero for future R/WC/S implementations. Software must use 0 for writes to these bits. 1 RO 1b Virtual Channel private Negotiation Pending (VCPNP) 0 = The VC negotiation is complete.
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Processor Configuration Registers 2.12.14 DMILE1D—DMI Link Entry 1 Description Register This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31:24 2.12.15 Attr RW-O 0/0/0/DMIBAR 50–53h 0000_0000h RWO, RO Reset Value Description 00h Target Port Number (TPN) This field specifies the port number associated with the element targeted by this link entry (egress port of the PCH).
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Processor Configuration Registers 2.12.16 DMILE2D—DMI Link Entry 2 Description Register This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31:24 2.12.17 Attr RO 0/0/0/DMIBAR 60–63h 0000_0000h RO, RWO Reset Value Description 00h Target Port Number (TPN) This field specifies the port number associated with the element targeted by this link entry (Egress Port).
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Processor Configuration Registers 2.12.18 DMILCAP—DMI Link Capabilities Register This field indicates DMI specific capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 31:18 RO 0000h 17:15 172 0/0/0/DMIBAR 84–87h 00012C41h RO, RW-O RW-O Description Reserved 010b L1 Exit Latency (L1SELAT) This field indicates the length of time this Port requires to complete the transition from L1 to L0. The value 010b indicates the range of 2 us to less than 4 us.
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Processor Configuration Registers 2.12.19 DMILCTL—DMI Link Control Register This register allows control of DMI. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 15:8 RO 00h Description Reserved 7 RW 0b Extended Synch (EXTSYNC) 0 = Standard Fast Training Sequence (FTS). 1 = Forces the transmission of additional ordered sets when exiting the L0s state and when in the Recovery state.
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Processor Configuration Registers 2.13 PCI Device 2, Function 0 Registers Table 2-10. PCI (Device 2, Function 0) Register Address Map 2.13.
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Processor Configuration Registers 2.13.2 DID2—Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: 2.13.3 0/2/0/PCI 2–3h 0042h RO Bit Attr Reset Value 15:0 RO 0042h Description Device Identification Number (DID) This is a 16 bit value assigned to the processor Graphics device.
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Processor Configuration Registers 2.13.4 PCISTS2—PCI Status Register PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD. B/D/F/Type: Address Offset: Reset Value: Access: 176 0/2/0/PCI 6–7h 0090h RO Bit Attr Reset Value 15 RO 0b Detected Parity Error (DPE) Since the IGD does not detect parity, this bit is always hardwired to 0.
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Processor Configuration Registers 2.13.5 RID2—Revision Identification Register This register contains the revision number for Device 2, Functions 0 and 1. This register contains the revision number of the processor. The Revision ID (RID) is a traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function. B/D/F/Type: Address Offset: Reset Value: Access: Bit 7:0 2.13.
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Processor Configuration Registers 2.13.7 CLS—Cache Line Size Register The IGD does not support this register as a PCI slave. B/D/F/Type: Address Offset: Reset Value: Access: Bit 7:0 2.13.8 Attr RO 0/2/0/PCI Ch 00h RO Reset Value Description 00h Cache Line Size (CLS) This field is hardwired to 0s. The IGD as a PCI compliant master does not use the Memory Write and Invalidate command and, in general, does not perform operations based on cache line size.
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Processor Configuration Registers 2.13.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address Register This register requests allocation for the combined Graphics Translation Table Modification Range and Memory Mapped Range. The range requires 4 MB combined for MMIO and Global GTT aperture, with 512K of that used by MMIO and 2MB used by GTT. GTTADR will begin at (GTTMMADR + 2 MB) while the MMIO base address will be the same as GTTMMADR.
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Processor Configuration Registers 2.13.11 GMADR—Graphics Memory Range Address Register The IGD graphics memory base address is specified in this register. Software must not change the value in MSAC[1:0] (offset 62h) after writing to the GMADR register.
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Processor Configuration Registers 2.13.12 IOBAR—I/O Base Address Register This register provides the Base offset of the I/O registers within Device 2. Bits 15:3 are programmable allowing the I/O Base to be located anywhere in 16bit I/O Address Space. Bits 2:1 are fixed and return zero, bit 0 is hardwired to a one indicating that 8 bytes of I/O space are decoded. Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set.
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Processor Configuration Registers 2.13.14 SID2—Subsystem Identification Register B/D/F/Type: Address Offset: Reset Value: Access: 2.13.15 0/2/0/PCI 2E–2Fh 0000h RW-O Bit Attr Reset Value 15:0 RW-O 0000h Description Subsystem Identification (SUBID) This value is used to identify a particular subsystem. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can only be cleared by a Reset.
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Processor Configuration Registers 2.13.17 MINGNT—Minimum Grant Register B/D/F/Type: Address Offset: Reset Value: Access: 2.13.18 0/2/0/PCI 3Eh 00h RO Bit Attr Reset Value 7:0 RO 00h Minimum Grant Value (MGV) The IGD does not burst as a PCI compliant master. MAXLAT—Maximum Latency Register B/D/F/Type: Address Offset: Reset Value: Access: 2.
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Processor Configuration Registers 2.14.1 Index—MMIO Address Register A 32 bit I/O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed. An I/O Read returns the current value of this register. An 8/16 bit I/O write to this register is completed by the processor but does not update this register. This mechanism to access internal graphics MMIO registers must not be used to access VGA IO registers which are mapped through the MMIO space.
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Processor Configuration Registers 2.15 DMI and PEG VC0/VCp Remap Registers Table 2-11.
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Processor Configuration Registers Table 2-11. MMI and PEG VC0/VCp Remap Register Address Map (Sheet 2 of 2) 2.15.
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Processor Configuration Registers 2.15.2 CAP_REG—Capability Register This register reports general DMA remapping hardware capabilities. B/D/F/Type: Address Offset: Reset Value: Access: 0/0/0/VC0PREMAP 8–Fh 00C9008020630272h RO Bit Attr Reset Value 63:56 RO 00h 55 RO 1b DMA Write Draining (DWD) 0 = On IOTLB invalidations, hardware does not support draining of translated DMA writes queued within the root complex.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 23 22 RO RO Reset Value Description 0b Isochrony (Isoch) 0 = Indicates this DMA-remapping hardware unit has no critical isochronous requesters in its scope. 1 = Indicates this DMA-remapping hardware unit has one or more critical isochronous requesters in its scope. To ensure isochronous performance, software must ensure invalidation operations do not impact active DMA streams.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 6 5 RO RO Reset Value Description 1b Protected High-Memory Region (PHMR) 0 = Indicates protected high-memory region not supported. 1 = Indicates protected high-memory region is supported. DMA-remapping hardware implementations on Intel TXT platforms supporting main memory above 4 GB are required to support protected highmemory region.
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Processor Configuration Registers 2.15.3 ECAP_REG—Extended Capability Register This register reports DMA-remapping hardware extended capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 63:32 RO 00000000 h Description Reserved 31:24 RO 00h Number of IOTLB Invalidation Units (NIU) This field indicates a value of N-1, where N is the number of IOTLB invalidation units supported by hardware.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value Description 2 RO 0b Device IOTLB Support (DI) 0 = Hardware does not support device- IOTLBs. 1 = Hardware supports Device-IOTLBs. Implementations reporting this field as Set must also support Queued Invalidation (QI = 1b). 1 RO 0b Queued Invalidation Support (QI) 0 = Hardware does not support queued invalidations. 1 = Hardware supports queued invalidations.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 30 29 28 27 192 Attr WO W W WO 0/0/0/VC0PREMAP 18–1Bh 00000000h W, WO, RO Reset Value Description 0b Set Root Table Pointer (SRTP) Software sets this field to set/update the root-entry table pointer used by hardware. The root-entry table pointer is specified through the Root-entry Table Address register.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 26 25 24 Datasheet, Volume 2 Attr W W W 0/0/0/VC0PREMAP 18–1Bh 00000000h W, WO, RO Reset Value Description 0b Queued Invalidation Enable (QIE) This field is valid only for implementations supporting queued invalidations. Software writes to this field to enable or disable queued invalidations. 0 = Disable queued invalidations. 1 = Enable use of queued invalidations.
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Processor Configuration Registers 2.15.5 GSTS_REG—Global Status Register This register reports general DMA-remapping hardware status. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31 30 29 28 27 RO RO RO RO RO Reset Value Description 0b Translation Enable Status (TES) This field indicates the status of DMA-remapping hardware.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.15.6 Attr 0/0/0/VC0PREMAP 1C–1Fh 00000000h RO Reset Value Description Compatibility Format Interrupt Status (CFIS) This field indicates the status of Compatibility format interrupts on Intel 64 implementations supporting interrupt-remapping. The value reported in this field is applicable only when interrupt-remapping is enabled and Legacy interrupt mode is active. 0 = Compatibility format interrupts are blocked.
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Processor Configuration Registers 2.15.7 CCMD_REG—Context Command Register Register to manage context cache. The act of writing the uppermost byte of the CCMD_REG with ICC field set causes the hardware to perform the context-cache invalidation.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr 0/0/0/VC0PREMAP 28–2Fh 0000000000000000h W, RW, RO Reset Value Description Context Actual Invalidation Granularity (CAIG) Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field). The following are the encodings for the CAIG field: 00 = Reserved 01 = Global Invalidation performed.
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Processor Configuration Registers 2.15.8 FSTS_REG—Fault Status Register This register indicates the primary fault logging status. The VTd specification describes hardware behavior for primary fault logging. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 31:16 RO 0000h Description Reserved Fault Record Index (FRI) This field is valid only when the PPF field is set.
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Processor Configuration Registers 2.15.9 FECTL_REG—Fault Event Control Register This register specifies the fault event interrupt message control bits. The VTd specification describes hardware handling of fault events. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31 Datasheet, Volume 2 Attr RW 0/0/0/VC0PREMAP 38–3Bh 80000000h RW, RO Reset Value Description 1b Interrupt Mask (IM) 0 = No masking of interrupt.
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Processor Configuration Registers 2.15.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.15.11 Attr 0/0/0/VC0PREMAP 3C–3Fh 00000000h RO, RW Reset Value Description 31:16 RO 0000h Extended Interrupt Message Data (EIMD) This field is valid only for implementations supporting 32-bit MSI data fields. Hardware implementations supporting only 16-bit MSI data may treat this field as read-only (0).
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Processor Configuration Registers 2.15.13 AFLOG_REG—Advanced Fault Log Register This register specifies the base address of memory-resident fault-log region. This register is treated as read-only (0) for implementations not supporting advanced translation fault logging (AFL field reported as 0 in the Capability register). This register is sticky and can be cleared only through a powergood reset or using software clearing the RW1C fields by writing a 1.
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Processor Configuration Registers 2.15.14 PMEM_REG—Protected Memory Enable Register This register enables the DMA protected memory regions setup through the PLMBASE, PLMLIMT, PHMBASE, PHMLIMIT registers. When LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO). When LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated RW).
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Processor Configuration Registers 2.15.15 PLMBASE_REG—Protected Low-Memory Base Register This register is used to setup the base address of DMA protected low-memory region. The register must be setup before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. When LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO). When LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated RW).
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Processor Configuration Registers 2.15.16 PLMLIMIT_REG—Protected Low-Memory Limit Register Register to setup the limit address of DMA protected low-memory region. This register must be setup before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. When LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO). When LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated RW).
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Processor Configuration Registers 2.15.17 PHMBASE_REG—Protected High-Memory Base Register This register is used to setup the base address of DMA protected high-memory region. This register must be setup before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. When LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO). When LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated RW).
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Processor Configuration Registers 2.15.18 PHMLIMIT_REG—Protected High-Memory Limit Register Register to setup the limit address of DMA protected high-memory region. This register must be setup before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. When LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO). When LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated RW).
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Processor Configuration Registers 2.15.20 IQT_REG—Invalidation Queue Tail Register Register indicating the invalidation tail head. This register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: 2.15.
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Processor Configuration Registers 2.15.22 ICS_REG—Invalidation Completion Status Register This register reports the completion status of invalidation wait descriptor with Interrupt Flag (IF) Set. This register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: 2.15.
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Processor Configuration Registers 2.15.24 IEDATA_REG—Invalidation Event Data Register Register specifying the Invalidation Event interrupt message data. This register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.15.
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Processor Configuration Registers 2.15.26 IEUADDR_REG—Invalidation Event Upper Address Register This register specifies the Invalidation Event interrupt message upper address. This register is treated as reserved by implementations reporting both Queued Invalidation (QI) and Extended Interrupt Mode (EIM) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31:0 2.15.
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Processor Configuration Registers 2.15.28 IVA_REG—Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register. This register is a write-only register. Value returned on reads of this register is undefined. There is an IVA_REG for each IOTLB Invalidation unit supported by hardware.
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Processor Configuration Registers 2.15.29 IOTLB_REG—IOTLB Invalidate Register Register to control page-table entry caching. The act of writing the upper byte of the IOTLB_REG with IVT field set causes the hardware to perform the IOTLB invalidation. There is an IOTLB_REG for each IOTLB Invalidation unit supported by hardware.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr 0/0/0/VC0PREMAP 108–10Fh 0000000000000000h RW, RO Reset Value Description IOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granularity at which an invalidation request was processed through this field at the time of reporting invalidation completion (by clearing the IVT field). The following are the encodings for the IAIG field. 000 = Reserved.
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Processor Configuration Registers 2.15.30 FRCD_REG—Fault Recording Registers This registers records DMA-remapping fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register. This register is relevant only for primary fault logging. These registers are sticky and can be cleared only through powergood reset or using software clearing the RW1C fields by writing a 1.
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Processor Configuration Registers 2.15.31 VTCMPLRESR—VT Completion Resource Dedication This register provides a programmable interface to dedicate the DMI Completion Tracking Queue resources to DMI VC0 Read, DMI VC0 Write, DMI VC1 and DMI VCp VT fetch and PEG Completion Tracking Queue resources to PEG VC0 read and PEG VC0 write VT fetch.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 3:0 2.15.32 Attr RW-L 0/0/0/VC0PREMAP F00–F03h 00060000h RW-L, RO Reset Value 0h Description DMI VC0 Read VT Completion Tracking Queue Resource Threshold (DMIVC0RDCTQRT) This field provides a 1-based minimum threshold value used to throttle DMI VC0 Read VT fetch.
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Processor Configuration Registers 2.15.33 PEGVTCMPLRESR—PEG VT Completion Resource Dedication This register provides a programmable interface to dedicate the PEG0 and PEG1 Completion Tracking Queue resources to PEG0 VC0 read, PEG0 VC0 write, PEG1 VC0 read and PEG1 VC0 write VT fetch.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 14:10 9:5 4:0 218 Attr RO RW-L RW-L 0/0/0/VC0PREMAP F08–F0Bh 20004000h RW-L, RO Reset Value Description 10000b PEG0 VT Completion Tracking Queue Resource Available (PEG0VTCTRA) Number of entries available in PEG0 VT Completion Tracking Queue. 1-based. The values programmed in the fields below must not be greater than the value advertised in this field.
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Processor Configuration Registers 2.15.34 VTPOLICY—DMA Remap Engine Policy Control This registers contains all the policy bits related to the DMA remap engine. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31 Attr RW-L 0/0/0/VC0PREMAP FFC–FFFh 00000000h RW-L Reset Value Description 0b DMA Remap Engine Policy Lock-Down (DMAR_LCKDN) This register bit protects all the DMA remap engine specific policy configuration registers.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 12 RW-L 0b PEG1 L3 TLBR (PEG1L3TLBR) This is a TLBR policy bit for PEG1VC0 L3 Cache 0b PEG1 TLB Disable (PEG1TLBDIS) 1 = PEG1VC0 TLBs are disabled and each GPA request will result in a miss and a root walk will be requested from VTd Dispatcher 0 = Normal mode (default), PEG1VC0 TLBs are enabled and normal hit/miss flows are followed 0b DMIVC0TLBDisable (DMIVC0 TLB Disable) 1 = DMIVC0P TLBs are
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Processor Configuration Registers 2.16 DMI VC1 REMAP Registers Table 2-12.
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Processor Configuration Registers 2.16.1 VER_REG—Version Register This register reports the architecture version supported. Backward compatibility for the architecture is maintained with new revision numbers, allowing software to load DMAremapping drivers written for prior architecture versions.
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Processor Configuration Registers 2.16.2 CAP_REG—Capability Register This register reports general DMA remapping hardware capabilities. B/D/F/Type: Address Offset: Reset Value: Access: 0/0/0/DMIVC1REMAP 8–Fh 00C9008020E30272h RO Bit Attr Reset Value 63:56 RO 00h 55 RO Description Reserved 1b DMA Read Draining (DRD) 0 = On IOTLB invalidations, hardware does not support draining of DMA read requests. 1 = On IOTLB invalidations, hardware supports draining of DMA read requests.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 23 22 RO RO Reset Value Description 1b Isochrony (Isoch) 0 = Indicates this DMA-remapping hardware unit has no critical isochronous requesters in its scope. 1 = Indicates this DMA-remapping hardware unit has one or more critical isochronous requesters in its scope. To ensure isochronous performance, software must ensure invalidation operations do not impact active DMA streams from such requesters.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 6 RO 1b Protected High-Memory Region (PHMR) 0 = Protected high-memory region not supported. 1 = Protected high-memory region is supported. 5 RO 1b Protected Low-Memory Region (PLMR) 0 = Protected low-memory region not supported. 1 = Protected low-memory region is supported.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Reset Value Description 17:8 RO 010h Invalidation Unit Offset (IVO) This field specifies the location to the first IOTLB registers relative to the register base address of this DMA-remapping hardware unit. If the register base address is X, and the value reported in this field is Y, the address for the first IOTLB register is calculated as X+(16*Y).
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Processor Configuration Registers 2.16.4 GCMD_REG—Global Command Register This register controls DMA-remapping hardware. If multiple control fields in this register need to be modified, software must serialize the modifications through multiple writes to this register.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 28 27 26 25 228 Attr W W RO RO 0/0/0/DMIVC1REMAP 18–1Bh 00000000h W, RO Reset Value Description 0b Enable Advanced Fault Logging (EAFL) This field is valid only for implementations supporting advanced fault logging. Software writes to this field to request hardware to enable or disable advanced fault logging. 0 = Disable advanced fault logging.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 24 Datasheet, Volume 2 Attr RO 0/0/0/DMIVC1REMAP 18–1Bh 00000000h W, RO Reset Value Description 0b Set Interrupt Remap Table Pointer (SIRTP) This field is valid only for implementations supporting interrupt-remapping. Software sets this field to set/update the interrupt remapping table pointer used by hardware.
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Processor Configuration Registers 2.16.5 GSTS_REG—Global Status Register This register reports general DMA-remapping hardware status. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31 30 29 28 RO RO RO RO Reset Value Description 0b Translation Enable Status (TES) This field indicates the status of DMA-remapping hardware.
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Processor Configuration Registers 2.16.6 RTADDR_REG—Root-Entry Table Address Register This register provides the base address of the root-entry table. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr 0/0/0/DMIVC1REMAP 20–27h 0000000000000000h RW, RO Reset Value 63:12 RW 00000000 00000h 11:0 RO 000h Datasheet, Volume 2 Description Root Table Address (RTA) This register points to base of page aligned, 4 KB-sized root-entry table in system memory.
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Processor Configuration Registers 2.16.7 CCMD_REG—Context Command Register This register manages context cache. The act of writing the uppermost byte of the CCMD_REG with ICC field set causes the hardware to perform the context-cache invalidation.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr 0/0/0/DMIVC1REMAP 28–2Fh 0000000000000000h RW-SC, RW, RO, W Reset Value Description Context Actual Invalidation Granularity (CAIG) Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field). The following are the encodings for the CAIG field: 00 = Reserved. 01 = Global Invalidation performed.
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Processor Configuration Registers 2.16.8 FSTS_REG—Fault Status Register This register indicates the various error status. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 31:16 RO 0000h Description Reserved Fault Record Index (FRI) This field is valid only when the PPF field is set. The FRI field indicates the index (from base) of the fault recording register to which the first pending fault was recorded when the PPF field was set by hardware.
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Processor Configuration Registers 2.16.9 FECTL_REG—Fault Event Control Register This register specifies the fault event interrupt message control bits. The VTd specification describes hardware handling of fault events. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31 Datasheet, Volume 2 Attr RW 0/0/0/DMIVC1REMAP 38-3Bh 80000000h RW, RO Reset Value Description 1b Interrupt Mask (IM) 0 = No masking of interrupt.
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Processor Configuration Registers 2.16.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.16.11 Attr 0/0/0/DMIVC1REMAP 3C–3Fh 00000000h RO, RW Reset Value Description 31:16 RO 0000h Extended Interrupt Message Data (EIMD) This field is valid only for implementations supporting 32-bit MSI data fields. Hardware implementations supporting only 16-bit MSI data may treat this field as read-only (0).
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Processor Configuration Registers 2.16.12 FEUADDR_REG—Fault Event Upper Address Register This register specifies the interrupt message upper address. The register is treated as reserved by implementations reporting Extended Interrupt Mode (EIM) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31:0 2.16.
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Processor Configuration Registers 2.16.14 PMEN_REG—Protected Memory Enable Register This register enables the DMA-protected memory regions set up through the PLMBASE, PLMLIMT, PHMBASE, PHMLIMIT registers. This register is treated as RO for implementations not supporting protected memory regions (PLMR and PHMR fields reported as Clear in the Capability register). Protected memory regions may be used by software to securely initialize remapping structures in memory.
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Processor Configuration Registers 2.16.15 PLMBASE_REG—Protected Low-Memory Base Register This register is used to set up the base address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
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Processor Configuration Registers 2.16.16 PLMLIMIT_REG—Protected Low-Memory Limit Register This register is used to setup the limit address of DMA protected low-memory region below 4 GB. This register must be setup before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as 0 in the Capability register).
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Processor Configuration Registers 2.16.17 PHMBASE_REG—Protected High-Memory Base Register This register is used to set up the base address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
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Processor Configuration Registers 2.16.18 PHMLIMIT_REG—Protected High-Memory Limit Register This register is used to setup the limit address of DMA protected high-memory region. This register must be setup before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as 0 in the Capability register).
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Processor Configuration Registers 2.16.19 IQH_REG—Invalidation Queue Head Register This register indicates the invalidation queue head. This register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: 2.16.
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Processor Configuration Registers 2.16.21 IQA_REG—Invalidation Queue Address Register This register is used to configure the base address and size of the invalidation queue. The register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. When supported, writing to this register causes the Invalidation Queue Head and Invalidation Queue Tail registers to be reset to 0h.
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Processor Configuration Registers 2.16.23 IECTL_REG—Invalidation Event Control Register This register specifies the invalidation event interrupt control bits. This register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31 Datasheet, Volume 2 Attr RO 0/0/0/DMIVC1REMAP A0–A3h 00000000h RO Reset Value Description 0b Interrupt Mask (IM) 0 = No masking of interrupt.
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Processor Configuration Registers 2.16.24 IEDATA_REG—Invalidation Event Data Register This register specifies the Invalidation Event interrupt message data. This register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.16.
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Processor Configuration Registers 2.16.26 IEUADDR_REG—Invalidation Event Upper Address Register This register specifies the Invalidation Event interrupt message upper address. This register is treated as reserved by implementations reporting both Queued Invalidation (QI) and Extended Interrupt Mode (EIM) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31:0 2.16.
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Processor Configuration Registers 2.16.28 IVA_REG—Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register. The register is a writeonly register. Value returned on reads of this register is undefined. B/D/F/Type: Address Offset: Reset Value: Access: Bit Reset Value Description Address (ADDR) Software provides the DMA address that needs to be page-selectively invalidated.
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Processor Configuration Registers 2.16.29 IOTLB_REG—IOTLB Invalidate Register This register is used to invalidate IOTLB. The act of writing the upper byte of the IOTLB_REG with IVT field set causes the hardware to perform the IOTLB invalidation.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Reset Value Description IOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granularity at which an invalidation request was processed through this field at the time of reporting invalidation completion (by clearing the IVT field). The following are the encodings for the IAIG field. 000 = Reserved. This indicates hardware detected an incorrect invalidation request and ignored the request.
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Processor Configuration Registers 2.16.30 FRCD_REG—Fault Recording Registers These Registers record fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register. This register is relevant only for primary fault logging. These registers are sticky and can be cleared only through powergood reset or using software clearing the RWC fields by writing a 1.
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Processor Configuration Registers 2.16.31 VTPOLICY—DMA Remap Engine Policy Control This registers contains all the policy bits related to the DMA remap engine. B/D/F/Type: Address Offset: Reset Value: Access: Bit Reset Value Description DMA Remap Engine Policy Lock-Down (DMAR_LCKDN) This bit protects all the DMA remap engine specific policy configuration registers. Once this bit is set by software all the DMA remap engine registers within the range 0xF00 to 0xFFC will be read-only.
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Processor Configuration Registers 2.17 Graphics Control Registers 2.17.1 MGGC—Graphics Control Register All the Bits in this register are Intel TXT lockable. B/D/F/Type: Address Offset: Reset Value: Access: 0/2/0/PCI 52–53h 0030h RO Bit Attr Reset Value 15:12 RO 0h Reserved 0h GTT Graphics Memory Size (GGMS) This field is used to select the amount of main memory that is pre-allocated to support the Internal Graphics Translation Table.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.17.2 Attr 0/2/0/PCI 52–53h 0030h RO Reset Value Description 1 RO 0b IGD VGA Disable (IVD) 0 = Enable. Device 2 (IGD) claims VGA memory and IO cycles, the SubClass Code within Device 2 Class Code register is 00. 1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and IO), and the Sub- Class Code field within Device 2 function 0 Class Code register is 80.
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Processor Configuration Registers 2.18 GFXVTBAR Registers Table 2-13.
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Processor Configuration Registers 2.18.1 VER_REG—Version Register This register reports the architecture version supported. Backward compatibility for the architecture is maintained with new revision numbers, allowing software to load DMAremapping drivers written for prior architecture versions. B/D/F/Type: Address Offset: Reset Value: Access: 256 0/2/0/GFXVTBAR 0–3h 00000010h RO Bit Attr Reset Value 31:8 RO 000000h 7:4 RO 1h Major Version number (MAX) Indicates supported architecture version.
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Processor Configuration Registers 2.18.2 CAP_REG—Capability Register This register reports general DMA remapping hardware capabilities. B/D/F/Type: Address Offset: Reset Value: Access: 0/2/0/GFXVTBAR 8–Fh 00C0000020230272h RO Bit Attr Reset Value 63:56 RO 00h 55 RO Description Reserved 1b DMA Read Draining (DRD) 0 = On IOTLB invalidations, hardware does not support draining of translated DMA read requests queued within the root complex.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 23 22 RO RO Reset Value Description 0b Isochrony (ISOCH) 0 = Indicates this DMA-remapping hardware unit has no critical isochronous requesters in its scope. 1 = Indicates this DMA-remapping hardware unit has one or more critical isochronous requesters in its scope. To ensure isochronous performance, software must ensure invalidation operations do not impact active DMA streams from such requesters.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 6 5 RO RO Reset Value Description 1b Protected High-Memory Region (PHMR) 0 = Indicates protected high-memory region is not supported. 1 = Indicates protected high-memory region is supported. DMA-remapping hardware implementations on Intel TXT platforms supporting main memory above 4 GB are required to support protected highmemory region.
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Processor Configuration Registers 2.18.3 ECAP_REG—Extended Capability Register This register reports DMA-remapping hardware extended capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 63:24 RO 0h Reserved Maximum Handle Mask Value (MHMV) The value in this field indicates the maximum supported value for the Handle Mask (HM) field in the interrupt entry cache invalidation descriptor (iec_inv_dsc). This field is valid only when the IR field is reported as Set.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 0 2.18.4 Attr RO 0/2/0/GFXVTBAR 10–17h 0000000000001000h RO Reset Value Description 0b Coherency (C) This field indicates if hardware access to the root, context, page-table and interrupt-remap structures are coherent (snooped) or not. 0 = Indicates hardware accesses to remapping structures are noncoherent. 1 = Indicates hardware accesses to remapping structures are coherent.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 30 29 28 27 262 Attr W RO RO W 0/2/0/GFXVTBAR 18–1Bh 00000000h W, RO, RW Reset Value Description 0b Set Root Table Pointer (SRTP) Software sets this field to set/update the root-entry table pointer used by hardware. The root-entry table pointer is specified through the Root-entry Table Address register.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 26 25 24 Datasheet, Volume 2 Attr RO RO RO 0/2/0/GFXVTBAR 18–1Bh 00000000h W, RO, RW Reset Value Description 0b Queued Invalidation Enable (QIE) This field is valid only for implementations supporting queued invalidations. Software writes to this field to enable or disable queued invalidations. 0 = Disable queued invalidations. 1 = Enable use of queued invalidations.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.18.5 Attr 0/2/0/GFXVTBAR 18–1Bh 00000000h W, RO, RW Reset Value Description Compatibility Format Interrupt (CFI) This field is valid only for Intel 64 implementations supporting interruptremapping. Software writes to this field to enable or disable Compatibility Format interrupts on Intel 64 platforms. The value in this field is effective only when interrupt-remapping is enabled and Legacy Interrupt Mode is active.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 27 26 25 24 Datasheet, Volume 2 Attr RO RO RO RO 0/2/0/GFXVTBAR 1C–1Fh 00000000h RO Reset Value Description 0b Write Buffer Flush Status (WBFS) This field is valid only for implementations requiring write buffer flushing. This field indicates the status of the write buffer flush command. It is Set by hardware when software sets the WBF field in the Global Command register.
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Processor Configuration Registers 2.18.6 RTADDR_REG—Root-Entry Table Address Register This register provides the base address of root-entry table. B/D/F/Type: Address Offset: Reset Value: Access: 2.18.7 0/2/0/GFXVTBAR 20–27h 0000000000000000h RO, RW Bit Attr Reset Value 63:36 RO 0000000h 35:12 RW 000000h 11:0 RO 000h Description Reserved Root table address (RTA) This register points to base of page aligned, 4 KB-sized root-entry table in system memory.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 62:61 Attr RW 0/2/0/GFXVTBAR 28–2Fh 0800000000000000h RW, RO Reset Value Description 00b Context Invalidation Request Granularity (CIRG) Software provides the requested invalidation granularity through this field when setting the ICC field: 00 = Reserved. 01 = Global Invalidation request. 10 = Domain-selective invalidation request. The target domain-id must be specified in the DID field.
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Processor Configuration Registers 2.18.8 FSTS_REG—Fault Status Register This register indicates the various error statuses. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 31:16 RO 0000h Description Reserved Fault Record Index (FRI) This field is valid only when the PPF field is Set. The FRI field indicates the index (from base) of the fault recording register to which the first pending fault was recorded when the PPF field was Set by hardware.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Datasheet, Volume 2 Attr 0/2/0/GFXVTBAR 34–37h 00000000h RO, RW1C-S, RO-V-S Reset Value Description 1 RO-V-S 0b Primary Pending Fault (PPF) This field indicates if there are one or more pending faults logged in the fault recording registers. Hardware computes this field as the logical OR of Fault (F) fields across all the fault recording registers of this remapping hardware unit.
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Processor Configuration Registers 2.18.9 FECTL_REG—Fault Event Control Register This register specifies the fault event interrupt message control bits. The VTd specification describes hardware handling of fault events. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31 270 Attr RW 0/2/0/GFXVTBAR 38–3Bh 80000000h RO, RW Reset Value Description 1b Interrupt Mask (IM) 0 = No masking of interrupts.
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Processor Configuration Registers 2.18.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.18.11 Attr 0/2/0/GFXVTBAR 3C–3Fh 00000000h RO, RW Reset Value Description 31:16 RO 0000h Extended Interrupt Message Data (EID) This field is valid only for implementations supporting 32-bit interrupt data fields. Hardware implementations supporting only 16-bit interrupt data treat this field as reserved.
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Processor Configuration Registers 2.18.13 AFLOG_REG—Advanced Fault Log Register This register specifies the base address of memory-resident fault-log region. This register is treated as read-only (0) for implementations not supporting advanced translation fault logging (AFL field reported as 0 in the Capability register).
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Processor Configuration Registers 2.18.14 PMEN_REG—Protected Memory Enable Register This register enables the DMA-protected memory regions set up through the PLMBASE, PLMLIMT, PHMBASE, PHMLIMIT registers. This register is always treated as RO (0) for implementations not supporting protected memory regions (PLMR and PHMR fields reported as 0 in the Capability register). Protected memory regions may be used by software to securely initialize remapping structures in memory.
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Processor Configuration Registers 2.18.15 PLMBASE_REG—Protected Low Memory Base Register This register is used to set up the base address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. When the LT CMD.LOCK.PMRC command is invoked, this register is locked (treated as RO). When the LT CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated as RW).
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Processor Configuration Registers 2.18.16 PLMLIMIT_REG—Protected Low Memory Limit Register This register is used to set up the limit address of DMA-protected low-memory region below 4 GB. The register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. When the LT CMD.LOCK.PMRC command is invoked, this register is locked (treated as RO). When the LT CMD.UNLOCK.
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Processor Configuration Registers 2.18.17 PHMBASE_REG—Protected High Memory Base Register This register is used to set up the base address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. When the LT CMD.LOCK.PMRC command is invoked, this register is locked (treated as RO). When the LT CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated as RW).
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Processor Configuration Registers 2.18.18 PHMLIMIT_REG—Protected High Memory Limit Register This register is used to set up the limit address of DMA-protected high-memory region. The register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. When the LT CMD.LOCK.PMRC command is invoked, this register is locked (treated as RO). When the LT CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated as RW).
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Processor Configuration Registers 2.18.19 IQH_REG—Invalidation Queue Head Register This register indicates the invalidation queue head. The register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: 2.18.
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Processor Configuration Registers 2.18.21 IQA_REG—Invalidation Queue Address Register This register is used to configure the base address and size of the invalidation queue. The register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. When supported, writing to this register causes the Invalidation Queue Head and Invalidation Queue Tail registers to be reset to 0h. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.18.
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Processor Configuration Registers 2.18.23 IECTL_REG—Invalidation Completion Event Control Register This register specifies the invalidation event interrupt control bits. The register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Bit 31 280 Attr RO 0/2/0/GFXVTBAR A0–A3h 80000000h RO Reset Value Description 1b Interrupt Mask (IM) 0 = No masking of interrupt.
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Processor Configuration Registers 2.18.24 IEDATA_REG—Invalidation Completion Event Data Register This register specifies the Invalidation Event interrupt message data. The register is treated as reserved by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.18.
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Processor Configuration Registers 2.18.26 IRTA_REG—Interrupt Remapping Table Address Register This register provides the base address of Interrupt remapping table. The register is treated as reserved by implementations reporting Interrupt Remapping (IR) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Bit 63:12 282 Attr RO 0/2/0/GFXVTBAR B8–BFh 0000000000000000h RO Reset Value 00..
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Processor Configuration Registers 2.18.27 IVA_REG—Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register. The register is a writeonly register. A value returned on a read of this register is undefined.
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Processor Configuration Registers 2.18.28 IOTLB_REG—IOTLB Invalidate Register This register is used to invalidate IOTLB. The act of writing the upper byte of the IOTLB_REG with the IVT field Set causes the hardware to perform the IOTLB invalidation. B/D/F/Type: Address Offset: Reset Value: Access: Bit 63 62:60 59:57 284 Attr RW RW RO 0/2/0/GFXVTBAR 108–10Fh 0200000000000000h RW, RO Reset Value Description 0b Invalidate IOTLB (IVT) Software requests IOTLB invalidation by setting this field.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: 0/2/0/GFXVTBAR 108–10Fh 0200000000000000h RW, RO Bit Attr Reset Value 56:50 RO 00h 49 48 RW RW Reserved 0b Drain Reads (DR) This field is ignored by hardware if the DRD field is reported as clear in the Capability register.
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Processor Configuration Registers 2.18.29 FRCD_REG—Fault Recording Registers Registers to record fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register. This register is relevant only for primary fault logging. These registers are sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1.
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Processor Configuration Registers 2.18.30 VTPOLICY—VT Policy Register B/D/F/Type: Address Offset: Reset Value: Access: Bit Reset Value Description 31 RW-O 0b DMA Remap Engine Policy Lock-Down (DMAR_LCKDN) This register bit protects all the DMA remap engine specific policy configuration registers. Once this bit is set by software, all the DMA remap engine registers within the range F00h to FFCh will be read-only. This bit can only be clear through platform reset.
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Processor Configuration Registers 2.19 PCI Device 6 Registers Note: Device 6 is not supported on all SKUs. Table 2-14.
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Processor Configuration Registers Table 2-14. PCI Device 6 Register Address Map (Sheet 2 of 2) 2.19.
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Processor Configuration Registers 2.19.2 DID6—Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: 2.19.3 0/6/0/PCI 2–3h 0043h RO Bit Attr Reset Value 15:4 RO 004h 3:2 RO 00b Device Identification Number Hardware controlled (DID6HW) Identifier assigned to the device 6 (virtual PCI-to-PCI bridge, PCI Express Graphics port).
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Datasheet, Volume 2 0/6/0/PCI 4–5h 0000h RO, RW Bit Attr Reset Value 7 RO 0b Reserved Not Applicable or Implemented. Hardwired to 0. Description 6 RW 0b Parity Error Response Enable (PERRE) Controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set. 0 = Master Data Parity Error bit in PCI Status register can NOT be set.
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Processor Configuration Registers 2.19.4 PCISTS6—PCI Status Register This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge embedded within the GMCH. B/D/F/Type: Address Offset: Reset Value: Access: 292 0/6/0/PCI 6–7h 0010h RO, RW1C Bit Attr Reset Value Description 15 RO 0b Detected Parity Error (DPE) Not Applicable or Implemented. Hardwired to 0.
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Processor Configuration Registers 2.19.5 RID6—Revision Identification Register This register contains the revision number of the processor. The Revision ID (RID) is a traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function. This register contains the revision number of Device 6. These bits are read only and writes to this register have no effect.
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Processor Configuration Registers 2.19.7 CL6—Cache Line Size Register B/D/F/Type: Address Offset: Reset Value: Access: 2.19.8 0/6/0/PCI Ch 00h RW Bit Attr Reset Value 7:0 RW 00h Description Cache Line Size (Scratch pad) Implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no impact on any PCI Express device functionality. HDR6—Header Type Register This register identifies the header layout of the configuration space.
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Processor Configuration Registers 2.19.10 SBUSN6—Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the "virtual" bridge (that is, to PCI Express-G). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express-G. B/D/F/Type: Address Offset: Reset Value: Access: 2.19.
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Processor Configuration Registers 2.19.12 IOBASE6—I/O Base Address Register This register controls the processor to PCI Express-G I/O access routing based on the following formula: IO_BASE  address  IO_LIMIT Only upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be aligned to a 4 KB boundary. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.19.
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Processor Configuration Registers 2.19.14 SSTS6—Secondary Status Register SSTS6 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI bridge embedded within GMCH.
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Processor Configuration Registers 2.19.15 MBASE6—Memory Base Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are readonly and return zeroes when read. This register must be initialized by the configuration software.
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Processor Configuration Registers 2.19.16 MLIMIT6—Memory Limit Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE  address  MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are readonly and return zeroes when read. This register must be initialized by the configuration software.
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Processor Configuration Registers 2.19.17 PMBASE6—Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
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Processor Configuration Registers 2.19.18 PMLIMIT6—Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
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Processor Configuration Registers 2.19.19 PMBASEU6—Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation.
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Processor Configuration Registers 2.19.20 PMLIMITU6—Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation.
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Processor Configuration Registers 2.19.22 INTRLINE6—Interrupt Line Register This register contains interrupt line routing information. The device itself does not use this value, rather it is used by device drivers and operating systems to determine priority and vector information. B/D/F/Type: Address Offset: Reset Value: Access: Bit 7:0 2.19.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 9 RO 0b Secondary Discard Timer (SDT) Not Applicable or Implemented. Hardwired to 0. 8 RO 0b Primary Discard Timer (PDT) Not Applicable or Implemented. Hardwired to 0. 7 RO 0b Fast Back-to-Back Enable (FB2BEN) Not Applicable or Implemented. Hardwired to 0. 6 RW 0b Secondary Bus Reset (SRESET) Setting this bit triggers a hot reset on the corresponding PCI Express Port.
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Processor Configuration Registers 2.19.25 PM_CAPID6—Power Management Capabilities Register B/D/F/Type: Address Offset: Reset Value: Access: Bit 306 Attr 0/6/0/PCI 80–83h C8039001h RO Reset Value Description PME Support (PMES) This field indicates the power states in which this device may indicate PME wake using PCI Express messaging. D0, D3hot & D3cold. This device is not required to do anything to support D3hot & D3cold, it simply must report that those states are supported.
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Processor Configuration Registers 2.19.26 PM_CS6—Power Management Control/Status Register B/D/F/Type: Address Offset: Reset Value: Access: 0/6/0/PCI 84–87h 00000008h RO, RW, RW-S Bit Attr Reset Value 31:16 RO 0000h 15 RO 0b 14:13 RO 00b Data Scale (DSCALE) Indicates that this device does not support the power management data register. 12:9 RO 0h Data Select (DSEL) Indicates that this device does not support the power management data register.
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Processor Configuration Registers 2.19.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. However, it is necessary because Microsoft will test for its presence. B/D/F/Type: Address Offset: Reset Value: Access: 2.19.
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Processor Configuration Registers 2.19.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability.
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Processor Configuration Registers 2.19.30 MC—Message Control Register System software can modify bits in this register, but the device is prohibited from doing so. If the device writes the same message multiple times, only one of those messages is ensured to be serviced. If all of them must be serviced, the device must not generate the same message again until the driver services the earlier one.
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Processor Configuration Registers 2.19.31 MA—Message Address Register B/D/F/Type: Address Offset: Reset Value: Access: 2.19.32 0/6/0/PCI 94–97h 00000000h RW, RO Bit Attr Reset Value Description 31:2 RW 00000000 h Message Address (MA) This field is used by system software to assign an MSI address to the device. The device handles an MSI by writing the padded contents of the MD register to this address.
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Processor Configuration Registers 2.19.34 PEG_CAP—PCI Express-G Capabilities Register This register indicates PCI Express device capabilities. B/D/F/Type: Address Offset: Reset Value: Access: 2.19.35 0/6/0/PCI A2–A3h 0142h RO, RW-O Bit Attr Reset Value 15 RO 0b Reserved 14 RO 0b Reserved: Reserved for TCS Routing Supported. 13:9 RO 00h Description Interrupt Message Number (IMN) Not Applicable or Implemented. Hardwired to 0.
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Processor Configuration Registers 2.19.36 DCTL—Device Control Register This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register.
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Processor Configuration Registers 2.19.37 DSTS—Device Status Register This register reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 15:6 RO 000h Description Reserved and Zero For future R/WC/S implementations; software must use 0 for writes to bits.
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Processor Configuration Registers 2.19.38 LCAP—Link Capabilities Register This register indicates PCI Express device specific capabilities. B/D/F/Type: Address Offset: Reset Value: Access: 0/6/0/PCI AC–AFh 03214C82h RO, RW-O Bit Attr Reset Value 31:24 RO 03h Port Number (PN) This field indicates the PCI Express port number for the given PCI Express link. Matches the value in Element Self Description[31:24].
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Reset Value Description L0s Exit Latency (L0SELAT) This field indicates the length of time this Port requires to complete the transition from L0s to L0.
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Processor Configuration Registers 2.19.39 LCTL—Link Control Register This register allows control of PCI Express link.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 5 RW-SC Reset Value Description 0b Retrain Link (RL) 0 = Normal operation. 1 = Full Link retraining is initiated by directing the Physical Layer LTSSM from L0, L0s, or L1 states to the Recovery state. This bit always returns 0 when read. This bit is cleared automatically (no need to write a 0). It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register.
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Processor Configuration Registers 2.19.40 LSTS—Link Status Register This register indicates PCI Express link status.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 3:0 Attr RO 0/6/0/PCI B2–B3h 1000h RO, RW1C Reset Value Description 0h Current Link Speed (CLS) This field indicates the negotiated Link speed of the given PCI Express Link. Defined encodings are: 0001b = 2.5 GT/s PCI Express Link 0010b = 5.0 GT/s PCI Express Link All other encodings are reserved. The value in this field is undefined when the Link is not up 2.19.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit Datasheet, Volume 2 Attr 0/6/0/PCI B4–B7h 00040000h RW-O, RO Reset Value Description 5 RO 0b Reserved for Hot-plug Surprise (HPS) When set to 1, this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability.
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Processor Configuration Registers 2.19.42 SLOTCTL—Slot Control Register Note: Hot Plug is not supported on the platforms. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 15:13 RO 000b Description Reserved 12 RO 0b Reserved for Data Link Layer State Changed Enable (DLLSCE) If the Data Link Layer Link Active capability is implemented, when set to 1b, this field enables software notification when Data Link Layer Link Active field is changed.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Bit 7:6 5 Datasheet, Volume 2 Attr RO RO 0/6/0/PCI B8–B9h 0000h RO, RW Reset Value Description 00b Reserved for Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.
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Processor Configuration Registers 2.19.43 SLOTSTS—Slot Status Register Note: Hot Plug is not supported on the platform. B/D/F/Type: Address Offset: Reset Value: Access: Bit Attr Reset Value 15:9 RO 0000000b Reserved. MBZ For future R/WC/S implementations; software must use 0 for writes to bits. 0b Reserved for Data Link Layer State Changed (DLLSC) This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed.
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Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Datasheet, Volume 2 0/6/0/PCI BA–BBh 0000h RO, RW1C Bit Attr Reset Value Description 2 RO 0b Reserved for MRL Sensor Changed (MSC) If an MRL sensor is implemented, this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented, this bit must not be set.
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Processor Configuration Registers 2.19.44 RCTL—Root Control Register This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link. Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register.
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Processor Configuration Registers 2.19.45 RSTS—Root Status This register provides information about PCI Express Root Complex specific parameters. B/D/F/Type: Address Offset: Reset Value: Access: 2.19.46 0/6/0/PCI C0–C3h 00000000h RO, RW1C Bit Attr Reset Value 31:18 RO 0000h Reserved: MBZ For future R/WC/S implementations; software must use 0 for writes to bits. Description 17 RO 0b PME Pending (PMEP) This bit indicates that another PME is pending when the PME Status bit is set.
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Processor Configuration Registers 2.20 Device 6 Extended Configuration Registers Note: Device 6 is not supported on all SKUs. Table 2-15. Device 6 Extended Configuration Register Address Map Address Offset 2.20.
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Processor Configuration Registers 2.20.2 PVCCAP2—Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port. B/D/F/Type: Address Offset: Reset Value: Access: Bit 2.20.3 Attr 0/6/0/MMR 108–10Bh 0000_0000h RO Reset Value Description VC Arbitration Table Offset (VCATO) This field indicates the location of the VC Arbitration Table.
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Processor Configuration Registers 2.20.
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Processor Configuration Registers 2.20.5 VC0RCTL—VC0 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type: Address Offset: Reset Value: Access: 0/6/0/MMR 114–117h 800000FFh RO, RW Bit Attr Reset Value 31 RO 1b VC0 Enable (VC0E) For VC0 this is hardwired to 1 and read only as VC0 can never be disabled. 30:27 RO 0h Reserved 26:24 RO 000b 23:20 RO 0h VC0 ID (VC0ID) Assigns a VC ID to the VC resource.
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Processor Configuration Registers 2.20.6 VC0RSTS—VC0 Resource Status Register B/D/F/Type: Address Offset: Reset Value: Access: 2.21 0/6/0/MMR 11A–11Bh 0002h RO Bit Attr Reset Value 15:2 RO 0000h Description Reserved: MBZ 1 RO 1b VC0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling). This bit indicates the status of the process of Flow Control initialization.
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Processor Configuration Registers 2.21.1 TXT.DID—TXT Device ID Register This register contains the TXT ID for the processor. B/D/F/Type: Address Offset: Reset Value: Access: 2.21.2 0/0/0/TXT Specific 110–117h 00000003A0008086h RO Bit Attr Reset Value 63:48 RO 0000h Reserved 47:32 RO 0003h Revision ID (TXT.RID) For the initial stepping of the component, the value is 0001h. The value is a bit-mask for compatibility with prior steppings. 31:16 RO A00h Device ID (TXT.
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Processor Configuration Registers 2.21.3 TXT.PUBLIC.KEY.LOWER—TXT Processor Public Key Hash Lower Half Register These registers hold the hash of the processor's public key. It is 256 bits (32 Bytes). B/D/F/Type: Address Offset: Reset Value: Access: Bit 127:0 2.21.4 Attr RO 0/0/0/TXT Specific 400–40Fh 73A13C69E7DCF24C384C652BA19DA250h RO Reset Value 73A13C69 E7DCF24 C384C652 BA19DA2 50h Description Public Key Hash Lower half (TXT.PUBLIC.
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Intel® QuickPath Architecture System Address Decode Register Description 3 Intel® QuickPath Architecture System Address Decode Register Description The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI specification as defined in the PCI Local Bus Specification, Revision 2.3, as well as the PCI Express* enhanced configuration mechanism as specified in the PCI Express Base Specification, Revision 1.1.
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Intel® QuickPath Architecture System Address Decode Register Description Table 3-1. Register Terminology (Sheet 2 of 2) Term 336 Description RWO Read/Write Once. A register bit with this attribute can be written to only once after power up. After the first write, the bit becomes read only. This attribute is applied on a bit by bit basis. For example, if the RWO attribute is applied to a 2 bit field, and only one bit is written, then the written bit cannot be rewritten (unless reset).
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Intel® QuickPath Architecture System Address Decode Register Description 3.2 Platform Configuration Structure The processor contains PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket. Bus number is derived by the maximum bus range setting and processor socket number.
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Intel® QuickPath Architecture System Address Decode Register Description 3.3 Detailed Configuration Space Maps Table 3-3.
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Intel® QuickPath Architecture System Address Decode Register Description Table 3-4.
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Intel® QuickPath Architecture System Address Decode Register Description Table 3-5.
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Intel® QuickPath Architecture System Address Decode Register Description Table 3-6.
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Intel® QuickPath Architecture System Address Decode Register Description 3.4 PCI Standard Registers These registers appear in every function for every device. 3.4.1 VID—Vendor Identification Register The VID Register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register uniquely identifies the manufacturer of the function within the processor. Writes to this register have no effect. 3.4.
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Intel® QuickPath Architecture System Address Decode Register Description 3.4.3 RID—Revision Identification Register This register contains the revision number of the processor. The Revision ID (RID) is a traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function.
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Intel® QuickPath Architecture System Address Decode Register Description 3.4.4 CCR—Class Code Register This register contains the Class Code for the device. Writes to this register have no effect. Device: Function: Offset: 0 0–1 09h Device: Function: Offset: 2 0–1 09h Bit Type Reset Value 23:16 RO 06h 15:8 7:0 344 RO RO Description Base Class This field indicates the general device category. For the processor, this field is hard wired to 06h, indicating it is a “Bridge Device”.
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Intel® QuickPath Architecture System Address Decode Register Description 3.4.5 HDR—Header Type Register This register identifies the header layout of the configuration space. Device: Function: Offset: 0 0–1 0Eh Device: Function: Offset: 2 0–1 0Eh Bit 7 6:0 3.4.6 Type RO RO Reset Value Description 1 Multi-function Device This bit selects whether this is a multi-function device, that may have alternative configuration layouts. This bit is hard wired to 1 for devices in the processor.
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Intel® QuickPath Architecture System Address Decode Register Description 3.4.7 PCICMD—Command Register This register defines the PCI 3.0 compatible command register values applicable to PCI Express space. 346 Device: Function: Offset: 0 0–1 04h Device: Function: Offset: 2 0–1 04h Bit Type Reset Value 15:11 RV 0 Reserved. (by PCI SIG) Description 10 RO 0 INTxDisable: Interrupt Disable This bit controls the ability of the PCI Express port to generate INTx messages.
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Intel® QuickPath Architecture System Address Decode Register Description 3.4.8 PCISTS—PCI Status Register The PCI Status register is a 16-bit status register that reports the occurrence of various error events on this device's PCI interface. Device: Function: Offset: 0 0–1 06h Device: Function: Offset: 2 0–1 06h Bit Type Reset Value 15 RO 0 Detect Parity Error (DPE) The host bridge does not implement this bit and is hard wired to a 0. Writes to this bit position have no effect.
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Intel® QuickPath Architecture System Address Decode Register Description Device: Function: Offset: 0 0–1 06h Device: Function: Offset: 2 0–1 06h Bit 4 348 Type RO Reset Value Description 0 Capability List (CLIST) This bit is hard wired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities.
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Intel® QuickPath Architecture System Address Decode Register Description 3.5 Generic Non-core Registers 3.5.1 MAX_RTIDS Maximum number of RTIDs other homes have. How many requests can this caching agent send to the other home agents. This number is one more than the highest numbered RTID to use. Note that these values reset to 2, and need to be increased by BIOS to whatever the home agents can support.
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Intel® QuickPath Architecture System Address Decode Register Description Device: Function: Offset: Access as a Dword Bit 350 Type 0 1 40h Reset Value Description 25:24 RW 0 PAM3_LOENABLE. 0D0000h–0D3FFFh Attribute (LOENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh. 00 = DRAM Disabled: All accesses are directed to ESI. 01 = Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
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Intel® QuickPath Architecture System Address Decode Register Description 3.6.2 SAD_PAM456 This register is for legacy Device 0, Function 0 94h–97h address space. Device: Function: Offset: Access as a Dword Bit Type Reset Value 31:22 RV 0 Reserved Description 21:20 RW 0 PAM6_HIENABLE. 0EC000h–0EFFFFh Attribute (HIENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0EC000h to 0EFFFFh. 00 = DRAM Disabled: All accesses are directed to ESI.
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Intel® QuickPath Architecture System Address Decode Register Description 3.6.3 SAD_HEN This register is for legacy Hole Enable. Device: Function: Offset: Access as a Dword 352 0 1 48h Bit Type Reset Value 31:8 RV 0 Reserved Description 7 RW 0 HEN This bit enables a memory hole in DRAM space. The DRAM that lies "behind" this space is not remapped. 0 = No Memory hole. 1 = Memory hole from 15 MB to 16 MB.
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Intel® QuickPath Architecture System Address Decode Register Description 3.6.4 SAD_SMRAM This register is for legacy 9Dh address space. Note: This register must be programmed consistently with any other registers controlling access to SMM space within the system, such as on IOH devices if present.
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Intel® QuickPath Architecture System Address Decode Register Description 3.6.5 SAD_PCIEXBAR This is the Global register for PCIEXBAR address space. Device: Function: Offset: Access as a QWord 354 0 1 50h Bit Type Reset Value 63:40 RV 0 Reserved 39:20 RW 0 ADDRESS This field contains the Base address of PCIEXBAR. It must be naturally aligned to size; low order bits are ignored. 19:4 RV 0 Reserved Description 3:1 RW 0 SIZE Size of the PCIEXBAR address space. (Maximum bus number).
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Intel® QuickPath Architecture System Address Decode Register Description 3.6.6 SAD_DRAM_RULE_0, SAD_DRAM_RULE_2, SAD_DRAM_RULE_4, SAD_DRAM_RULE_6, SAD_DRAM_RULE_1, SAD_DRAM_RULE_3, SAD_DRAM_RULE_5, SAD_DRAM_RULE_7 This register provides the SAD DRAM rules. Address Map for package determination. Device: Function: Offset: Access as a Dword Bit Type Reset Value 31:20 RV 0 Reserved Description 19:6 RW – LIMIT DRAM rule top limit address.
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Intel® QuickPath Architecture System Address Decode Register Description 3.7 Intel® QPI Link Registers 3.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1 This register provides Intel QPI Link Control. Device: Function: Offset: Access as a Dword Bit Type Reset Value 31:22 RV 0 Reserved 0 L1_MASTER This bit indicates that this end of the link is the L1 master. This link transmitter bit is an L1 power state master and can initiate an L1 power state transition.
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Intel® QuickPath Architecture System Address Decode Register Description 3.8 Intel® QPI Physical Layer Registers 3.8.1 QPI_0_PH_CPR, QPI_1_PH_CPR This is the Intel QPI Physical Layer Capability Register. Device: Function: Offset: Access as a Dword Bit Type Reset Value 31:30 RV – Reserved 29 RO – LFSR_POLYNOMIAL. Agent's ITU polynomial capability for loopback. Description 28:24 RO – NUMBER_OF_TX_LANES Number of Tx lanes with which an implementation can operate for full width.
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Intel® QuickPath Architecture System Address Decode Register Description 3.8.2 QPI_0_PH_CTR, QPI_1_PH_CTR This is the Intel QPI Physical Layer Control Register. Device: Function: Offset: Access as a Dword Bit Type Reset Value 31:28 RV 0 Reserved 27 RW 0 LA_LOAD_DISABLE This bit disables the loading of the effective values of the Intel QPI CSRs when set. 26:24 RV 0 Reserved 0 ENABLE_PRBS This bit enables LFSR pattern during bitlock/training. 1 = Use pattern in bitlock/retraining.
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Intel® QuickPath Architecture System Address Decode Register Description 3.8.3 QPI_0_PH_PIS, QPI_1_PH_PIS This is an Intel QPI Physical Layer Initialization Status Register. Device: Function: Offset: Access as a Dword 2 1 80h Bit Type Reset Value 31:30 RV – Reserved 29 RO – GLOBAL_ERROR Set upon any error detected on the link during Loopback Pattern. 28 RO – TEST_BUSY Test busy bit indicating that a test is in progress. 27 RW1C 0 STATE_HOLD.
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Intel® QuickPath Architecture System Address Decode Register Description 360 Datasheet, Volume 2