Mobile 3rd Generation Intel® Core™ Processor Family Datasheet – Volume 1 of 2 June 2012 Document Number: 326768-003
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Contents 1 Introduction ............................................................................................................ 11 1.1 Processor Feature Details ................................................................................... 13 1.1.1 Supported Technologies .......................................................................... 13 1.2 Interfaces ........................................................................................................ 13 1.2.
2.4 2.5 2.6 2.3.3 DMI Link Down .......................................................................................32 Processor Graphics Controller (GT).......................................................................32 2.4.1 3D and Video Engines for Graphics Processing ............................................33 2.4.1.1 3D Engine Execution Units ..........................................................33 2.4.1.2 3D Pipeline ...................................................................
4.3 4.4 4.5 4.6 4.7 5 4.2.4.4 Core C6 State........................................................................... 53 4.2.4.5 Core C7 State........................................................................... 54 4.2.4.6 C-State Auto-Demotion ............................................................. 54 4.2.5 Package C-States ................................................................................... 54 4.2.5.1 Package C0 ...............................................................
5.6.4 5.6.5 5.6.6 On-Demand Mode ...................................................................................79 5.6.4.1 MSR Based On-Demand Mode .....................................................79 5.6.4.2 I/O Emulation-Based On-Demand Mode .......................................79 Memory Thermal Management..................................................................80 Platform Environment Control Interface (PECI) ...........................................80 6 Signal Description .........
Figures 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 4-1 4-2 4-3 4-4 5-1 5-2 7-1 7-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 Mobile Processor Platform........................................................................................ 12 Mobile Processor Compatibility Diagram .................................................................... 19 Intel® Flex Memory Technology Operation ................................................................. 26 PCI Express* Layering Diagram........
4-11 4-12 5-1 5-2 5-3 5-4 5-5 5-6 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 8-1 8-2 8-3 9-1 9-2 8 Coordination of Core Power States at the Package Level ..............................................55 Targeted Memory State Conditions............................................................................60 Intel® Turbo Boost Technology Package Power Control Settings ....................................
Revision History Revision Number 001 002 Description • Initial release Revision Date April 2012 • Added Mobile 3rd Generation Intel® Core™ i7-3520M, i5-3360M, i5-3320M, i7-3667U, i5-3427U processors • Updated Table 7-10, Processor Graphics (VAXG) Supply DC Voltage and Current Specifications June 2012 • Updated Section 1.2.2, PCI Express* • Updated Section 1.5, Package 003 • Removed DDR 1066 MHz support June 2012 • Added support for DDR3L-RS • Updated Section 2.1.
Datasheet, Volume 1
Introduction 1 Introduction The Mobile 3rd Generation Intel® Core™ processor family is the next generation of 64bit, multi-core mobile processors built on 22-nanometer process technology. The processor is designed for a two-chip platform. The two-chip platform consists of a processor and a Platform Controller Hub (PCH) and enables higher performance, lower cost, easier validation, and improved x-y footprint.
Introduction Figure 1-1. Mobile Processor Platform PCI Express* 3.0 1 x16 or 2x8 DDR3 / DDR3L / DDR3L-RS Discrete Graphics (PEG) Intel® Processor PECI Embedded Display Port Intel® Flexible Display Interface DMI2 x4 Serial ATA Intel® Management Engine Digital Display x 3 USB 2.0 / USB 3.01 Intel® 6/7 Series Chipset Families LVDS Flat Panel Intel® HD Audio Analog CRT SPI Flash x 2 SMBUS 2.0 SPI Controller Link 1 FWH LPC PCI Express* WiFi / WiMax 8 PCI Express* 2.
Introduction 1.1 Processor Feature Details • • • • 1.1.
Introduction • Processor on-die Reference Voltage (VREF) generation for both DDR3 Read (RDVREF) and Write (VREFDQ) • 1Gb, 2Gb, and 4Gb DDR3 DRAM device technologies are supported — Using 4Gb DRAM device technologies, the largest memory capacity possible is 32 GB, assuming Dual Channel Mode with four x8 dual ranked DIMM memory configuration • Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank devices) • Command launch modes of 1N/2N • On-Die Termination (ODT) • Asynchronous ODT • I
Introduction • PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space. • PCI Express* Enhanced Access Mechanism. Accessing the device configuration space in a flat memory mapped fashion.
Introduction • 64-bit downstream address format; however, the processor never generates an address above 64 GB (Bits 63:36 will always be zeros) • 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.
Introduction 1.2.6 Embedded DisplayPort* (eDP*) • Stand alone dedicated port (unlike two generations ago that shared pins with PCIe interface) 1.2.
Introduction 1.3.6 Processor Graphics Controller (GT) • • • • Rapid Memory Power Management RMPM – CxSR Graphics Performance Modulation Technology (GPMT) Intel Smart 2D Display Technology (Intel S2DDT) Graphics Render C-State (RC6) • Intel Seamless Display Refresh Rate Switching with eDP port 1.3.
Introduction 1.6 Processor Compatibility The Mobile 3rd Generation Intel® Core™ processor family has specific platform requirements that differentiate it from a 2nd Generation Intel® Core™ processor family mobile processor. Platforms intending to support both processor families need to address the platform compatibility requirements detailed in Figure 1-2. Mobile Processor Compatibility Diagram VCCIO VR VDDQ VR 2 x 330 µF 2 x 330 µF + 1 placeholder VCore VR DDR3 DDR3/3L VAXG VR SVID Figure 1-2.
Introduction 1.7 Terminology Table 1-2.
Introduction Table 1-2. Terminology (Sheet 2 of 2) Term Description PCH Platform Controller Hub. The chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features. PECI Platform Environment Control Interface. PEG PCI Express* Graphics. External Graphics using PCI Express* Architecture.
Introduction 1.8 Related Documents Table 1-3. Related Documents Document Number/ Location Document Mobile 3rd Generation Intel® Core™ Processor Family Datasheet, Volume 2 326769 Mobile 3rd Generation Intel® Core™ Processor Family Specification Update 326770 Advanced Configuration and Power Interface Specification 3.0 PCI Local Bus Specification 3.0 http://www.acpi.info/ http://www.pcisig.com/speci fications PCI Express* Base Specification 2.0 http://www.pcisig.
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. 2.1 System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 / DDR3L / DDR3L-RS protocols with two independent, 64-bit wide channels, each accessing one or two DIMMs. The IMC supports one or two, unbuffered non-ECC DDR3 DIMM per-channel; thus, allowing up to four device ranks per-channel.
Interfaces Table 2-2.
Interfaces Table 2-4. DDR3/DDR3L/DDR3L-RS @ 1.5 V System Memory Timing Support Segment Extreme Edition (XE) and Quad Core SV Dual Core Standard Voltage (SV) & Ultra Transfer Rate (MT/s) tCL (tCK) tRCD (tCK) tRP (tCK) CWL (tCK) 1333 9 9 9 7 1600 11 11 11 8 1333 9 9 9 1600 11 11 11 DPC CMD Mode 1 1N/2N 2 2N 1 1N/2N 2 2N 7 1 1N/2N 8 1 1N/2N Notes1 Note: 1. System memory timing support is based on availability and is subject to change. Table 2-5.
Interfaces Figure 2-1. Intel® Flex Memory Technology Operation TOM C N o n in te r le a v e d access B C Dual channel in t e r le a v e d a c c e s s B B B CH A CH B C H A a n d C H B c a n b e c o n fig u re d to b e p h y s ic a l c h a n n e ls 0 o r 1 B – T h e la rg e s t p h y s ic a l m e m o ry a m o u n t o f th e s m a lle r s iz e m e m o ry m o d u le C – T h e re m a in in g p h y s ic a l m e m o ry a m o u n t o f th e la rg e r s iz e m e m o ry m o d u le 2.1.3.2.
Interfaces 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.
Interfaces 2.1.8 DDR3 Reference Voltage Generation The processor memory controller has the capability of generating the DDR3 Reference Voltage (VREF) internally for both read (RDVREF) and write (VREFDQ) operations. The generated VREF can be changed in small steps, and an optimum VREF value is determined for both during a cold boot through advanced DDR3 training procedures in order to provide the best voltage and signal margins. 2.
Interfaces PCI Express uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers.
Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-4.
Interfaces 2.2.3 PCI Express* Graphics The external graphics attach (PEG) on the processor is a single, 16-lane (x16) port. The PEG port is being designed to be compliant with the PCI Express Base Specification, Revision 3.0. 2.2.3.1 PCI Express* Lanes Connection Figure 2-5 demonstrates the PCIe lanes mapping. Figure 2-5.
Interfaces 2.3 Direct Media Interface (DMI) Direct Media Interface (DMI) connects the processor and the PCH. Next generation DMI 2.0 is supported. Note: Only DMI x4 configuration is supported. 2.3.1 DMI Error Flow DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or GPE. Any DMI related SERR activity is associated with Device 0. 2.3.2 Processor/PCH Compatibility Assumptions The processor is compatible with the Intel 7 Series Chipset PCH products. 2.3.
Interfaces Figure 2-6. Processor Graphics Controller Unit Block Diagram VS/GS Setup/Rasterize Hierachical Z Hardware Clipper Vertex Fetch Unified Execution Unit Array EU EU EU EU Texture Unit Pixel Backend Additional Post Processing Multi-Format Decode/Encode Full MPEG2, VC1, AVC Decode Fixed Function Post Processing Full AVC Encode Partial MPEG2, VC1 Encode 2.4.
Interfaces 2.4.1.2 3D Pipeline 2.4.1.2.1 Vertex Fetch (VF) Stage The VF stage executes 3DPRIMITIVE commands. Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL*. 2.4.1.2.2 Vertex Shader (VS) Stage The VS stage performs shading of vertices output by the VF function. The VS unit produces an output vertex reference for every input vertex reference received from the VF unit, in the order received. 2.4.1.2.
Interfaces 2.4.1.4 2D Engine The Display Engine fetches the raw data from the memory, puts the data into a stream, converts the data into raw pixels, organizes pixels into images, blends different planes into a single image, encodes the data, and sends the data out to the display device. The Display Engine executes its functions with the help of three main functional blocks – Planes, Pipes, and Ports, except for eDP. The Planes and Pipes are in the processor while the Ports reside in the PCH.
Interfaces 2.4.2 Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components: • Display Planes • Display Pipes • Embedded DisplayPort* and Intel® FDI Figure 2-7. Processor Display Block Diagram VGA Memory Host Interface (Outside of Display Engine) 2.4.2.
Interfaces 2.4.2.2 Display Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed. The display pipes A, B, and C operate independently of each other at the rate of 1 pixel per clock. They can attach to any of the display ports. Each pipe sends display data to eDP or to the PCH over the Intel Flexible Display Interface (Intel FDI). 2.4.2.
Interfaces 2.4.4 Multi Graphics Controllers Multi-Monitor Support The processor supports simultaneous use of the Processor Graphics Controller (GT) and a x16 PCI Express Graphics (PEG) device. The processor supports a maximum of 2 displays connected to the PEG card in parallel with up to 2 displays connected to the processor and PCH. Note: When supporting Multi Graphics Multi Monitors, “drag and drop” between monitors and the 2x8 PEG is not supported. 2.
Technologies 3 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.intel.com/technology/. 3.
Technologies 3.1.
Technologies • Support for register-based fault recording only (for single entry only) and support for MSI interrupts for faults • Support for both leaf and non-leaf caching • Support for boot protection of default page table • Support for non-caching of invalid page table entries • Support for hardware based flushing of translated but pending writes and pending reads, on IOTLB invalidation • Support for page-selective IOTLB invalidation • MSI cycles (MemWr to address FEEx_xxxxh) not translated — Translati
Technologies These extensions enhance two areas: • The launching of the Measured Launched Environment (MLE) • The protection of the MLE from potential corruption The enhanced platform provides these launch and control interfaces using Safer Mode Extensions (SMX).
Technologies with maximum performance. Since the turbo feature is configurable and dependent on many platform design limits outside of the processor control, the maximum performance cannot be ensured. Turbo Mode availability is independent of the number of active cores; however, the Turbo Mode frequency is dynamic and dependent on the instantaneous application power load, the number of active cores, user configurable settings, operating environment, and system design. 3.4.
Technologies 3.5 Intel® Advanced Vector Extensions (AVX) Intel® Advanced Vector Extensions (AVX) is the latest expansion of the Intel instruction set. It extends the Intel® Streaming SIMD Extensions (SSE) from 128-bit vectors to 256-bit vectors. Intel AVX addresses the continued need for vector floating-point performance in mainstream scientific and engineering numerical applications, visual processing, recognition, data-mining/synthesis, gaming, physics, cryptography and other application areas.
Technologies 3.6.3 RDRAND Instruction The processor introduces a software visible random number generation mechanism supported by a high quality entropy source. This capability will be made available to programmers through the new RDRAND instruction. The resultant random number generation capability is designed to comply with existing industry standards in this regard (ANSI X9.82 and NIST SP 800-90).
Technologies • More efficient MSR interface to access APIC registers. — To enhance inter-processor and self directed interrupt delivery as well as the ability to virtualize the local APIC, the APIC register set can be accessed only through MSR based interfaces in the x2APIC mode. The Memory Mapped IO (MMIO) interface used by xAPIC is not supported in the x2APIC mode.
Power Management 4 Power Management This chapter provides information on the following power management topics: • ACPI States • Processor Core • Integrated Memory Controller (IMC) • PCI Express* • Direct Media Interface (DMI) • Processor Graphics Controller Figure 4-1.
Power Management 4.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-1. System States State G0/S0 G1/S3-Cold Description Full On Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor). G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH). G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot. G3 Mechanical off. All power (AC and battery) removed from system.
Power Management 4.1.4 PCI Express* Link States Table 4-4. PCI Express* Link States State Description L0 Full on – Active transfer state. L0s First Active Power Management low power state – Low exit latency L1 Lowest Active Power Management – Longer exit latency L3 Lowest power state (power-off) – Longest exit latency 4.1.5 DMI States Table 4-5.
Power Management Table 4-8. D, S, and C State Combination Graphics Adapter (D) State 4.
Power Management 4.2.2 Low-Power Idle States When the processor is idle, low-power idle states (C-states) are used to save power. More power savings actions are taken for numerically higher C-states. However, higher C-states have longer exit and entry latencies. Resolution of C-states occur at the thread, processor core, and processor package level. Thread-level C-states are available if Intel Hyper-Threading Technology is enabled. Caution: Figure 4-2.
Power Management Table 4-9. Coordination of Thread Power States at the Core Level Processor Core C-State C0 C1 C3 C6 C7 C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C11 C3 C0 C11 C3 C3 C3 C6 C0 C1 1 C3 C6 C6 C7 C0 C11 C3 C6 C7 C0 Thread 0 Note: 4.2.3 Thread 1 If enabled, the core C-state will be C1E if all cores have resolved a core C1 state or higher.
Power Management 4.2.4 Core C-states The following are general rules for all core C-states, unless specified otherwise: • A core C-State is determined by the lowest numerical thread state (such as Thread 0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See Table 4-7.
Power Management 4.2.4.5 Core C7 State Note: The terms “Core C6 state” and “Core C7 state” defines the same individual core power state. In both cases the processor cores that request either C6 or C7 will enter the C6 state. Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to the P_BLK or by an MWAIT(C7) instruction. The core C7 state exhibits the same behavior as the core C6 state unless the core is the last one in the package to enter the C7 state.
Power Management The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following: • If a core break event is received, the target core is activated and the break event message is forwarded to the target core. — If the break event is not masked, the target core enters the core C0 state and the processor enters package C0. • If the break event was due to a memory access or snoop request.
Power Management 4.2.5.1 Package C0 Package C0 is the normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0. 4.2.5.2 Package C1/C1E No additional power reduction actions are taken in the package C1 state.
Power Management 4.2.5.5 Package C7 State The processor enters the package C7 low power state when all cores are in the C7 state and the L3 cache is completely flushed. The last core to enter the C7 state begins to shrink the L3 cache by N-ways until the entire L3 cache has been emptied. This allows further power savings. Core break events are handled the same way as in package C3 or C6.
Power Management 4.3.2 DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface. There are four SDRAM operations associated with the Clock Enable (CKE) signals that the SDRAM controller supports. The processor drives four CKE pins to perform these operations. The CKE is one means of power saving. When CKE is off, the internal DDR clock is disabled and the DDR power is reduced.
Power Management It is important to understand that since the power down decision is per rank, the MC can find a lot of opportunities to power down ranks, even while running memory intensive applications; savings may be significant (up to a few Watts, depending on DDR configuration). This becomes more significant when each channel is populated with more ranks.
Power Management The target behavior is to enter self-refresh for the package C3, C6, and C7 states as long as there are no memory requests to service. Table 4-12. Targeted Memory State Conditions Mode Memory State with Processor Graphics Memory State with External Graphics C0, C1, C1E Dynamic memory rank power down based on idle conditions. Dynamic memory rank power down based on idle conditions.
Power Management There is no change to the signals driven by the processor to the DIMMs during DDR IO EPG mode. During EPG mode, all the DDR IO logic will be powered down, except for the Physical Control registers that are powered by the un-gated VCCIO power supply. Unlike S3 exit, at DDR EPG exit, the DDR will not go through training mode. Rather, it will use the previous training information retained in the physical control registers and will immediately resume normal operation. 4.
Power Management 4.6.3 Graphics Render C-State Render C-State (RC6) is a technique designed to optimize the average power to the graphics render engine during times of idleness of the render engine. Render C-state is entered when the graphics render engine, blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions.
Power Management 4.6.6 Display Power Savings Technology 6.0 (DPST) This is a mobile only supported power management feature. The Intel DPST technique achieves backlight power savings while maintaining a good visual experience. This is accomplished by adaptively enhancing the displayed image while decreasing the backlight brightness simultaneously. The goal of this technique is to provide equivalent end-user-perceived image quality at a decreased backlight power level. 1.
Power Management 4.7 Graphics Thermal Power Management See Section 4.6 for all graphics thermal power management-related features.
Thermal Management 5 Thermal Management The thermal solution provides both the component-level and the system-level thermal management. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed so that the processor: • Remains below the maximum junction temperature (Tj,Max) specification at the maximum thermal design power (TDP).
Thermal Management The following considerations and limitations apply to the Intel Turbo Boost Technology power monitoring: • Internal power monitoring is calibrated per processor family and is not conducted on a part-by-part basis. Therefore, some difference between actual and reported power may be observed. • Power monitoring is calibrated with a variety of common, realistic workloads near Tj,Max.
Thermal Management Table 5-1. Intel® Turbo Boost Technology Package Power Control Settings MSR: Address: Control POWER_LIMIT_1 (PL1) POWER_LIMIT_1_TIME (Turbo Time Parameter) POWER_LIMIT_2 (PL2) Figure 5-1. MSR_TURBO_POWER_LIMIT 610h Bit 14:0 23:17 46:32 Default Description SKU TDP This value sets the exponentially weighted moving average power limit over a long time period. This is normally aligned to the TDP of the part and steadystate cooling capability of the thermal solution.
Thermal Management 5.3.2 Power Plane Control The processor core and graphics core power plane controls allow for customization to implement optimal Turbo within voltage regulator thermal limitations. It is possible to use these power plane controls to protect the voltage regulator from overheating due to extended high currents. Power limiting per plane cannot be ensured in all usages. This function is similar to the package level long duration Turbo control.
Thermal Management Table 5-2. Configurable TDP Modes Mode Description Nominal This is the processor’s rated frequency and TDP. TDP-Up When extra cooling is available, this mode specifies a higher TDP and higher ensured frequency versus the nominal mode. TDP-Down When a cooler or quieter mode of operation is desired, this mode specifies a lower TDP and lower ensured frequency versus the nominal mode.
Thermal Management 5.5 Thermal and Power Specifications The following notes apply to the tables in this section. 70 Note Definition 1 The TDPs given are not the maximum power the processor can generate. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained periods of time. 2 TDP workload may consist of a combination of a processor-core intensive and a graphics-core intensive applications.
Thermal Management Table 5-3. TDP Specifications Segment Processor Core Frequency State Processor Graphics Core frequency Thermal Design Power TDP-Up 1.9 GHz up to 3.8 GHz TDP-Down Quad Core SV Quad Core SV Dual Core SV 45 LFM 1200 MHz 40 800 MHz 35 HFM 2.3 GHz up to 3.7 GHz LFM 1200 MHz HFM 2.1 GHz up to 3.1 GHz LFM 1200 MHz HFM 2.4 GHz up to 3.
Thermal Management Table 5-5.
Thermal Management Table 5-6. Idle Power Specifications Segment Symbol Extreme Edition (XE) Quad Core SV 45 W Dual Core and Quad Core SV 35 W Min Typ Max Units Notes PC6 Idle power in the Package C6 state - - 3.6 W 6, 9 PC7 Idle power in the Package C7state - - 3.5 W 6, 9 PC6 Idle power in the Package C6 state - - 3.1 W 6, 9 PC7 Idle power in the Package C7state - - 3.0 W 6, 9 PC6 Idle power in the Package C6 state - - 3.
Thermal Management The temperature at which the Adaptive Thermal Monitor activates the thermal control circuit is factory calibrated and is not user configurable. The default value is software visible in the TEMPERATURE_TARGET (1A2h) MSR, bits 23:16. The Adaptive Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines. The Adaptive Thermal Monitor is not intended as a mechanism to maintain processor TDP.
Thermal Management Figure 5-2. Frequency and Voltage Ordering Once a target frequency/bus ratio is resolved, the processor core will transition to the new target automatically. • On an upward operating point transition, the voltage transition precedes the frequency transition. • On a downward transition, the frequency transition precedes the voltage transition. When transitioning to a target core operating voltage, a new VID code to the voltage regulator is issued.
Thermal Management 5.6.1.3 Clock Modulation If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor event, the Adaptive Thermal Monitor will utilize clock modulation. Clock modulation is done by alternately turning the clocks off and on at a duty cycle (ratio between clock “on” time and total time) specific to the processor. The duty cycle is adjusted dynamically based on the throttling need, and cannot be modified.
Thermal Management The DTS-relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point. When a package DTS indicates that it has reached the TCC activation (a reading of 0h, except when the TCC activation offset is changed), the TCC will activate and indicate a Adaptive Thermal Monitor event. A TCC activation will lower both IA core and graphics core frequency, voltage or both.
Thermal Management The TCC will remain active until the system de-asserts PROCHOT#. The processor can be configured to generate an interrupt upon assertion and de-assertion of the PROCHOT# signal. Note: Toggling PROCHOT# more than once in 1.5 ms period will result in constant Pn state of the processor. 5.6.3.2 Voltage Regulator Protection versus PROCHOT# PROCHOT# may be used for thermal protection of voltage regulators (VR).
Thermal Management 5.6.3.5 THERMTRIP# Signal Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the package will automatically shut down when the silicon has reached an elevated temperature that risks physical damage to the product. At this point the THERMTRIP# signal will go active. 5.6.3.6 Critical Temperature Detection Critical Temperature detection is performed by monitoring the package temperature.
Thermal Management 5.6.5 Memory Thermal Management The integrated memory controller (IMC) provides thermal protection for system memory DIMMs using memory bandwidth throttling. Like processor package throttling, memory throttling is initiated based on temperature. The IMC offers two levels of throttling (warm and hot). The temperature and the amount of bandwidth reduced while throttling is programmable for the warm and hot trip points through memory mapped I/O registers.
Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type. Notations Signal Type I Input Signal O Output Signal I/O Bi-directional Input/Output Signal The signal description also includes the type of buffer used for the particular signal (see Table 6-1). Table 6-1.
Signal Description 6.1 System Memory Interface Table 6-2. Memory Channel A Signal Name Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SA_WE# Write Enable Control Signal: This signal is used with SA_RAS# and SA_CAS# (along with SA_CS#) to define the SDRAM Commands. O DDR3 SA_RAS# RAS Control Signal: This signal is used with SA_CAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands.
Signal Description Table 6-3. Memory Channel B Signal Name Direction/ Buffer Type Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SB_WE# Write Enable Control Signal: This signal is used with SB_RAS# and SB_CAS# (along with SB_CS#) to define the SDRAM Commands. O DDR3 SB_RAS# RAS Control Signal: This signal is used with SB_CAS# and SB_WE# (along with SB_CS#) to define the SRAM Commands.
Signal Description 6.2 Memory Reference and Compensation Table 6-4. Memory Reference and Compensation Signal Name SM_RCOMP[2:0] SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ System Memory Impedance Compensation: I/O A DDR3/DDR3L/DDR3L-RS Reference Voltage: This signal is used as a reference voltage to the DDR3/DDR3L/DDR3L-RS controller. I A Memory Channel A/B DIMM DQ Voltage Reference: These output pins are connected to the DIMMs, and are programmed to have a reference voltage with optimized margin.
Signal Description 6.4 PCI Express*-based Interface Signals Table 6-6. PCI Express* Graphics Interface Signals Signal Name PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO Description PCI Express* Input Current Compensation I A PCI Express* Current Compensation I A PCI Express* Resistance Compensation I A PEG_RX[15:0] PEG_RX#[15:0] PCI Express* Receive Differential Pair I PCI Express* PEG_TX[15:0] PEG_TX#[15:0] PCI Express* Transmit Differential Pair O PCI Express* 6.
Signal Description Table 6-8. Intel® Flexible Display Interface (Sheet 2 of 2) Signal Name FDI1_FSYNC[1] FDI1_LSYNC[1] FDI_INT Intel® Flexible Display Interface Frame Sync: Pipe B and C I CMOS Intel® Flexible Display Interface Line Sync: Pipe B and C I CMOS Intel® Flexible Display Interface Hot-Plug Interrupt 6.7 Direct Media Interface (DMI) Table 6-9. DMI – Processor to PCH Serial Interface Signal Name 6.
Signal Description Table 6-11. TAP Signals (Sheet 2 of 2) 6.10 Signal Name Description PREQ# PREQ# is used by debug tools to request debug operation of the processor. Direction/ Buffer Type I Asynchronous CMOS TCK TCK (Test Clock): This signal provides the clock input for the processor Test Bus (also known as the Test Access Port). TCK must be driven low or allowed to float during power on Reset. I CMOS TDI TDI (Test Data In): This signal transfers serial test data into the processor.
Signal Description 6.11 Power Sequencing Table 6-13. Power Sequencing Signal Name SM_DRAMPWROK SM_DRAMPWROK Processor Input: Connects to PCH DRAMPWROK. I Asynchronous CMOS UNCOREPWRGOOD The processor requires this input signal to be a clean indication that the VCCSA, VCCIO, VAXG, and VDDQ, power supplies are stable and within specifications. This requirement applies regardless of the S-state of the processor.
Signal Description 6.12 Processor Power Signals Table 6-14. Processor Power Signals Signal Name Description VCC Direction/ Buffer Type Processor core power rail. Ref VCCIO Processor power for I/O. Ref VDDQ Processor I/O supply voltage for DDR3. Ref VAXG Graphics core power supply. Ref VCCPLL VCCPLL provides isolated power for internal processor PLLs. Ref VCCSA System Agent power supply. Ref VCCPQE (BGA Only) Filtered, low noise derivative of VCCIO. Load current is less than 1 mA.
Signal Description Table 6-15. Sense Signals (Sheet 2 of 2) Signal Name Description Direction/ Buffer Type VCCSA_SENSE VCCSA_SENSE provide an isolated, low impedance connection to the processor system agent voltage. It can be used to sense or measure voltage near the silicon. O Analog VCC_DIE_SENSE VCC_VAL_SENSE VSS_VAL_SENSE VAXG_VAL_SENSE VSSAXG_VAL_SENSE 6.14 Die Validation Sense. O Analog VCC Validation Sense. O Analog VAXG Validation Sense. O Analog Ground and NCTF Table 6-16.
Electrical Specifications 7 Electrical Specifications 7.1 Power and Ground Pins The processor has VCC, VCCIO, VDDQ, VCCPLL, VCCSA, VAXG and VSS (ground) inputs for on-chip power distribution. All power pins must be connected to their respective processor power planes, while all VSS pins must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
Electrical Specifications 7.3 Voltage Identification (VID) The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages. Table 7.4 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself.
Electrical Specifications Table 7-1.
Electrical Specifications Table 7-1.
Electrical Specifications 7.4 System Agent (SA) Vcc VID The VCCSA is configured by the processor output pins VCCSA_VID[1:0]. VCCSA_VID[0] output default logic state is low for 2nd Generation Intel® Core® family mobile processors. Note: During boot, the processor VCCSA voltage is 0.9 V. The VCCSA may change only once during the reset sequence. Note: For Ultra products, for power optimization purposes, the VCCSA_VID may change dynamically during the processor’s operation.
Electrical Specifications 7.6 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7-3 The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have OnDie Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. Table 7-3.
Electrical Specifications Table 7-3.
Electrical Specifications 7.7 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.
Electrical Specifications 7.9 DC Specifications The processor DC specifications in this section are defined at the processor pins, unless noted otherwise. See Chapter 8 for the processor pin listings and Chapter 6 for signal definitions. • The DC specifications for the DDR3 signals are listed in Table 7-7 Control Sideband and Test Access Port (TAP) are listed in Table 7-8.
Electrical Specifications Table 7-5. Symbol ICC_C6/C7 TOLVCC Ripple VR Step SLOPELL Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications (Sheet 2 of 2) Parameter ICC at C6/C7 Idle-state Voltage Tolerance Ripple Tolerance Segment Typ Max Unit Note A 10 mV 7, 9 mV 7, 9 XE SV-QC-45W SV-QC-35W SV-DC Ultra-DC — — 5.5 5.0 5.0 3.0 2.5 PS0 — — ±15 PS1 — — ±12 PS2, PS3 — — ±11.
Electrical Specifications Table 7-6. Processor Uncore (VCCIO) Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit VCCIO Voltage for the memory controller and shared cache defined at the motherboard VCCIO_SENSE and VSS_SENSE_VCCIO — 1.05 — V TOLCCIO VCCIO Tolerance defined across VCCIO_SENSE and VSS_SENSE_VCCIO DC: ±2% including ripple AC: ±3% Note % ICCMAX_VCCIO Max Current for VCCIO Rail — — 8.
Electrical Specifications Table 7-9. Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications Symbol VCCPLL TOLCCPLL Parameter PLL supply voltage (DC + AC specification) VCCPLL Tolerance Min Typ Max Unit — 1.8 — V AC+DC= ±5% Note % ICCMAX_VCCPLL Max Current for VCCPLL Rail — — 1.2 A ICCTDC_VCCPLL Thermal Design Current (TDC) for VCCPLL Rail — — 1.2 A Note: 1. Long term reliability cannot be assured in conditions above or below Max/Min functional limits. Table 7-10.
Electrical Specifications 3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe. PSx refers to the voltage regulator power state as set by the SVID protocol.
Electrical Specifications Table 7-11. DDR3/DDR3L/DDR3L-RS Signal Group DC Specifications (Sheet 2 of 2) Symbol Parameter Max Units Notes1 Min Typ ILI Input Leakage Current (DQ, CK) 0V 0.2*VDDQ 0.8*VDDQ VDDQ — — ILI Input Leakage Current (CMD, CTL) 0V 0.2*VDDQ 0.8*VDDQ VDDQ — — 138.6 140 141.4 Ω 8 ± 0.75 ± 0.55 ± 0.9 ± 1.4 ± ± ± ± mA 0.85 0.65 1.10 1.65 mA SM_RCOMP0 Command COMP Resistance SM_RCOMP1 Data COMP Resistance 25.245 25.5 25.
Electrical Specifications Table 7-13. PCI Express* DC Specifications Symbol Parameter Min Typ Max Units Notes1 ZTX-DIFF-DC DC Differential Tx Impedance (Gen 1 Only) 80 — 120 Ω 2 ZTX-DIFF-DC DC Differential Tx Impedance (Gen 2 and Gen 3) — — 120 Ω 2 DC Common Mode Rx Impedance 40 — 60 Ω 3,4 DC Differential Rx Impedance (Gen1 Only) 80 — 120 Ω ZRX-DC ZRX-DIFF-DC PEG_ICOMPO Comp Resistance 24.75 25 25.25 Ω 5, 6 PEG_ICOMPI Comp Resistance 24.75 25 25.
Electrical Specifications 7.10 Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external Adaptive Thermal Monitor devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications 7.10.2 PECI DC Characteristics The PECI interface operates at a nominal voltage set by VCCIO The set of DC electrical specifications shown in Table 7-15 is used with devices normally operating from a VCCIO interface supply. VCCIO nominal levels will vary between processor families. All PECI devices will operate at the VCCIO level determined by the processor installed in the system. For specific nominal VCCIO levels, refer to Table 7-6. Table 7-15.
Electrical Specifications §§ 108 Datasheet, Volume 1
Processor Pin, Signal, and Package Information 8 Processor Pin, Signal, and Package Information 8.1 Processor Pin Assignments Figure 8-1.
Processor Pin, Signal, and Package Information Table 8-1. 110 rPGA988B Processor Pin List by Pin Name Table 8-1.
Processor Pin, Signal, and Package Information Table 8-1. rPGA988B Processor Pin List by Pin Name (Continued) Table 8-1.
Processor Pin, Signal, and Package Information Table 8-1. 112 rPGA988B Processor Pin List by Pin Name (Continued) Buffer Type Dir Table 8-1.
Processor Pin, Signal, and Package Information Table 8-1. rPGA988B Processor Pin List by Pin Name (Continued) Pin Name Pin # Buffer Type SA_DQ[43] AK9 SA_DQ[44] AH8 SA_DQ[45] Table 8-1.
Processor Pin, Signal, and Package Information Table 8-1. 114 rPGA988B Processor Pin List by Pin Name (Continued) Table 8-1.
Processor Pin, Signal, and Package Information Table 8-1.
Processor Pin, Signal, and Package Information Table 8-1. 116 rPGA988B Processor Pin List by Pin Name (Continued) Dir Table 8-1.
Processor Pin, Signal, and Package Information Table 8-1.
Processor Pin, Signal, and Package Information Table 8-1. 118 rPGA988B Processor Pin List by Pin Name (Continued) Dir Table 8-1.
Processor Pin, Signal, and Package Information Table 8-1.
Processor Pin, Signal, and Package Information Table 8-1.
Processor Pin, Signal, and Package Information Figure 8-2.
Processor Pin, Signal, and Package Information Figure 8-3.
Processor Pin, Signal, and Package Information Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name Ball # Buffer Type Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. 124 BGA1224 Processor Ball List by Ball Name (Continued) Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. BGA1224 Processor Ball List by Ball Name (Continued) Ball Name Ball # Buffer Type Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. 126 BGA1224 Processor Ball List by Ball Name (Continued) Buffer Type Dir Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. BGA1224 Processor Ball List by Ball Name (Continued) Ball Name Ball # Buffer Type SA_DQ[13] AR6 SA_DQ[14] AW6 SA_DQ[15] SA_DQ[16] Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. 128 BGA1224 Processor Ball List by Ball Name (Continued) Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. BGA1224 Processor Ball List by Ball Name (Continued) Ball Name Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. 130 BGA1224 Processor Ball List by Ball Name (Continued) Dir Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. 132 BGA1224 Processor Ball List by Ball Name (Continued) Dir Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. 134 BGA1224 Processor Ball List by Ball Name (Continued) Dir Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. 136 BGA1224 Processor Ball List by Ball Name (Continued) Dir Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. 138 BGA1224 Processor Ball List by Ball Name (Continued) Dir Table 8-2.
Processor Pin, Signal, and Package Information Table 8-2. BGA1224 Processor Ball List by Ball Name (Continued) Dir Table 8-2.
Processor Pin, Signal, and Package Information Figure 8-4.
Processor Pin, Signal, and Package Information Figure 8-5.
Processor Pin, Signal, and Package Information Table 8-3. 142 BGA1023 Processor Ball List by Ball Name Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3. BGA1023 Processor Ball List by Ball Name (Continued) Ball Name Ball # Buffer Type Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3. BGA1023 Processor Ball List by Ball Name (Continued) Ball Name Ball # Buffer Type Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3. 146 BGA1023 Processor Ball List by Ball Name (Continued) Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3. BGA1023 Processor Ball List by Ball Name (Continued) Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3. BGA1023 Processor Ball List by Ball Name (Continued) Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3. 150 BGA1023 Processor Ball List by Ball Name (Continued) Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3. 152 BGA1023 Processor Ball List by Ball Name (Continued) Dir Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3. BGA1023 Processor Ball List by Ball Name (Continued) Ball Name Ball # Buffer Type VSS AL28 VSS AL25 VSS Dir Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3. 154 BGA1023 Processor Ball List by Ball Name (Continued) Dir Table 8-3.
Processor Pin, Signal, and Package Information Table 8-3.
Processor Pin, Signal, and Package Information 8.2 Package Mechanical Information Figure 8-6.
Processor Pin, Signal, and Package Information Figure 8-7.
Processor Pin, Signal, and Package Information Figure 8-8.
Processor Pin, Signal, and Package Information Figure 8-9.
Processor Pin, Signal, and Package Information Figure 8-10.
Processor Pin, Signal, and Package Information Figure 8-11.
Processor Pin, Signal, and Package Information Figure 8-12.
Processor Pin, Signal, and Package Information Figure 8-13.
Processor Pin, Signal, and Package Information Figure 8-14.
DDR Data Swizzling 9 DDR Data Swizzling To achieve better memory performance and timing, Intel Design performed DDR Data pin swizzling that allows a better use of the product across different platforms. Swizzling has no effect on functional operation and is invisible to the operating system/software. However, during debug, swizzling needs to be taken into consideration. Therefore, this swizzling information is presented.
DDR Data Swizzling Table 9-1. Pin Name SA_DQ[0] 166 DDR Data Swizzling Table – Channel A Pin Pin Pin Number Number Number rPGA BGA1023 BGA1224 C5 AG6 AL6 Table 9-1.
DDR Data Swizzling Table 9-2. Table 9-2.
DDR Data Swizzling 168 Datasheet, Volume 1
