Am486® Microprocessor PCI Customer Development Platform User’s Manual Order #22408A
Am486® Microprocessor PCI Customer Development Platform User’s Manual © 1998 by Advanced Micro Devices, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Advanced Micro Devices, Inc.
IF YOU HAVE QUESTIONS, WE’RE HERE TO HELP YOU. The AMD customer service network includes U.S. offices, international offices, and a customer training center. Technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff to answer E86™ and Comm86™ microcontroller family hardware and software development questions. Frequently accessed numbers are listed below. Additional contact information is listed on the back of this manual.
iv Am486® Microprocessor PCI Customer Development Platform
Contents About the Customer Development Platform Evaluation Board Features ................................................................................ xiii Am486® Microprocessor .............................................................................. xiii Core Logic Chipset ....................................................................................... xiii DRAM Main Memory................................................................................... xiv Boot ROM and Flash Memory....
Chapter 1 Quick Start Setting Up the PCI CDP .................................................................................... 1-2 Installation Requirements.............................................................................. 1-3 Board Installation .......................................................................................... 1-4 Starting from Diskette ................................................................................... 1-6 Starting from an IDE Hard Drive ............
Super I/O (C19)........................................................................................... 2-28 IDE Hard Drive (L4 and M4)...................................................................... 2-31 Keyboard (O1) ............................................................................................ 2-31 Mouse (M1)................................................................................................. 2-31 CPU Voltage Adjustment (Q15–Q16).........................................
List of Figures Figure 0-1. PCI CDP Overview............................................................................................. xii Figure 2-1. PCI CDP Overview (Same as Figure 0-1)......................................................... 2-3 Figure 2-2. PCI CDP Block Diagram................................................................................... 2-4 Figure 2-3. PCI CDP Layout ................................................................................................
List of Tables Table 0-1. Notational Conventions ................................................................................. xix Table 1-1. Installation Troubleshooting ............................................................................. 1-8 Table 2-1. Board Jumper Summary .................................................................................. 2-6 Table 2-2. PCI Configuration Addressing ........................................................................
x Am486® Microprocessor PCI Customer Development Platform
About the Customer Development Platform Congratulations on your decision to design with the Am486® microprocessor. The Am486 microprocessor PCI customer development platform (CDP) provides a reference design for embedded Am486 microprocessor-based systems using the Peripheral Component Interconnect (PCI) bus with an onboard 10- or 100-Mbit/s Ethernet connection.
Am486® Microprocessor DRAM Level-2 Cache Three 72-pin SIMM Sockets Supports 48 Mbytes of EDO or FPM DRAM 48 Mbytes of 60-ns DRAM Installed 512 Kbyte Write-Back Policy JTAG Port CPU Logic Analyzer Headers In-Circuit Emulator Support Zero-Insertion-Force Socket Fan/Heat Sink Included EIP Flash Memory CPU Bus Addressed as fourth DRAM bank 8-Mbyte Flash Memory Faster than ISA Bus Flash Memory Coexists with up to 48 Mbyte of DRAM ALi M1489 Cache, Memory, and DRAM Controller (Northbridge Chip) PCI Bus Lo
Evaluation Board Features This section describes the following features of the PCI CDP: • • • • • • • • • • • • • Am486® Microprocessor, page xiii Core Logic Chipset, page xiii DRAM Main Memory, page xiv Boot ROM and Flash Memory, page xiv Onboard L2 Cache, page xiv PC and DOS Compatibility, page xv PC-Style Super I/O, page xv Keyboard and Mouse Controller, page xv Onboard 10/100-Mbit/s Ethernet, page xvi Expansion Bus Support, page xvi Development Support, page xvi Form Factor, page xvi BIOS and Software,
DRAM Main Memory • 48 Mbyte of 60-ns EDO DRAM installed. • Supports one, two, or three banks of 32- or 36-bit-wide DRAM using industry standard 5-V 72-pin SIMMs. DRAM can be fast page mode (FPM) or extended data out (EDO). • Supports 1-, 4-, or 16-Mbit technology DRAMs. • Three SIMM sockets. One or two banks per socket. Three banks DRAM maximum. • DRAM is accessible by CPU and PCI bus masters. • L1/L2 cache snoop cycles are generated for PCI master memory accesses.
PC and DOS Compatibility • IDE interface in chipset. • Standard chipset configuration registers, known to BIOS and DOS. • Off-the-shelf PC chipset provides common I/O functions found in a PC: - Two 82C59 interrupt controllers (SMI, NMI, and INT support) - One 82C54 programmable interval timer - Two 82C37 DMA controllers (seven channels) - External boot ROM chip-select signal - PC-style real-time clock (RTC) (non-Y2K-compliant, disabled by default) • DS1285 Y2K-compliant RTC chip.
Onboard 10/100-Mbit/s Ethernet • AMD PCnet™-Fast+ Ethernet Controller Chip, Am79C972. • 32-bit PCI bus interface with bus mastering capability. • Integrated 12-Kbyte buffer. • External PHY transceiver for full duplex operation at 10 or 100 Mbit/s. • IEEE802.3, PC97, PC98, and NetPC compliance. • Preprogrammed 1-Kbyte serial EEPROM included for Ethernet configuration. • Extra 4-Kbyte serial EEPROM included for user nonvolatile data. Expansion Bus Support • Two PCI 2.0 expansion connectors, desktop PC style.
Customer Development Platform Documentation The Am486® Microprocessor PCI Customer Development Platform User’s Manual provides information on the design and function of the development platform. The software shipped with the board is described in the README files and online BIOS manual included with your kit. The included online documentation is in text or Adobe Acrobat (PDF) format. The latest Acrobat Reader is available from Adobe’s site on the World Wide Web (currently at www.adobe.com).
Suggested Reference Material The following AMD documentation may be of interest to the PCI CDP user. For information on ordering literature, see page iii.
Documentation Conventions The Advanced Micro Devices Am486® Microprocessor PCI Customer Development Platform User’s Manual uses the conventions shown in Table 0-1 (unless otherwise noted). These same conventions are used in all the E86 family support product manuals. Table 0-1. Notational Conventions Symbol Usage Boldface Indicates that characters must be entered exactly as shown, except that the alphabetic case is only significant when indicated.
xx Am486® Microprocessor PCI Customer Development Platform User’s Manual
Chapter 1 Quick Start This chapter provides information that helps you quickly set up and start using the Am486® microprocessor PCI customer development platform (CDP). The PCI CDP is shipped with a BIOS that has been configured specifically for the chipset used on this platform. The BIOS contains the code that enables the PCI CDP to function as a standard AT-compatible PC, using AT-compatible displays, display adapters, and keyboards.
Setting Up the PCI CDP ! CAUTION: As with all computer equipment, the PCI CDP may be damaged by electrostatic discharge (ESD). Please take proper ESD precautions when handling any board. Warning: Read before using this development platform Before applying power, the following precautions should be taken to avoid damage or misuse of the board: • Make sure power supply connectors (from a standard AT system power supply) are plugged onto the board correctly.
Installation Requirements You need to provide the following items (in addition to the PCI CDP from the kit). Required for all setups: • A VGA-compatible monitor • A PCI- or ISA-bus video card that supports VGA • A cable to connect the monitor to the video card • An AT-compatible keyboard • A PS/2-style mouse (if needed for your operating system) • A standard AT-style power supply To boot from a floppy diskette: • An AT-compatible 3.5-inch or 5.
Board Installation Note: See Figure 2-2 on page 2-4 for a block diagram of the board. See Figure 2-3 on page 2-5 for a layout diagram of the board, including connector locations referenced in this section. ! DANGER: Make sure the power supply and the VGA monitor are not plugged into an electrical outlet during the following steps. 1. Remove the board from the shipping carton. Visually inspect the board to verify that it was not damaged during shipment. The board contains several jumpers.
3. If you are installing a hard disk drive, perform the following steps: a. Inspect the 40-wire IDE cable that you are providing. The red wire along one edge of the ribbon cable indicates wire 1. b. Connect one end of the 40-wire IDE cable to the hard drive just as you would for a standard PC installation. The connector’s orientation should be indicated in the drive documentation, or marked near the connector on the drive. Usually wire 1 is oriented towards the drive’s power cable connector. c.
Starting from Diskette Use the following steps to start the PCI CDP from a bootable diskette: 1. Make sure you have installed the PCI CDP correctly as described in “Setting Up the PCI CDP” on page 1-2. ! CAUTION: Failure to verify the power supply connections can result in total destruction of the PCI CDP. 2. Plug the VGA monitor into an electrical outlet and turn it on. 3. Insert a bootable DOS diskette (not included) in the disk drive. 4.
Starting from an IDE Hard Drive Use the following steps to start up the PCI CDP from an IDE hard drive on which you have preinstalled an operating system (while it was connected to another PC): 1. Make sure you have installed the PCI CDP correctly as described in “Setting Up the PCI CDP” on page 1-2. ! CAUTION: Failure to verify the power supply connections can result in total destruction of the PCI CDP. 2. Plug the VGA monitor into an electrical outlet and turn it on. 3.
Installation Troubleshooting Table 1-1. Installation Troubleshooting Problem Solution The Port 80h LED readout is blank after I turn on the power supply. Check power supply connectors J2 and J3. The Port 80h LED readout is stuck at 00. I see nothing on the VGA monitor and do not hear any beeps from the speaker. I do not hear the head synchronization on the diskette drive (if attached). Ensure processor reset by pressing the Reset button, SW1 at location N5.
Table 1-1. Installation Troubleshooting (Continued) Problem Solution I configured the CMOS RAM and saved my settings, but settings are lost the next time I turn on the PCI CDP. Make sure a fresh 3.0-V 20-mm coin cell is installed correctly (“+” side facing up) in the BT1 battery holder at location E12. I don’t hear any sound from the diskette drive and the system does not boot from a diskette.
Table 1-1. Installation Troubleshooting (Continued) Problem Solution I have installed a hard disk with a preinstalled operating system, but the PCI CDP won’t access the hard disk. Check that the 40-wire IDE cable is properly connected at both the drive end and the board end (board connector J5 at location L4). Check that the CMOS setup is configured correctly for your drive. Make sure the board will start from a bootable diskette in drive A. Then try to do a directory listing of drive C.
Chapter 2 Board Functional Description The Am486® microprocessor PCI customer development platform (CDP) provides a test and development platform for Am486 microprocessor-based designs.
– – – – – – – IDE Hard Drive (L4 and M4), page 2-31 Keyboard (O1), page 2-31 Mouse (M1), page 2-31 CPU Voltage Adjustment (Q15–Q16), page 2-32 Power Supply Connectors (N2 and P2), page 2-33 Reset and Interrupt Switches and Headers, page 2-34 Resistor Options, page 2-35 See the appendices for information about default board settings, bill of materials, and schematics. Feature and Layout Diagrams The following figures summarize the features and layout of the PCI CDP.
Am486® Microprocessor DRAM Level-2 Cache Three 72-pin SIMM Sockets Supports 48 Mbytes of EDO or FPM DRAM 48 Mbytes of 60-ns DRAM Installed 512 Kbyte Write-Back Policy JTAG Port CPU Logic Analyzer Headers In-Circuit Emulator Support Zero-Insertion-Force Socket Fan/Heat Sink Included EIP Flash Memory CPU Bus Addressed as fourth DRAM bank 8-Mbyte Flash Memory Faster than ISA Bus Flash Memory Coexists with up to 48 Mbyte of DRAM ALi M1489 Cache, Memory, and DRAM Controller (Northbridge Chip) PCI Bus Lo
JTAG CPU Power CPU Jumpers Am486® Microprocessor Pin Grid Array (ZIF Socket) EDO DRAM 72-pin SIMM Socket 1 Logic Analyzer Header(s): CPU Signals EDO DRAM 72-pin SIMM Socket 2 Onboard 512K L2 Cache EDO DRAM 72-pin SIMM Socket 3 CPU Address CPU Data Cache Control CPU Control DRAM-to-Flash Interface 8-Mbyte Flash Memory For Execute-In-Place Memory Address ALi M1489 Cache, Memory, and PCI Controller & Control Logic Analyzer Header(s): PCI Signals IDE Connector PCI Bus (33 MHz, 5 V) AMD Am79C
A B C D 1 E F G H I J K L Ethernet Conn. M N O P Q 1 KBD Mouse 2 2 4 5 6 Pin 1 IDE Hard Disk Conn. 3 3 IDE Hard Disk Conn. Pin 1 Power Conn. 4 5 6 Am79C972 7 Ethernet Controller ISA Slots 8 DRAM SIMM Slots PCI Slots M1489 7 8 Northbridge 9 9 10 10 11 11 12 12 Battery M1487 13 13 Southbridge Pin A1 Speaker 14 15 M5042 Kbd/ Mouse TIP 16 14 Am486® Microprocessor 15 Boot ROM Conn. 16 MACH® Logic Chip 17 DS 1685 RTC 17 18 18 Floppy Conn.
Jumper Functions Table 2-1 describes the configuration jumpers on the PCI CDP. Table 2-1. Board Jumper Summary Part Signal Description Location in See App. B Figure 2-3 Schematics on Page 2-5 on: For More Info., See: JP2 CPUVCC3 Used with JP3 to select either 5-V CPU voltage or the adjustable voltage set by jumper JP4. Both JP2 and JP3 must be positioned the same. Q15 Sheet 3 page 2-32 JP3 CPUVCC3 Used with JP2 to select either 5-V CPU voltage or the adjustable voltage set by jumper JP4.
Board Restrictions • Using a PCI chipset with the Am486 microprocessor is a fast and effective way to design a working system, but the system’s features can be limited by the chipset’s capabilities. • The chipset used in the PCI CDP supports 5-V PCI 2.0 devices only. Three devices are supported: the onboard Ethernet controller and two PCI slots. • Except for the adjustable CPU supply voltage and 3.3-V Ethernet controller, the PCI CDP uses 5-V power throughout.
Am486 Microprocessor (M14) The PCI CDP includes an Am486 microprocessor in a 168-pin, pin-grid-array package (part U25). The microprocessor is zero-insertion-force (ZIF) socketed and a CPU fan heat sink is provided for cooling. For debugging and analysis, access is provided to the Am486 microprocessor’s JTAG debugging port and to all of the microprocessor signals, and support is provided for Intel-compatible in-circuit emulators. See “Development Support” on page 2-15.
• Static design with Auto Halt power-down support • Wide range of chipsets supporting SMM available to allow product differentiation (the PCI CDP uses the Acer Laboratories Inc.
VOLDET Power Plane 32-Bit Data Bus Clock Interface 32-Bit Data Bus Clock Generator 32-Bit Linear Address Barrel Shifter Register File Descriptor Registers 24 Physical Address ALU Limit and Attribute PLA Cache Unit 2 32 Paging Unit 24 Translation Lookaside Buffer Physical Address 16-Kbyte Cache Prefetcher 32 Micro-instruction Code Stream Floating Point Unit Floating Point Register File Central and Protection Test Unit Control ROM Instruction Decode 24 Address Drivers Write Buffers 4x32
Core Logic Chipset (M8, I13, D15) The PCI CDP uses the Acer Laboratories Inc. FINALi 486 chipset. The chipset consists of two very-large-scale-integration (VLSI) devices that provide bus interface and peripheral functions used in the system, plus an M5042 keyboard and mouse controller. See “Keyboard (O1)” on page 2-31. The M1489 Cache, Memory, and PCI Controller (often called a northbridge chip) interfaces the Am486 microprocessor to the memory and PCI bus.
All PCI bus signals are routed to logic analyzer headers. See “Development Support” on page 2-15. The M1487 ISA Bridge Controller (often called a southbridge chip) interfaces the ISA bus to the PCI bus and provides standard, PC-compatible peripherals devices common to desktop computers.
Onboard Ethernet Controller (F7) The PCI CDP includes an onboard, full-duplex 10/100BaseT Ethernet port based on the AMD Am79C972 PCnet™-FAST+ Ethernet Controller (part U51). A separate voltage regulator provides 3.3-V power for the Ethernet controller. The Ethernet port is part J10 at location E1 on the board. Three LEDs near the port indicate transmit and receive activity and link speed. The link LED lights if 100 Mbit/s operation is established.
The PCnet-FAST+ device supports the industry’s Net PC specification. The PCnetFAST+ device also complies with Microsoft’s PC97 and PC98 requirements by fully supporting the OnNow and ACPI power management initiatives; however, the PCI CDP does not implement OnNow or ACPI. A customer design could support these technologies by using an ATX-style power supply and motherboard design.
Development Support The PCI CDP includes the following facilities for development support: • JTAG port • CPU-bus and PCI-bus logic analyzer headers • Port 80 and Port 680 hexadecimal displays • TIP board interface These features are described in the following paragraphs. JTAG Ports (Q14 and D17) The Am486 microprocessor provides an IEEE Standard 1149.1-1990 (JTAG) compliant test access port and boundary-scan architecture.
Table 2-3. Analyzer Headers 2-16 Part Description Location in Figure 2-3 on Page 2-5 See App.
In addition to the logic analyzer headers, separate three-pin headers are provided for each PCI device’s bus request and bus grant signals. These headers are listed in Table 2-4: Table 2-4. PCI Bus Master Test Points Part Signal Location in Figure 2-3 on Page 2-5 See App.
Test Interface Port (TIP) (A16) The PCI CDP includes a connector for the AMD Test Interface Port (TIP) board. The TIP board is used for testing and debugging AMD embedded product customer development platforms. It connects through a ribbon cable to the TIP connector on the platform. The TIP board provides a collection of peripherals, such as LEDs, hexadecimal displays, an LCD display, two serial ports, a parallel port, an Ethernet controller, and Flash memory, that can be convenient in system development.
PCI Bus (I7) The PCI CDP has two desktop-PC-style PCI expansion connectors (parts SLT1 and SLT2) to allow the installation of a wide array of off-the-shelf 5-V PCI devices. These include standard devices such as video, sound, SCSI, or PCMCIA adapters, or diagnostic devices such as PCI bus analyzers, extender cards, and other diagnostic hardware. The slots do not support 3.3-V PCI peripherals.
Level-2 Cache Memory (K19–N19 and N11) The PCI CDP includes an onboard 512-Kbyte, single-bank, direct-mapped, unified Level-2 cache. This is the largest single-bank cache allowed by the chipset. The cache tag and data static RAM (SRAM) devices are soldered onto the PCI CDP board. A 10-ns tag SRAM device and 15-ns data SRAM devices are used to achieve 2-1-1-1 timing on reads and 2-2-2-2 on writes.
Table 2-7. SIMM Socket Population Chart SIMM 0 SIMM 1 SIMM 2 Single Bank SIMM Single Bank SIMM Single Bank SIMM Double Bank SIMM Single Bank SIMM — NOTE: 32- or 36-bit-wide memory can be used. However, 36-bit EDO SIMMs are accessed as only 32 bits wide because the FINALi chipset does not support EDO SIMMs’ 32-bit data plus 4-bit error correction code (ECC) format. Only traditional byte-wide parity is supported. Boot ROM (C16) The PCI CDP provides a 0.
JP33 (SA18) 1 2 JP32 (SA17) 3 1 2 5V 3 ISA Signal 1 2 3 (SA17 or SA18) Boot ROM ROM Pin (A17 or A18) ROM Jumper Locations Individual Jumper Schematic Figure 2-5. JP32 and JP33 Jumper Configuration (B14–C14) By default, jumpers JP32 and JP33 are not connected, so ROM device pins A17 and A18 are tied High to address the 128-Kbyte BIOS range, E0000h–FFFFFh.
ISA Flash Memory (F20) The PCI CDP includes 1 Mbyte of 16-bit wide AMD Flash memory soldered onto the board and located logically on the ISA Bus. A Vantis MACH programmable logic device is used to control the interface between the ISA bus and the Flash device. This provides an example of how a small amount of ISA Flash memory might be implemented in customer designs. The ISA Flash memory employs one Am29F800 top-sector boot block Flash memory chip (part U58).
(56 Mbyte) 37FFFFFh 3400000h (52 Mbyte) 33FFFFFh EIP Flash Bank 1 EIP Flash Bank 0 3000000h (48 Mbyte) 2FFFFFFh } Accessed as Fourth DRAM Bank (Bank 3) } Enabled Via Chipset Register 12h, Bit 3 EIP Location Depends on DRAM Size DRAM 1000000h (16 Mbyte) FFFFFFh ISA Flash Memory F00000h (15 Mbyte) EFFFFFh DRAM 100000h 128 Kbyte Boot ROM (1 Mbyte) 0FFFFFh DRAM 000000h Figure 2-6.
EIP Flash Memory (L21) The PCI CDP includes 8 Mbytes of Flash memory for execute-in-place (EIP) applications. The EIP Flash memory is implemented in the fourth bank (bank 3) of the DRAM controller’s address space. This memory consists of eight 29F800B top-sector boot block Flash memory devices (parts U61, U62, U63, U64, U65, U66, U67, and U68), soldered to the board and organized as two 32-bit wide Flash memory banks.
Software that writes to the EIP Flash memory must also avoid any back-to-back write cycles (including back-to-back non-burst cycles) to the EIP Flash memory space. For reliable writes, always read or write a different DRAM bank (0, 1 or 2) before and after writes to the EIP space. For example, read location 00000h, write a value to Flash memory, and then read location 00000h again.
Real-Time Clock (G17) The real-time clock (RTC) function in the chipset’s 1487 chip is initially disabled on the PCI CDP. Instead, a separate DS1685 year-2000 (Y2K)-compliant RTC is enabled. The DS1685 provides the features of widely-used, non-Y2K-compliant RTCs such as the DS1287. In addition, the DS1685 provides a byte for storing century information, plus other registers and features not found in older RTC chips. Because of its extra features, the DS1685 RTC is not completely compatible with the DS1287.
ISA Bus Interface (A7) The PCI CDP is populated with two standard ISA bus connectors (parts SL1 and SL2) for developers who need to use ISA devices in their development systems. The ISA bus interface is provided by the chipset’s M1497 southbridge. ISA devices that use the F00000h to FFFFFFh address space cannot be used on the PCI CDP, because this area is used by the ISA Flash memory bank. See “ISA Flash Memory (F20)” on page 2-23.
Serial Ports (E23 and C23) The platform’s Super I/O device includes two 16550-compatible serial ports. These are routed to two 9-pin D-shell connectors, J8 and J9. See Figure 2-7 and Table 28. Light-emitting diodes (LEDs) are provided near each serial port to indicate transmit and receive activity. 1 5 Notes: 6 9 See Figure 2-3 on page 2-5 for connector locations. Figure 2-7. Serial Port Connector Pins (J8, J9) Table 2-8.
Parallel Port (A22) Figure 2-8 and Table 2-9 show the parallel port pinouts. 13 1 Notes: 25 14 See Figure 2-3 on page 2-5 for connector locations. Figure 2-8. Parallel Port Socket (J4) Table 2-9. Parallel Port Pin/Signal Table Pin Signal 1 STRB 2–9 PD0–PD7 10 ACK 11 BUSY 12 PE 13 SLCT 14 AFDT 15 ERROR 16 INIT 17 SLCTIN 18–25 GND Floppy Disk Drive (E20) The PCI CDP’s Super I/O chip provides a floppy disk controller to support the system’s floppy disk drive connector (part J6).
IDE Hard Drive (L4 and M4) The PCI CDP contains two standard 40-pin IDE connectors (parts J5 and J7). The M1498 chip provides the IDE hard drive controller. For details on how to connect a single IDE hard drive to the PCI CDP, see “Board Installation” on page 1-4. An LED is located next to each IDE connector to indicate IDE activity. IDE devices on connector J5 can generate interrupts on IRQ14, and devices on connector J7 can generate interrupts on IRQ15.
CPU Voltage Adjustment (Q15–Q16) The CPU power supply voltage can be adjusted by moving jumper JP4 or both jumpers JP2 and JP3 on the PCI CDP. Selectable voltages are 2.5 V, 3.3 V, 3.45 V, or 5 V. Figure 2-9 shows the default configuration of the CPU voltage jumpers (set for 3.45 V). To select either 3.3-V or 2.5-V CPU voltage, leave JP2 and JP3 set to “ADJ” and move jumper JP4 to the desired voltage. To select 5-V operation, move both jumpers JP2 and JP3 to their “5 V” position. JP2 JP3 ADJ ADJ JP4 3.
Power Supply Connectors (N2 and P2) The PCI CDP accepts standard PC-style motherboard power connectors to supply power to the CPU and all onboard components. To ensure proper functionality of the power module, the board’s PC power supply sockets must be inserted correctly onto the board. ! CAUTION: It is important that the ground wires of one connector are adjacent to the ground wires of the other. See Figure 2-10.
Reset and Interrupt Switches and Headers Three push-button switches are provided so the user can generate RESET, SMI, and NMI events. In addition, a two-pin header is provided for the RESET signal so that an external pushbutton switch can be attached. These switches and headers are routed to the appropriate chipset signals as listed in Table 2-10. Table 2-10. Switch Summary Part Signal Description Location in Figure 2-3 on Page 2-5 See App. B Schematics on: SW1, JP34 PWG Used to reset the system.
Resistor Options The PCI CDP includes a number of resistor populate/depopulate options, which are listed in Table 2-11. Many are used only as manufacturing options, but some may be useful for exploring design options or better emulating a target design. Table 2-11. Resistor Options Part Signal Description Location in Figure 2-3 on Page 2-5 See App. B Schematics on: R11 CLKMUL When R11 is populated and R148 is removed, the clock multiplier for an Am486DX2-66 microprocessor is selected.
Table 2-11. Resistor Options (Continued) Part Signal Description Location in Figure 2-3 on Page 2-5 See App. B Schematics on: R145 KBINHIBIT When R145 is populated and R146 is removed (the default), the M5042 keyboard controller is enabled. D15 (back side) Sheet 25 R146 KBINHIBIT When R145 is populated and R146 is removed (the default), the M5042 keyboard controller is enabled.
Appendix A Default Settings This chapter lists the default settings of the Am486 microprocessor PCI customer development platform when it is shipped. Table A-1. Default Jumper Settings Part Signal Location in Default Position Figure 2-3 on Page 2-5 Position Marking JP2 CPUVCC3 Q15 Pins 2–3 “ADJ” JP3 CPUVCC3 Q16 Pins 2–3 “ADJ” JP4 CPUV1, CPUV2, CPUV3 R15 Pins 1–2 “3.
A-2 Am486® Microprocessor PCI Customer Development Platform User’s Manual
Appendix B Bill of Materials and Schematics The bill of materials for the Am486 microprocessor PCI customer development platform (CDP) begins on page B-2. The actual schematics used to build the PCI CDP begin on page B-10.
Board Bill of Materials (BOM) Item Qty.
Item Qty. Reference Part Package Description 6 10 C33, C41, C42, C43, C46, C56, C57, C60, C66, C154 15 pF 805 RC0805, NPO, ±5%, 50 V 7 1 C40 1000 pF 805 RC0805, 1/8 W, ±5%, 50 V 8 2 C44, C45 39 pF 805 RC0805, NPO, ±5%, 50 V 9 4 C53, C54, C155, C161 10 pF 805 RC0805, NPO, ±5%, 50 V 10 1 C55 22 pF 805 RC0805, NPO, ±5%, 50 V 11 1 C68 6.8 µF C-CASE TANTALUM, C-CASE, 16 V, ±20% 12 2 C86, C78 2.
Item Qty. Reference Part Package Description 22 2 D16, D18 LED (2mA, SOT23) SOT-23 KINGBRIGHT KM-23LEC 23 2 F1, F2 FUSE, 0.5A 1206 BUSSMAN 3216FF-500mA 24 1 HS1 HEATSINK (TO-220) 25 7 JP2, JP3, JP29, JP30, JP31, JP32, JP33 HEADER 3X1 TH-1X3 1X3 HEADER; 0.025” SQ. POST AMP 87224-3 26 1 JP4 HEADER 3X2 TH-2X3 1X3 HEADER; 0.025” SQ. POST AMP 103186-3 27 1 JP34 HEADER 2X1 TH-1X2 1X2 HEADER; 0.025” SQ.
Item Qty.
Item Qty. Reference Part Package Description 58 1 R25 25.5 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V 59 1 R26 15.8 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V 60 10 R28, R94, R97, R135, R136, R137, R138, R156, R158, R160 330 805 RC0805, 1/8 W, ±5%, 50 V 61 1 R29 15.
Item Qty. Reference Part Package Description 75 4 R110, R111, R112, R113 75, 1% 805 RC0805, 1/8 W, ±1%, 50 V 76 3 R114, R115, R117 1.00 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V 77 1 R116 22 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V 78 4 R152, R153, R154, R155 1.
Item Qty. Reference Part Package Description 95 1 U17 IMI SC464 SSOP28 INTL. MICROCKTS. INC. IMISC464AYB 96 1 U21 M1487 PQFP160 ALi M1487 97 1 U22 DS1685-5 DIP24(0.65 0”) DALLAS SEMI.
Item Qty. Reference Part Package Description 115 1 U77 74F32 SO14 SIGNETICS 74F032D 116 1 U78 74F06 SO14 SIGNETICS 74F06D 117 1 U79 M5042 PLCC44 ALi M5042 118 1 U81 NM93C66M8 SO8 NATIONAL NM93C66M8 119 1 U83 74F14 SO14 SIGNETICS 74F14D 120 1 U84 74ABT125 SO14 Signetics 74ABT125D 121 1 Y1 24 MHz_SMD ECLIPTEK ECSMA-24.00MTR 122 1 Y2 14.318 MHz_SMD ECLIPTEK ECSMAT-14.318MTR 123 2 Y4, Y6 32.768 KHz_SMD ECLIPTEK ECPSM29T-32.
Schematics The schematics that follow are the actual CAD schematics used to build the PCI CDP. These schematics are useful for understanding and modifying the PCI CDP. Because the development platform is based on a particular chipset and incorporates many different possible design options, actual Am486 microprocessor-based designs might be considerably different.
1 2 3 4 5 Table of Contents A B Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Am486 Microprocessor PCI Customer Development Platform 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: 13: 14: 15: 16: 17: 18: 19: 20: 21: 22: 23: 24: 25: 26: COVER.SCH CPU.SCH CPU_POWER.SCH CPU_VIS1.SCH CPU_VIS2.SCH M1489.SCH L2_CACHE.SCH SIMM_SKTS.SCH EIP_MEM1.SCH EIP_MEM2.SCH PCI_CONN.SCH PCI_VIS.SCH ENET1.SCH ENET2.SCH IDE.SCH M1487.
1 2 3 4 5 Am486 MICROPROCESSOR, PULLUPS, AND JTAG INTERFACE STPCLKJ PCD_CACH CPURST HITMJ INV A A VCC RP1 1 C K2VCC K2VCC GD31 GD30 GD29 GD28 GD27 GD26 GD25 GD24 GD23 GD22 GD21 GD20 GD19 GD18 GD17 GD16 GD15 GD14 GD13 GD12 GD11 GD10 GD9 GD8 GD7 GD6 GD5 GD4 GD3 GD2 GD1 GD0 C DP0 DP1 DP2 DP3 13 47 83 10 12 44 29 74 INV(DX2INC) HITM#(DX2INC) SRESET CACHE#(DX2INC) STPCLK# M/IO# D/C# W/R# LOCK# PLOCK# ADS# BLAST# BREQ HLDA PWT PCD FERR# A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A1
1 2 3 4 5 POWER CONNECTOR, CPU PULLUPS, CPU POWER SUPPLY, CPU BYPASS CAPACITORS VCC CPUVCC3 HS1 C162 C163 C164 C165 C166 C167 C168 C169 0.015uF 0.015uF 0.015uF 0.015uF 0.1uF 0.1uF 0.1uF 0.1uF R30 K2VCC VCC 1 1 + HEATSINK (TO-220) THERMALLOY C39 0.1uF 10uF A ML32 VCC VCC Q5 TIP127 3 JP2 E C 2 HEADER 3X1 JP3 1 DP[0..3] RP2 10 9 8 7 6 5 4 3 2 DP1 DP2 DP3 DP0 B MIOJ RDYOJ BRDYOJ BOFFJ U6 U6O/P VCC 1 2 3 4 C37 O/P SEN SD GND VIN FB TAP ERR 8 7 6 5 R23 27.
1 2 3 4 5 BUFFERS AND LOGIC ANALYZER HEADERS FOR CPU SIGNALS A A VCC U26 1 48 25 24 GD31 GD30 GD29 GD28 GD27 GD26 GD25 GD24 GD23 GD22 GD21 GD20 GD19 GD18 GD17 GD16 B 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 21 4 10 15 1OE# 2OE# 3OE# 4OE# VCC VCC VCC VCC 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND P36 7 18 31 42 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VGD31 VGD30 VG
1 2 3 4 5 BUFFERS AND LOGIC ANALYZER HEADERS FOR CPU SIGNALS, AND PAL TO AID LOGIC ANALYZER USE VCC U49 1 48 25 24 A BEJ[0..3] BEJ[0..
1 2 3 4 5 FINALi M1489 INTERFACE PARITY HDCSJ3 HDCSJ2 HDCSJ1 HDCSJ0 HDIO16J HDIORDY HDA2 HDA1 HDA0 HDIORJ HDIOWJ A HDD[0..15] R162 *0 R166 *0 R164 *0 R168 *0 PD0 PD1 PD2 PD3 R163 R167 0 R165 0 R169 MDP0 MDP1 MDP2 MDP3 0 0 FOR IDE MASTER: DO NOT POPULATE A VCC HDD0 HDD1 HDD2 HDD3 HDD4 HDD5 HDD6 HDD7 HDD8 HDD9 HDD10 HDD11 HDD12 HDD13 HDD14 HDD15 HDD[0..15] DEVSELJ PAR STOPJ IRDYJ TRDYJ C_BEJ0 C_BEJ1 C_BEJ2 C_BEJ3 FRAMEJ HDRQ1 HDACK1 HDRQ0 HDACK0 HDRQ1 HDACK1 HDRQ0 HDACK0 GA[2..
1 2 3 4 5 L2 CACHE TAG AND DATA SRAMS AND BYTE CONTROL; DRAM SERIES TERMINATION AND WE* FANOUT GD[0..31] GA[4..18] A3II A A3I GD[0..31] GA[4..
1 2 3 4 5 DRAM 72-PIN SIMM SOCKETS VCC 66 48 46 11 70 69 68 67 MRASJ1 B A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IO34 IO33 IO32 IO31 IO30 IO29 IO28 IO27 IO25 IO24 IO23 IO22 IO21 IO20 IO19 IO18 IO16 IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 NC4 NC3 NC2 NC1 PRD3 PRD2 PRD1 PRD0 MRASJ0 MCASJ3 MCASJ2 MCASJ1 MCASJ0 42 41 43 40 47 MWEJ0 CAS3 CAS2 CAS1 CAS0 WE SIMM72 GND GND GND MCASJ[0..
1 2 3 4 5 EIP FLASH MEMORY CONTROLLER VA(2:21) A A Am486 MICROPROCESSOR A(2:22) A(22)=0 U60 Bank1 Cntl. VA(22) VCC R158 330 RSTDRV VGA22 AMA8 VWRJ MRASJ3 MCASJ3 MCASJ2 MCASJ1 MCASJ0 VCPUCLK1 3 4 5 6 7 9 10 11 12 13 16 2 R159 470 B I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 ’ABT244 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 27 26 25 24 23 21 20 19 18 17 REFCIP WRCIP Bank2 Cntl. EIPCE1# EIPCE2# EIPOE1# EIPOE2# 4 ea. 1Mx8 Flash ROM Chips A(22)=1 PAL 4 ea.
1 2 3 4 5 EIP FLASH MEMORY ARRAY GD[0..31] VGA[2..
1 2 3 4 5 PCI PULLUPS AND SLOT CONNECTORS; PCI IDSEL GENERATION VCC VCC VCC RP10 A 2 3 4 5 6 7 8 9 10 FRAMEJ TRDYJ DEVSELJ STOPJ PLOCKJ PAR SERRJ C_BEJ0 C42 15pF O2 C O3 O4 O5 O6 O7 O8 O9 O10 RP11 1 INT0J INT2J INT1J INT3J PREQJ1 PGNTJ2 PREQJ2 2 3 4 5 6 7 8 9 10 4.7K-10P RP9 O2 C O3 O4 O5 O6 O7 O8 O9 O10 1 PGNTJ0 PGNTJ1 PREQJ0 C_BEJ1 C_BEJ2 IRDYJ C_BEJ3 4.
1 2 3 4 5 BUFFERS AND LOGIC ANALYZER HEADERS FOR PCI BUS VCC U36 1 48 25 24 PAD[0..31] JP29 1 2 3 PREQJ0 PGNTJ0 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 A 21 4 10 15 HEADER 3X1 PLACE NEAR PCI0 CONNECTOR 1OE# 2OE# 3OE# 4OE# VPAD[0..
1 2 3 4 5 ETHERNET CONTROLLER, BYPASS CAPACITORS AND POWER SUPPLY FOR ETHERNET CONTROLLER, VCC3 AND SERIAL EEPROMS VCC3 VCC VCC3 EECS_1K ENETPG R105 1K C_BEJ0 C_BEJ1 C_BEJ2 C_BEJ3 PCIID3 FRAMEJ IRDYJ TRDYJ DEVSELJ STOPJ PERRJ SERRJ PAR INT2J PCIRSTJ PREQJ2 PGNTJ2 1 17 18 20 22 23 25 26 28 142 143 146 145 PCICLK3 144 131 132 133 141 5 13 21 29 38 45 53 147 155 65 77 88 101 113 124 136 VDDB VDDB VDDB VDDB VDDB VDDB VDDB PME# WUMI# RWU PG VCC3 EBDA15 EBDA14 EBDA13 EBDA12 EBDA11 EBDA10 EBDA9
1 2 3 4 5 ETHERNET PHY CHIP, ETHERNET CONNECTOR, AND LEDS Y5 A A 1 2 4 3 C98 C99 33pF 25MHz_SMD ECLIPTEK ECSMA-25.00MTR ETXD3 ETXD2 ETXD1 ETXD0_TXDAT TX_CLK_TXCLK TX_EN_TXEN COL_CLSN RX_DV RX_ER_RXDAT RX_CLK_RXCLK ERXD3 ERXD2 ERXD1 ERXD0 CRS_RXEN MDIO VCC MDC 13 15 3 4 5 6 7 8 33 14 34 16 R114 1.00K, 1% MFV0 R115 1.00K, 1% PHY_RST LEDS# R117NET C 38 39 40 41 42 LEDT# LEDR# 32 35 36 R117 1.
1 2 3 4 5 IDE INTERFACE AND BOARD BYPASS CAPACITORS HDD[0..15] VCC Byass Capacitors For The Board VCC RP6 BC3 BC4 BC5 BC6 BC7 BC1 BC2 BC8 BC9 BC10 BC11 BC12 BC13 BC14 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF BC15 BC16 BC17 BC18 BC19 BC20 BC21 BC22 BC23 BC24 BC25 BC26 BC27 BC28 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.
1 2 3 4 5 FINALi M1487 INTERFACE VCC A RP12 1 C 2 3 4 5 6 7 8 9 10 O2 O3 O4 O5 O6 O7 O8 O9 O10 DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 DACK7 DACK6 DACK5 DACK3 DACK2 DACK1 DACK0 IRQ15 IRQ14 IRQ12 IRQ11 IRQ10 IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ1 IRQ8J XBUSCSJ CLEAROKJ CMPGNTJ CMPSTJ ENRTC A VCC TC17 10K-10P C50 C173 C174 0.1uF 0.1uF 0.
1 2 3 4 5 BIOS ROM, ISA SIGNAL SERIES TERMINATION; BATTERY AND SPEAKER CIRCUITS; RESET, SMI, AND NMI PUSHBUTTONS VCC A VCC SA[0..19] SA[0..19] 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 XBUSCSJ MRDJ B GA[2..
1 2 3 4 5 CLOCK GENERATOR A A Y2 1 2 C161 VCC 4 3 C155 B VCC INSTALL PULLUP RESISTOR AND REMOVE 0-OHM RESISTOR FOR 25MHz CPU AND PCI BUS 14.318MHz_SMD VCC OSC U17 R92 R93 4.7K 1 *4.7K 2 CLKOSCOUT 11 10 17 CLKPU2 CLKPU1 R176 18 0 15 U15E 14.318 OSCout S0 S1 S2 DOZE# 10 TC14 + 14 AVDD 28 24 MCLK1 25 MCLK2 B2in B1in ST# R42 CLKAVDD1 R41 OSCin VCC C B R39 4.
1 2 3 4 5 ISA BUS CONNECTORS AND PULLUPS VCC -5V VCC R75 4.
1 2 3 4 5 SUPER I/O CHIP, IrDA INTERFACE, FLOPPY DISK INTERFACE, SERIAL PORT ACTIVITY LEDS Y1 VCC C44 39pF R152 1.5K SD[0..7] SD[0..7] VCC R153 1.
1 2 3 4 5 SERIAL AND PARALLEL PORT INTERFACES VCC RP3 2 3 4 5 6 7 8 9 10 A PP[0..7] PP[0..
1 2 3 4 5 INTERFACE FOR ISA BUS MEMORY AND HEX DISPLAYS LA[17..23] ISAA[1..23] U69 3 4 7 8 13 14 17 18 LA23 LA22 LA21 LA20 LA19 LA18 LA17 A 1 11 BALE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 2 5 6 9 12 15 16 19 RSTDRV IORJ ISAA23 ISAA22 ISAA21 ISAA20 ISAA19 ISAA18 ISAA17 BALE ATCLKO REFRESHJ U55 OE# E VCC SA[0..
1 2 3 4 5 ISA BUS FLASH MEMORY A A ISAD[0..15] ISAA[1..
1 2 3 4 5 OPTIONAL Y2K RTC AND TEST INTERFACE PORT CONNECTOR VCC GA[2..
1 2 3 4 5 PC KEYBOARD AND MOUSE INTERFACE VCC R145 470 KEYBOARD INHIBIT FUNCTION A A KBINHIBIT R146 *2.2K VCC VCC R171 4.7K U78A R172 4.7K F2 FUSE--0.5A 1 B 2 L8 VCC FB 3 R174 1K C157 0.1uF RSTDRV# 5 IORJ XBUSCSJ IOWJ IORJ XBUSCSJ IOWJ 9 7 11 SA2 8 10 28 6 GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 14 15 16 17 18 19 20 21 74F06 7 8 C159 47pF C160 0.
1 2 3 4 5 SOCKET1 Am486 MICROPROCESSOR (PIN #)-PIN DESIGNATION (PIN SIDE VIEW) (1)-D20 (18)-D19 (35)-D11 (52)-D9 (59)-GND (65)-DP1 (71)-GND (77)-GND (83)-INC (89)-GND (95)-GND (101)-GND (107)-D2 (113)-D0 (119)-A31 (136)-A28 (153)-A27 (2)-D22 (19)-D21 (36)-D18 (53)-D13 (60)-VCC (66)-D8 (72)-VCC (78)-D3 (84)-D5 (90)-VCC (96)-D6 (102)-VCC (108)-D1 (114)-A29 (120)-GND (137)-A25 (154)-A26 (3)-TCK (20)-GND (37)-CLK (54)-D17 (61)-D10 (67)-D15 (73)-D12 (79)-DP2 (85)-D
Index Numerics 25-MHz system clock, 33-MHz system clock, B 2-35 2-36 A A17, boot address, 2-6, 2-21, A-1 A18, boot address, 2-6, 2-21, A-1 Am486 microprocessor block diagram, 2-10 overview, 2-8 Am486 microprocessor PCI customer development platform analyzer headers, 2-15 block diagram, 2-4 damage, avoiding, 1-2 default settings, A-1 documentation, xvii features overview, xiii installation requirements, 1-3 installing, 1-4 jumper summary, 2-6, A-1 layout diagram, 2-5 overview diagram, xi, 2-3 purpose, xi r
CPUV3 signal, 2-6, A-1 CPUVCC3, 2-6, A-1 F D debugging monitor, 2-34 support, 2-15 defaults for jumpers and switches, A-1 development support, 2-15 diskette connecting drive, 1-4 starting from, 1-6 DMA controller, 2-12 documentation conventions, xix description of, xvii manual contents, xvii reference material, xviii support, iii DRAM limit without buffering, 2-7 speed limit with EIP, 2-7 using, 2-20 drive See IDE hard drive or floppy disk drive.
installing customer development platform, 1-4 requirements, 1-3 troubleshooting, 1-8 interrupt controller, chipset function, 2-12 interrupt signals DMA channel limitations, 2-7 PCI, 2-19 TIP interface, 2-18 IrDA interface Super I/O, 2-29 ISA bus, 2-28 J J1 connector, 1-5 J2 connector, 1-5 J3 connector, 1-5 J4 connector, 2-30 J5 connector, 1-5, 2-31 J6 connector, 1-4, 2-30 J7 connector, 2-31 J8 connector, 2-29 J9 connector, 2-29 JP2 jumper, 2-6, A-1 JP29 test header, 2-17 JP3 jumper, 2-6, A-1 JP30 test head
N NMI signal, 2-34 nonvolatile data, 2-14 northbridge chip, 2-11 P P36 analyzer header, 2-16 P38 analyzer header, 2-16 P39 analyzer header, 2-16 P40 analyzer header, 2-16 P41 analyzer header, 2-16 P42 analyzer header, 2-16 P43 analyzer header, 2-16 P44 analyzer header, 2-16 P45 analyzer header, 2-16 P46 analyzer header, 2-16 P47 analyzer header, 2-16 parallel port, 2-30 part locations, 2-5 PCI bus arbiter, 2-12 configuration addressing, 2-11 description, 2-19 interrupt signals, 2-19 limitations, 2-7 periph
SMI signal, 2-34 southbridge chip, 2-12 super I/O IrDA interface, 2-29 overview, 2-28 serial ports, 2-29 support, iii SW1 switch, 2-34 SW2 switch, 2-34 SW3 switch, 2-34 switch summary, 2-34 system clock speed, 2-35, W WWW support, iii Y year-2000 (Y2K), 2-36 2-27 Z zero-insertion-force (ZIF) socket, T 2-17 technical support, iii test interface port (TIP), 2-18 test points, PCI, 2-17 third-party support, iii timer, chipset function, 2-12 TIP board, 2-18 TURBO signal, 2-35 U U25 ZIF socket, 2-8 U44
Index-6 Am486® Microprocessor PCI Customer Development Platform User’s Manual
