Intel® Xeon® Processor 5500 Series Datasheet, Volume 1 March 2009 Document Number: 321321-001
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Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ..................................................................................................... 10 1.2 References ....................................................................................................... 12 2 Intel® Xeon® Processors 5500 Series Electrical Specifications ............................... 13 2.1 Processor Signaling ......
6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 Multi-Domain Commands ....................................................................... 125 Client Responses .................................................................................. 125 Originator Responses ............................................................................ 126 Temperature Data ................................................................................ 127 Client Management .........................................................
Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 3-1 3-2 3-3 3-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 7-1 7-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 Active ODT for a Differential Link Example ............................................................ 13 Input Device Hysteresis ..................................................................................... 14 VCC Static and Transient Tolerance Loadlines1,2,3,4.............
8-8 8-9 8-10 8-11 8-12 8-13 8-14 Primary and Secondary Side 3D Height Restriction Zones ...................................... 144 Volumetric Height Keep-Ins............................................................................... 145 Volumetric Height Keep-Ins............................................................................... 146 4-Pin Fan Cable Connector (For Active Heat Sink) ................................................ 147 4-Pin Base Baseboard Fan Header (For Active Heat Sink) ...
6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 7-1 7-2 7-3 7-4 8-1 8-2 8-3 PCIConfigRd() Response Definition .................................................................... 113 PCIConfigWr() Device/Function Support ............................................................. 114 PCIConfigWr() Response Definition .................................................................... 115 Mailbox Command Summary ...................................................
Revision History Document Number Revision Number 321321 001 Description • Initial release Date March 2009 § 8 Intel® Xeon® Processor 5500 Series Datasheet, Volume 1
Introduction 1 Introduction The Intel® Xeon® Processor 5500 Series is the first-generation server/workstation multi-core processor to implement key new technologies: • Integrated Memory Controller • Point-to-point link interface based on Intel® QuickPath Technology The processor is optimized for performance with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems.
Introduction • 1-Socket Workstation Platforms support Intel Xeon Processor 5500 Series SKUs. These platforms enable a wide range of options for either the performance, power, or cost sensitive customer. Note: All references to “chipset” in this document pertain to the Intel® 5520 chipset and Intel® 5500 chipset, unless specifically stated otherwise. Table 1-1. Intel Xeon Processor 5500 Series Feature Set Overview Feature 1.
Introduction • Intel Xeon Processor 5500 Series — Includes processor substrate and integrated heat spreader (IHS). • Integrated Memory Controller (IMC) — As the term implies, the Memory Controller is integrated on the processor die. • Intel QuickPath Interconnect (Intel® QPI) — A cache-coherent, link-based Interconnect specification for Intel processors, chipsets, and I/O bridge components.
Introduction 1.2 References Platform designers are strongly encouraged to maintain familiarity with the most up-todate revisions of processor and platform collateral. Table 1-2.
Intel® Xeon® Processors 5500 Series Electrical Specifications 2 Intel® Xeon® Processors 5500 Series Electrical Specifications 2.1 Processor Signaling Intel® Xeon® Processor 5500 Series include 1366 lands, which utilize various signaling technologies. Signals are grouped by electrical characteristics and buffer type into various signal groups.
Intel® Xeon® Processors 5500 Series Electrical Specifications 2.1.3 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The Intel Xeon Processor 5500 Series contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Intel® Xeon® Processors 5500 Series Electrical Specifications DDR3 memory frequency are set during manufacturing. It is possible to override the processor core frequency setting using software. This permits operation at lower core frequencies than the factory set maximum core frequency. The processor core frequency is configured during reset by using values stored within the device during manufacturing. The stored value sets the lowest core multiplier at which the particular processor can operate.
Intel® Xeon® Processors 5500 Series Electrical Specifications 2.1.7.1 Power and Ground Lands For clean on-chip power distribution, processors include lands for all required voltage supplies. These include: • 210 each VCC (271 ea. VSS) lands must be supplied with the voltage determined by the VID[7:0] signals. Table 2-2 defines the voltage level associated with each core VID pattern. Table 2-9 and Figure 2-3 represent VCC static and transient limits. • 3 each VCCPLL lands, connected to a 1.
Intel® Xeon® Processors 5500 Series Electrical Specifications The Intel Xeon Processor 5500 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This is represented by a DC shift in the loadline. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the maximum specified VID are not permitted.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-2.Voltage Identification Definition (Sheet 2 of 5) 18 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 0 0 0 1 1 1 1 0 1.42500 0 0 0 1 1 1 1 1 1.41875 0 0 1 0 0 0 0 0 1.41250 0 0 1 0 0 0 0 1 1.40625 0 0 1 0 0 0 1 0 1.40000 0 0 1 0 0 0 1 1 1.39375 0 0 1 0 0 1 0 0 1.38750 0 0 1 0 0 1 0 1 1.38125 0 0 1 0 0 1 1 0 1.37500 0 0 1 0 0 1 1 1 1.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-2.Voltage Identification Definition (Sheet 3 of 5) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 0 1 0 0 1 0 0 0 1.16250 0 1 0 0 1 0 0 1 1.15625 0 1 0 0 1 0 1 0 1.15000 0 1 0 0 1 0 1 1 1.14375 0 1 0 0 1 1 0 0 1.13750 0 1 0 0 1 1 0 1 1.13125 0 1 0 0 1 1 1 0 1.12500 0 1 0 0 1 1 1 1 1.11875 0 1 0 1 0 0 0 0 1.11250 0 1 0 1 0 0 0 1 1.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-2.Voltage Identification Definition (Sheet 4 of 5) 20 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 0 1 1 1 0 0 1 0 0.90000 0 1 1 1 0 0 1 1 0.89375 0 1 1 1 0 1 0 0 0.88750 0 1 1 1 0 1 0 1 0.88125 0 1 1 1 0 1 1 0 0.87500 0 1 1 1 0 1 1 1 0.86875 0 1 1 1 1 0 0 0 0.86250 0 1 1 1 1 0 0 1 0.85625 0 1 1 1 1 0 1 0 0.85000 0 1 1 1 1 0 1 1 0.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-2.Voltage Identification Definition (Sheet 5 of 5) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 1 0 0 1 1 1 0 0 0.63750 1 0 0 1 1 1 0 1 0.63125 1 0 0 1 1 1 1 0 0.62500 1 0 0 1 1 1 1 1 0.61875 1 0 1 0 0 0 0 0 0.61250 1 0 1 0 0 0 0 1 0.60625 1 0 1 0 0 0 1 0 0.60000 1 0 1 0 0 0 1 1 0.59375 1 0 1 0 0 1 0 0 0.58750 1 0 1 0 0 1 0 1 0.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-3. Power-On Configuration (POC[7:0]) Decode Function Bits POC Settings VR_Key VID[7] 0b for VR11.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-4. VTT Voltage Identification Definition VID7 2.1.8 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VR 11.0 Voltage VTT_TYP (Voltage + Offset) 0 1 0 0 0 0 1 0 1.200V 1.220V 0 1 0 0 0 1 1 0 1.175V 1.195V 0 1 0 0 1 0 1 0 1.150V 1.170V 0 1 0 0 1 1 1 0 1.125V 1.145V 0 1 0 1 0 0 1 0 1.100V 1.120V 0 1 0 1 0 1 1 0 1.075V 1.095V 0 1 0 1 1 0 1 0 1.050V 1.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-5.
Intel® Xeon® Processors 5500 Series Electrical Specifications Notes: 1. Refer to Section 4 for land assignments and Section 5 for signal definitions. 2. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel1 and DDR3 Channel 2. Signals that include on-die termination (ODT) are listed in Table 2-6. Table 2-6.
Intel® Xeon® Processors 5500 Series Electrical Specifications 2. Processors must operate at the same core frequency. Note, processors within the same power-optimization segment supporting different maximum core frequencies (e.g. a 2.93 GHz / 95 W and 2.66 GHz / 95 W) can be operated within a system. However, both must operate at the highest frequency rating commonly supported. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel. 3.
Intel® Xeon® Processors 5500 Series Electrical Specifications At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded.
Intel® Xeon® Processors 5500 Series Electrical Specifications 2.6 Processor DC Specifications DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temperature (TCASE specified in Section 6), clock frequency, and input voltages. Care should be taken to read all notes associated with each specification. Table 2-8. Voltage and Current Specifications (Sheet 1 of 2) Symbol Voltage Plane Min 0.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-8. Voltage and Current Specifications (Sheet 2 of 2) Symbol ICC_TDC ICCPLL_TDC IDDQ_TDC ITT_TDC IDDQ_S3 Parameter Voltage Plane Min Typ Max Unit Notes1 Thermal Design Current: Intel Xeon Processor W5580 (TDP = 130W) (Launch - FMB) VCC VCCPLL VDDQ VTTA VTTD 110 1.1 9 6 22 A A A A A 11,12 Thermal Design Current: Intel Xeon Processor 5500 Series Advanced SKU (TDP = 95W) (Launch - FMB) VCC VCCPLL VDDQ VTTA VTTD 85 1.
Intel® Xeon® Processors 5500 Series Electrical Specifications drawing ICC_MAX for up to 10 ms. Refer to Figure 2-5 through Figure 2-8 for further details on the average processor current draw over various time durations. 8. Refer to Table 2-11 and corresponding Figure 2-10. The processor should not be subjected to any static VTT level that exceeds the VTT_MAX associated with any particular current. Failure to adhere to this specification can shorten processor lifetime. 9.
Intel® Xeon® Processors 5500 Series Electrical Specifications 2. 3. This table is intended to aid in reading discrete points on Figure 2-3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_SENSE lands. Please refer to the appropriate platform design guide for further details on regulator and decoupling implementations.
Intel® Xeon® Processors 5500 Series Electrical Specifications Figure 2-4. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID Notes: 1. VOS is the measured overshoot voltage. 2. TOS is the measured time duration above VID. 2.6.
Intel® Xeon® Processors 5500 Series Electrical Specifications Figure 2-5. Load Current Versus Time (130W TDP Processor)1,2 155 150 Sustained Current (A) 145 140 135 130 125 120 115 110 105 0.01 0.1 1 10 100 1000 Time Duration, (s) Notes: 1. 2. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. Not 100% tested. Specified by design characterization.
Intel® Xeon® Processors 5500 Series Electrical Specifications Figure 2-6. Load Current Versus Time (95W TDP Processor)1,2 125.0 120.0 Sustained Current (A) 115.0 110.0 105.0 100.0 95.0 90.0 85.0 80.0 0.01 0.1 1 10 100 1000 Time Duration, (s) Notes: 1. 2. 34 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. Not 100% tested. Specified by design characterization.
Intel® Xeon® Processors 5500 Series Electrical Specifications Figure 2-7. Load Current Versus Time (80W TDP Processor)1,2 105 100 Sustained Current (A) 95 90 85 80 75 70 65 0.01 0.1 1 10 100 1000 Time Duration, (s) Notes: 1. 2. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. Not 100% tested. Specified by design characterization.
Intel® Xeon® Processors 5500 Series Electrical Specifications Figure 2-8. Load Current Versus Time (60W TDP Processor)1,2 85 Sustained Current (A) 80 75 70 65 60 55 0.01 0.1 1 10 100 1000 Time Duration, (s) Notes: 1. 2. 36 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. Not 100% tested. Specified by design characterization.
Intel® Xeon® Processors 5500 Series Electrical Specifications Figure 2-9. Load Current Versus Time (38W TDP Processor)1,2 45 Sustained Current (A) 40 35 30 25 20 0.01 0.1 1 10 100 1000 Time Duration, (s) Notes: 1. 2. Table 2-11. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. Not 100% tested. Specified by design characterization.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-11. VTT Static and Transient Tolerance (Sheet 2 of 2) ITT (A) VTT_Max (V) VTT_Typ (V) VTT_Min (V) 13 VTT_VID - 0.0465 VTT_VID - 0.0780 VTT_VID - 0.1095 14 VTT_VID - 0.0525 VTT_VID - 0.0840 VTT_VID - 0.1155 15 VTT_VID - 0.0585 VTT_VID - 0.0900 VTT_VID - 0.1215 16 VTT_VID - 0.0645 VTT_VID - 0.0960 VTT_VID - 0.1275 17 VTT_VID - 0.0705 VTT_VID - 0.1020 VTT_VID - 0.1335 18 VTT_VID - 0.0765 VTT_VID - 0.
Intel® Xeon® Processors 5500 Series Electrical Specifications Figure 2-10. VTT Static and Transient Tolerance Loadlines 0 5 10 ITT [A] 15 20 25 0.0500 0.0375 0.0250 0.0125 0.0000 VTT_VID DevIatIon -0.0125 -0.0250 -0.0375 -0.0500 -0.0625 -0.0750 -0.0875 -0.1000 -0.1125 -0.1250 -0.1375 -0.1500 -0.1625 -0.1750 -0.1875 -0.2000 -0.2125 Notes: 1. The VTT_MIN and VTT_MAX loadlines represent static and transient limits. Each is characterized by a ±31.5 mV offset from VTT_TYP. 2.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-12. DDR3 Signal Group DC Specifications (Sheet 2 of 2) Symbol Parameter Min ILI Input Leakage Current Typ Max Units Notes1 N/A N/A ± 500 mA DDR_COMP0 COMP Resistance 99 100 101 Ω 8 DDR_COMP1 COMP Resistance 24.65 24.9 25.15 Ω 8 DDR_COMP2 COMP Resistance 128.7 130 131.3 Ω 8 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-14. RESET# Signal DC Specifications Symbol Parameter VIL Input Low Voltage VIH Input High Voltage RON Processor Sideband Buffer On Resistance ILI Min Typ Units 0.60 * VTTA V 2,3 V 2,3,5 0.70 * VTTA 10 Input Leakage Current Notes1 Max 18 Ω ± 200 μA 4 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Intel® Xeon® Processors 5500 Series Electrical Specifications Table 2-17. Control Sideband Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Voltage 0.64 * VTTA V 2,3 VIL Input Low Voltage for PECI_ID signal 0.15 * VTTA V 2,3 VIH Input High Voltage 0.76 * VTTA V 2,3 VIH Input High Voltage for PECI_ID signal 0.
Package Mechanical Specifications 3 Package Mechanical Specifications 3.1 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA1366 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications 3.1.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: 1. Package reference with tolerances (total height, length, width, etc.) 2. IHS parallelism and tilt 3. Land dimensions 4. Top-side and back-side component keep-out dimensions 5. Reference datums 6. All drawing dimensions are in mm. 7.
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications 3.1.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Do not contact the Test Pad Area with conductive material. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.
Package Mechanical Specifications 3.1.6 Processor Mass Specification The typical mass of the processor is 35 grams. This mass [weight] includes all the components that are included in the package. 3.1.7 Processor Materials Table 3-3 lists some of the package components and associated materials. Table 3-3. Processor Materials Component 3.1.
Land Listing 4 Land Listing 4.1 Intel® Xeon® Processors 5500 Series Pin Assignments This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number. Note: A land name prefixed with a FC denotes a Future Connect land. 4.1.1 Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 1 of 36) Land Name BCLK_DN Table 4-1.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 3 of 36) Land No. Buffer Type Direction AW37 QPI I QPI0_DRX_DP[6] BA38 QPI QPI0_DRX_DP[7] AU39 QPI QPI0_DRX_DP[8] AW40 QPI0_DRX_DP[9] AU40 QPI0_DTX_DN[0] QPI0_DTX_DN[1] QPI0_DTX_DN[10] QPI0_DTX_DN[11] Table 4-1. Land Listing by Land Name (Sheet 4 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 5 of 36) Table 4-1. Land Listing by Land Name (Sheet 6 of 36) Land Name Land No. Buffer Type Direction Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 7 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 9 of 36) Land No. Buffer Type Direction DDR0_DQS_N[7] W1 CMOS I/O DDR0_DQS_N[8] D35 CMOS DDR0_DQS_N[9] V42 CMOS DDR0_DQS_P[0] T43 DDR0_DQS_P[1] L41 DDR0_DQS_P[10] DDR0_DQS_P[11] DDR0_DQS_P[12] DDR0_DQS_P[13] Land Name Table 4-1. Land Listing by Land Name (Sheet 10 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 11 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 13 of 36) Table 4-1. Land Listing by Land Name (Sheet 14 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 15 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 17 of 36) Land No. Buffer Type Direction DDR2_DQS_N[7] T8 CMOS I/O DDR2_DQS_N[8] G30 CMOS DDR2_DQS_N[9] T35 CMOS DDR2_DQS_P[0] W37 DDR2_DQS_P[1] T37 Land Name Table 4-1. Land Listing by Land Name (Sheet 18 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 19 of 36) Land Name RSVD Land No. Buffer Type Table 4-1. Direction Land Listing by Land Name (Sheet 20 of 36) Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 21 of 36) Land No. Buffer Type VCC AL21 PWR VCC AL24 VCC AL25 VCC VCC Table 4-1. Land Listing by Land Name (Sheet 22 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 23 of 36) Land No. Buffer Type VCC AT27 PWR VCC AT28 VCC AT30 VCC VCC Table 4-1. Land Listing by Land Name (Sheet 24 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 25 of 36) Table 4-1. Land Listing by Land Name (Sheet 26 of 36) Land No. Buffer Type VCC BA18 PWR VDDQ VCC BA19 PWR VDDQ B7 PWR VCC BA24 PWR VDDQ C10 PWR VCC BA25 PWR VDDQ C15 PWR VCC BA27 PWR VDDQ C20 PWR VCC BA28 PWR VDDQ C25 PWR VCC BA30 PWR VDDQ C30 PWR Land Name Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 27 of 36) Table 4-1. Land Listing by Land Name (Sheet 28 of 36) Land No. Buffer Type Direction VID[4]/CSC[1] AN10 CMOS O VSS VID[5]/CSC[2] AP9 CSMO O VSS AH1 GND VID[6] AP8 CMOS O VSS AH34 GND VID[7] AN8 CMOS O VSS AH37 GND VSS A35 GND VSS AH39 GND VSS A39 GND VSS AH7 GND VSS A4 GND VSS AJ34 GND VSS A41 GND VSS AJ36 GND VSS A6 GND VSS AJ41 GND Land Name Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 29 of 36) Land No. Buffer Type VSS AM11 GND VSS AM14 VSS AM17 VSS VSS Table 4-1. Land Listing by Land Name (Sheet 30 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 31 of 36) Land No. Buffer Type VSS AU29 GND VSS AU32 VSS AU35 VSS VSS Table 4-1. Land Listing by Land Name (Sheet 32 of 36) Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 33 of 36) Table 4-1. Land Listing by Land Name (Sheet 34 of 36) Land No. Buffer Type VSS G7 GND VSS VSS H10 GND VSS N5 GND VSS H30 GND VSS P11 GND VSS H35 GND VSS P3 GND VSS H40 GND VSS P33 GND Land Name Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 35 of 36) Land No. Buffer Type VTTA AE10 PWR VTTA AE11 VTTA AE33 VTTA VTTA Land Name Table 4-1. Land Listing by Land Name (Sheet 36 of 36) Land No.
Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 1 of 35) Land No. A4 Land Name VSS Buffer Type Direction Table 4-2. Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 3 of 35) Land Name Buffer Type Direction AC33 VTTD PWR AC34 VTTD AC35 VTTD AC36 VSS GND AC37 CAT_ERR# GTL I/O AC38 QPI0_DTX_DN[16] QPI AC39 QPI0_DTX_DP[16] QPI AC40 QPI0_DTX_DN[15] AC41 QPI0_DTX_DP[15] AC42 AC43 Table 4-2. Land No.
Land Listing Table 4-2. Land No. AG4 Land Listing by Land Number (Sheet 5 of 35) Land Name Buffer Type Direction RSVD Table 4-2. Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 7 of 35) Land Name Buffer Type Direction Table 4-2. Land No.
Land Listing Table 4-2. Land No. AM12 Land Listing by Land Number (Sheet 9 of 35) Land Name Buffer Type Direction Table 4-2. Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 11 of 35) Land Name Buffer Type AP6 VSS AP7 PSI# CMOS AP8 VID[6] CMOS AP9 VID[5]/CSC[2] CMOS Direction GND Table 4-2. Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 13 of 35) Land No. Land Name AR43 Table 4-2. Land Listing by Land Number (Sheet 14 of 35) Buffer Type Direction Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 15 of 35) Land Name Table 4-2. Buffer Type Direction Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 17 of 35) Land Name AW31 VCC AW32 AW33 Buffer Type Direction Table 4-2. Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 19 of 35) Land Name Table 4-2. Buffer Type Direction Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 21 of 35) Land Name Table 4-2. Buffer Type Direction Land No.
Land Listing Table 4-2. Land No. 78 Land Listing by Land Number (Sheet 23 of 35) Land Name Table 4-2. Buffer Type Direction Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 25 of 35) Land Name Table 4-2. Buffer Type Direction Land No.
Land Listing Table 4-2. Land No. 80 Land Listing by Land Number (Sheet 27 of 35) Land Name Buffer Type J18 VDDQ J19 DDR0_CLK_P[0] CLOCK J20 DDR2_MA[3] CMOS J21 DDR2_CLK_N[0] CLOCK J22 DDR2_CLK_P[0] CLOCK Direction PWR J23 VDDQ J24 DDR2_MA[7] CMOS J25 DDR2_PAR_ERR#[1] J26 DDR2_CKE[0] J27 DDR1_MA[6] J28 VDDQ J29 RSVD J30 DDR2_ECC[5] Table 4-2. Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 29 of 35) Land Name Table 4-2. Buffer Type Direction Land No.
Land Listing Table 4-2. Land No. Land Name Table 4-2. Buffer Type Direction Land No.
Land Listing Table 4-2. Land No. Land Listing by Land Number (Sheet 33 of 35) Table 4-2. Land Listing by Land Number (Sheet 34 of 35) Buffer Type Direction Land No.
Land Listing Table 4-2. Land No.
Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (Sheet 1 of 4) Name Type Description BCLK_DN BCLK_DP I Differential bus clock input to the processor. BCLK_ITP_DN BCLK_ITP_DP O Buffered differential bus clock pair to ITP. BPM#[7:0] I/O BPM#[7:0] are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance.
Signal Definitions Table 5-1. Signal Definitions (Sheet 2 of 4) Name Type Description DDR_THERM# I DDR_THERM# is used for imposing duty cycle throttling on all memory channels. The platform should ensure that DDR_THERM# is exerted when any DIMM is over T64 (85 °C) DDR{0/1/2}_BA[2:0] O Defines the bank which is the destination for the current Activate, Read, Write, or Precharge command. DDR{0/1/2}_CAS# O Column Address Strobe. DDR{0/1/2}_CKE[3:0] O Clock Enable.
Signal Definitions Table 5-1. Signal Definitions (Sheet 3 of 4) Name Type Description PSI# O Processor Power Status Indicator signal. This signal is asserted when maximum possible processor core current consumption is less than 20A, Assertion of this signal is an indication that the VR controller does not currently need to be able to provide ICC above 20A, and the VR controller can use this information to move to more efficient operation point. This signal will de-assert at least 3.
Signal Definitions Table 5-1. Signal Definitions (Sheet 4 of 4) Name Type Description VTT_VID[4:2] O VTT_VID[4:2] is used to support automatic selection of power supply voltages (VTT). The voltage supply for this signal must be valid before the VR can supply VTT to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signal become valid. The VID signal is needed to support the processor voltage specification variations.
Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Intel® Xeon® processor 5500 series requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system. Maintaining the proper thermal environment is key to reliable, long-term system operation.
Thermal Specifications The Intel Xeon Processor W5580 (see Figure 6-1; Table 6-2) supports a single Thermal Profile. For this processor, it is expected that the Thermal Control Circuit (TCC) would only be activated for very brief periods of time when running the most power-intensive applications. Refer to the Intel® Xeon® Processor 5500 Series Thermal / Mechanical Design Guide (TMDG) for details on system thermal solution design, thermal profiles and environmental considerations.
Thermal Specifications designed to the Flexible Motherboard (FMB) guidelines, even if a processor with lower power dissipation is currently planned. The Adaptive Thermal Monitor feature must be enabled for the processor to remain within its specifications. Table 6-1. Intel Xeon Processor W5580 Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes 130 5 See Figure 6-2; Table 6-4 1, 2, 3, 4, 5 Notes: 1.
Thermal Specifications Table 6-2. Table 6-3. Intel Xeon Processor W5580 Thermal Profile Power (W) TCASE_MAX (°C) 0 43.5 5 44.4 10 45.3 15 46.2 20 47.1 25 48.0 30 48.9 35.6 49.9 40 50.7 45 51.6 50 52.6 55 53.5 60 54.4 65 55.3 70 56.2 75 57.1 80 58.0 85 58.9 90 59.8 95 60.7 100 61.6 105 62.5 110 63.4 115 64.3 120 65.2 125 66.1 130 67.
Thermal Specifications Figure 6-2. Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile 85 80 T C A S E _ M A X is a th erm a l so lu tio n d e s ig n p o in t. In ac tu ality, u n its w ill n o t s ig n ific an tly e x ce e d T C A S E _M A X _ A d u e to T C C ac tiv a tio n . 75 Thermal Profile B Y = 0.244*p + 57.8 Temperature [C] 70 65 60 55 50 45 40 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 Power [W] Notes: 1.
Thermal Specifications Table 6-4. Table 6-5. 94 Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile A Power (W) TCASE_MAX (°C) 0 57.8 5 58.7 10 59.6 15 60.5 20 61.4 25 62.3 30 63.2 35.6 64.2 40 65.0 45 65.9 50 66.9 55 67.8 60 68.7 65 69.6 70 70.5 75 71.4 80 72.3 85 73.2 90 74.1 95 75.0 Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile B Power (W) TCASE_MAX (°C) 0 57.8 5 59.0 10 60.2 15 61.5 20 62.7 25 63.9 30 65.1 35 66.
Thermal Specifications Table 6-6. Intel Xeon Processor 5500 Series Standard/Basic SKUs Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) 80 5 See Figure 6-3; Table 6-7; Notes 1, 2, 3, 4, 5 Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC.
Thermal Specifications Table 6-7. Intel Xeon Processor 5500 Series Standard/Basic SKUs Thermal Profile Power (W) TCASE_MAX (°C) 0 51.8 5 53.3 10 54.8 15 56.3 20 57.9 25 59.4 30 60.9 35 62.4 40 63.9 45 65.4 50 67.0 55 68.5 60 70.0 65 71.5 70 73.0 75 74.5 80 76.0 Table 6-8.
Thermal Specifications Figure 6-4. Intel Xeon Processor 5500 Series Low Power SKU Thermal Profile Notes: 1. Intel Xeon processor 5500 series Low Power SKU Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-9 for discrete points that constitute the thermal profile. 2. Implementation of Intel Xeon processor 5500 series Low Power SKU Thermal Profile should result in virtually no TCC activation.
Thermal Specifications Table 6-9. Intel Xeon Processor 5500 Series Low Power SKU Thermal Profile Power (W) TCASE_MAX (°C) 0 51.9 5 53.4 10 54.9 15 56.4 20 57.9 25 59.5 30 61.0 35 62.5 40 64.0 45 65.5 50 67.0 55 68.5 60 70.0 Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC.
Thermal Specifications Figure 6-5. Intel Xeon Processor L5518 Thermal Profile Notes: 1. Intel Xeon Processor L5518 Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-11 for discrete points that constitute the thermal profile. 2. Implementation of Intel Xeon Processor L5518 nominal and short-term thermal profiles should result in virtually no TCC activation.
Thermal Specifications Table 6-11. Intel Xeon Processor L5518 Thermal Profile Power (W) Nominal TCASE_MAX (°C) Short-term TCASE_MAX (°C) 0 51.9 66.9 5 53.4 68.4 10 54.9 69.9 15 56.4 71.4 20 57.9 72.9 25 59.5 74.5 30 61.0 76.0 35 62.5 77.5 40 64.0 79.0 45 65.5 80.5 50 67.0 82.0 55 68.5 83.5 60 70.0 85.0 Notes: 1. These values are specified at VCC_MAX for all processor frequencies.
Thermal Specifications Figure 6-6. Intel Xeon Processor L5508 Thermal Profile Notes: 1. Intel Xeon Processor L5508 Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-13 for discrete points that constitute the thermal profile. 2. Implementation of Intel Xeon Processor L5508 nominal and short-term thermal profiles should result in virtually no TCC activation.
Thermal Specifications Table 6-13. Intel Xeon Processor L5508 Thermal Profile Power (W) Nominal TCASE_MAX (°C) Short-Term TCASE_MAX (°C) 0 50.0 65.0 5 52.7 67.7 10 55.3 70.3 15 58.0 73.0 20 60.6 75.6 25 63.3 78.3 30 66.0 81.0 35 68.6 83.6 38 70.2 85.2 Notes: 1. These values are specified at VCC_MAX for all processor frequencies.
Thermal Specifications 6.1.2 Thermal Metrology The minimum and maximum case temperatures (TCASE) are specified in Table 6-6, through Table 6-13 and are measured at the geometric top center of the processor integrated heat spreader (IHS). Figure 6-7 illustrates the location where TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel® Xeon® Processor 5500 Series Thermal / Mechanical Design Guide. Figure 6-7.
Thermal Specifications 6.2 Processor Thermal Features 6.2.1 Processor Temperature A new feature in the Intel Xeon processor 5500 series is a software readable field in the IA32_TEMPERATURE_TARGET register that contains the minimum temperature at which the TCC will be activated and PROCHOT# will be asserted.
Thermal Specifications 6.2.2.1 Frequency/VID Control The processor uses Frequency/VID control whereby TCC activation causes the processor to adjust its operating frequency (via the core ratio multiplier) and input voltage (via the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption. This method includes multiple operating points, each consisting of a specific operating frequency and voltage.
Thermal Specifications 6.2.2.2 Clock Modulation Clock modulation is performed by alternately turning the clocks off and on at a duty cycle specific to the processor (factory configured to 37.5% on and 62.5% off). The period of the duty cycle is configured to 32 microseconds when the TCC is active. Cycle times are independent of processor frequency.
Thermal Specifications PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power.
Thermal Specifications Table 6-14. Summary of Processor-specific PECI Commands Command Supported on Intel Xeon Processor 5500 Series CPU Ping() Yes GetDIB() Yes GetTemp() Yes PCIConfigRd() Yes PCIConfigWr() Yes MbxSend() MbxGet() 1 Yes 1 Yes Note: 1. Refer to Table 6-19 for a summary of mailbox commands supported by the Intel Xeon processor 5500 series CPU. 6.3.
Thermal Specifications 6.3.1.3 Processor Interface Tuning and Diagnostics Intel Xeon processor 5500 series Intel IBIST allows for in-field diagnostic capabilities in Intel QuickPath Interconnect and memory controller interfaces. PECI provides a port to execute these diagnostics via its PCI Configuration read and write capabilities. 6.3.2 Client Command Suite 6.3.2.1 Ping() Ping() is a required message for all PECI devices.
Thermal Specifications Figure 6-11. GetDIB() Byte # Byte Definition 6.3.2.2.2 0 1 2 3 4 Client Address Write Length 0x01 Read Length 0x08 Cmd Code 0xf7 FCS 5 6 7 8 9 Device Info Revision Number Reserved Reserved Reserved 10 11 12 13 Reserved Reserved Reserved FCS Device Info The Device Info byte gives details regarding the PECI client configuration. At a minimum, all clients supporting GetDIB will return the number of domains inside the package via this field.
Thermal Specifications 6.3.2.3 GetTemp() The GetTemp() command is used to retrieve the temperature from a target PECI address. The temperature is used by the external thermal management system to regulate the temperature on the die. The data is returned as a negative value representing the number of degrees centigrade below the Thermal Control Circuit Activation temperature of the PECI device. Note that a value of zero represents the temperature at which the Thermal Control Circuit activates.
Thermal Specifications 6.3.2.3.2 Supported Responses The typical client response is a passing FCS and good thermal data. Under some conditions, the client’s response will indicate a failure. Table 6-15. GetTemp() Response Definition Response Meaning General Sensor Error (GSE) 6.3.2.4 Thermal scan did not complete in time. Retry is appropriate. 0x0000 Processor is running at its maximum temperature or is currently being reset.
Thermal Specifications Description: Returns the data maintained in the PCI configuration space at the PCI configuration address sent. The Read Length dictates the desired data return size. This command supports byte, word, and dword responses as well as a completion code. All command responses are prepended with a completion code that includes additional pass/fail status information. Refer to Section 6.3.4.2 for details regarding completion codes. Figure 6-17.
Thermal Specifications Table 6-17. PCIConfigWr() Device/Function Support Writable Description Device Function 2 1 Intel QuickPath Interconnect Link 0 Intel IBIST 2 5 Intel QuickPath Interconnect Link 1 Intel IBIST 3 4 Memory Controller Intel IBIST1 4 3 Memory Controller Channel 0 Thermal Control / Status 5 3 Memory Controller Channel 1 Thermal Control / Status 6 3 Memory Controller Channel 2 Thermal Control / Status Notes: 1.
Thermal Specifications Figure 6-18. PCIConfigWr() Byte # Byte Definition 0 1 2 3 Client Address Write Length {0x07,0x08,0x10} Read Length 0x01 Cmd Code 0xc5 4 LSB 5 6 PCI Configuration Address 8 LSB WL AW FCS 7 MSB WL-1 Data (1, 2 or 4 bytes) MSB WL+1 WL+2 WL+3 FCS Completion Code FCS Note that the 4-byte PCI configuration address and data defined above are sent in standard PECI ordering with LSB first and MSB last. 6.3.2.5.
Thermal Specifications 6.3.2.6.1 Capabilities Table 6-19. Mailbox Command Summary Command Name Request Type Code (byte) MbxSend Data (dword) MbxGet Data (dword) Description Ping 0x00 0x00 0x00 Verify the operability / existence of the Mailbox. Thermal Status Read/Clear 0x01 Log bit clear mask Thermal Status Register Read the thermal status register and optionally clear any log bits.
Thermal Specifications These status bits are a subset of the bits defined in the IA32_THERM_STATUS MSR on the processor, and more details on the meaning of these bits may be found in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Vol. 3B. Both status and sticky log bits are managed in this status word. All sticky log bits are set upon a rising edge of the associated status bit, and the log bits are cleared only by Thermal Status reads or a processor reset.
Thermal Specifications 6.3.2.6.5 Icc-TDC Read Icc-TDC is the Intel Xeon processor 5500 series TDC current draw specification. This data may be used to confirm matching Icc profiles of processors in DP configurations. It may also be used during the processor boot sequence to verify processor compatibility with motherboard Icc delivery capabilities. This command returns Icc-TDC in units of 1 Amp. 6.3.2.6.6 TCONTROL Read TCONTROL is used for fan speed control management.
Thermal Specifications Table 6-21. Machine Check Bank Definitions 6.3.2.6.
Thermal Specifications managed only in the PECI domain. In-band software may not manipulate or read the PECI T-state control setting. In the event that multiple agents are requesting T-state throttling simultaneously, the CPU always gives priority to the lowest power setting, or the numerically lowest duty cycle. On Intel Xeon processor 5500 series, the only supported duty cycle is 12.5% (12.5% clocks on, 87.5% clocks off).
Thermal Specifications Figure 6-23. MbxSend() Command Data Format 1 0 Byte # Byte Definition 2 Request Type 3 4 Data[31:0] Because a particular MbxSend() command may specify an update to potentially critical registers inside the processor, it includes an Assured Write FCS (AW FCS) byte as part of the write data payload. In the event that the AW FCS mismatches with the clientcalculated FCS, the client will abort the write and will always respond with a bad Write FCS. 6.3.2.7.
Thermal Specifications Note that the 4-byte data defined above is sent in standard PECI ordering with LSB first and MSB last. Table 6-23. MbxSend() Response Definition Response Bad FCS Meaning Electrical error CC: 0x4X Semaphore is granted with a Transaction ID of ‘X’ CC: 0x80 Error causing a response timeout. Either due to a rare, internal timing condition or a processor RESET condition or processor S1 state. Retry is appropriate outside of the RESET or S1 states.
Thermal Specifications Figure 6-25. MbxGet() Byte # Byte Definition 0 1 2 3 Client Address Write Length 0x02 Read Length 0x05 Cmd Code 0xd5 4 10 5 11 6 Transaction ID FCS Completion Code 7 10 5 8 11 6 9 LSB Response Data[31:0] 10 11 MSB FCS Note that the 4-byte data response defined above is sent in standard PECI ordering with LSB first and MSB last. Table 6-24. MbxGet() Response Definition Response Aborted Write FCS Meaning Response data is not ready. Command retry is appropriate.
Thermal Specifications 6.3.2.9.2 Transaction ID For all MbxSend() commands that complete successfully, the passing completion code (0x4X) includes a 4-bit Transaction ID (‘X’). That ID is the key to the mailbox and must be sent when retrieving response data and releasing the lock by using the MbxGet() command. The Transaction ID is generated internally by the processor and has no relationship to the originator of the request.
Thermal Specifications 6.3.3 Multi-Domain Commands The Intel Xeon processor 5500 series does not support multiple domains, but it is possible that future products will, and the following tables are included as a reference for domain-specific definitions. Table 6-25. Domain ID Definition Domain ID Domain Number 0b01 0 0b10 1 Table 6-26.
Thermal Specifications Table 6-28. Device Specific Completion Code (CC) Definition Completion Code 0x00..0x3F 0x40 0x4X 0x50..0x7F Description Device specific pass code Command Passed Command passed with a transaction ID of ‘X’ (0x40 | Transaction_ID[3:0]) Device specific pass code CC: 0x80 Error causing a response timeout. Either due to a rare, internal timing condition or a processor RESET condition or processor S1 state. Retry is appropriate outside of the RESET or S1 states.
Thermal Specifications 6.3.6 Temperature Data 6.3.6.1 Format The temperature is formatted in a 16-bit, 2’s complement value representing a number of 1/64 degrees centigrade. This format allows temperatures in a range of ±512°C to be reported to approximately a 0.016°C resolution. Figure 6-26. Temperature Sensor Data Format MSB Upper nibble S x Sign 6.3.6.2 MSB Lower nibble x x x x x LSB Upper nibble x Integer Value (0-511) x x x LSB Lower nibble x x x x x Fractional Value (~0.
Thermal Specifications 6.3.6.4 Reserved Values Several values well out of the operational range are reserved to signal temperature sensor errors. These are summarized in the table below: Table 6-30. Error Codes and Descriptions Error Code 0x8000 Description General Sensor Error (GSE) 6.3.7 Client Management 6.3.7.1 Power-up Sequencing The PECI client is fully reset during processor RESET# assertion.
Thermal Specifications Figure 6-27. PECI Power-up Timeline Vtt VttPwrGd SupplyVcc Bclk VccPwrGd RESET# Mclk CSI training CSI pins uOp execution In Reset PECI Client Status PECI Node ID 6.3.7.2 x Data Not Rdy idle running Reset uCode Boot BIOS Fully Operational 0b1 or 0b0 Device Discovery The PECI client is available on all processors, and positive identification of the PECI revision number can be achieved by issuing the GetDIB() command. Please refer to Section 6.3.2.
Thermal Specifications • MbxSend(), PCIConfigRd() and PCIConfigWr() usage under package C-states may result in increased power consumption because the processor must temporarily return to a C0 state in order to execute the request. The exact power impact of a pop-up to C0 varies by product SKU, the C-state from which the pop-up is initiated, and the negotiated TBIT. Table 6-32. Power Impact of PECI Commands versus C-states Command 6.3.7.
Features 7 Features 7.1 Power-On Configuration (POC) Several options can be configured by hardware. Power-On configuration (POC) functionality is provided by strapping VID signals (see Table 2-3) or sampled on the active-to-inactive transition of RESET#. For specifics on these options, please refer to Table 7-1. Please note that requests to execute Built-In Self Test (BIST) are not selected by hardware, but rather passed across the Intel® QuickPath Interconnect link during initialization.
Features Figure 7-1. PROCHOT# POC Timing Requirements Min Setup (2) Min Hold (106) BCLK CPURESET# Tri-State POC (xxPROCHOT#) Non-FRB assertion of xxPROCHOT# during this window can trigger false tri-state xxPROCHOT# deassertion is not required for FRB Power-On Configuration (POC) logic levels are MUX-ed onto the VID[7:0] signals with 1-5 KΩ pull-up and pull-down resistors located on the baseboard.
Features ‘C-state Range’ field. This field maybe written by BIOS to restrict the range of I/O addresses that are trapped and redirected to MWAIT instructions. Note that when I/O instructions are used, no MWAIT substates can be defined, as therefore the request defaults to have a sub-state or zero, but always assumes the ‘break on EFLAGS.IF==0’ control that can be selected using ECX with an MWAIT instruction. Figure 7-2.
Features 7.2.1.2 C1/C1E State C1/C1E is a low power state entered when all threads within a core execute a HLT or MWAIT(C1E) instruction. The processor thread will transition to the C0 state upon occurrence of an interrupt or an access to the monitored address if the state was entered via the MWAIT instruction. RESET# will cause the processor to initialize itself and return to C0. A System Management Interrupt (SMI) handler will return execution to either Normal state or the C1/C1E state.
Features than C1/C1E but the package low power state is limited to C1/C1E via the PMG_CST_CONFIG_CONTROL MSR. In the C1E state, the processor will automatically transition to the lowest power operating point (lowest supported voltage and associated frequency). When entering the C1E state, the processor will first switch to the lowest bus ratio and then transition to the lower VID. No notification to the system occurs upon entry to C1/C1E.
Features 7.3 Sleep States The processor supports the ACPI sleep states S0, S1, S3, and S4/S5 as shown in. For information on ACPI S-states and related terminology, refer to ACPI Specification. The S-state transitions are coordinated by the processor in response PM Request (PMReq) messages from the chipset. The processor itself will never request a particular S-state. Table 7-4.
Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Intel® Xeon® processor 5500 series will be offered as an Intel boxed processor, however the thermal solution will be sold separately. Unlike previous-generation boxed processors, Intel Xeon processor 5500 series boxed processors will not include thermal solution in the box.
Boxed Processor Specifications 8.1.3 Intel Boxed “Active” Heat Sink Solution The Boxed Active solution will be available for purchase for processors with TDP’s of 80W and lower and will be an aluminum extrusion. This heat sink solution is intended to be used as an active heat sink only for pedestal chassis. Figure 8-1 is a representation of the heat sink solution. Both active solutions will utilize a fan capable of 4-pin pulse width modulated (PWM) control.
Boxed Processor Specifications Figure 8-3. Boxed Passive/Active Combination Heat Sink (with Fan Removed) Figure 8-4. Intel Boxed 25.5 mm Tall Passive Heat Sink Solution 8.1.4 Intel Boxed 25.5mm Tall Passive Heat Sink Solution The boxed 25.5 mm Tall heatsink solution will be available for use with boxed processors that have TDP’s of 95 W and lower. The 25.5 mm Tall passive solution is designed to be used in Blades, 1U, and 2U chassis where ducting is present. The use of a 25.
Boxed Processor Specifications 8.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor solution. 8.2.1 Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones The boxed processor and boxed thermal solution will be sold separately. Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling. Baseboard keepout zones are shown in Figure 8-5 through Figure 8-8.
Intel® Xeon® Processor 5500 Series Datasheet, Volume 1 A B C D 8 7 6 5 8 BALL 1 POSITION 4 LINE REPRESENTS OF OUTERMOST ROWS AND COLUMNS OF SOCKET BALL ARRAY OUTLINE. FOR REFERENCE ONLY SOCKET BODY OUTLINE FOR REFERENCE ONLY 7 6 AS VIEWED FROM PRIMARY SIDE OF THE MOTHERBOARD 36.00 [1.417] SOCKET ILM HOLE PATTERN 41.66 [1.640] CENTERLINE OF OUTER SOCKET BALL ARRAY 47.50 [1.870] SOCKET BODY OUTLINE, FOR REFERENCE ONLY 80.00 [3.150] THERMAL RETENTION HOLE PATTERN 90.00 [3.
A B C D 8 7 6 8 5.00 [0.197 ] 85.00 [3.346 ] 3X 80.00 [3.150 ] 77.90 [3.067 ] 2X 72.50 [2.854 ] 2X 70.600 [2.7795 ] 62.39 [2.456 ] BALL 1 4 49.40 [1.945 ] 30.600 [1.205 ] 29.90 [1.177 ] 9.900 [0.3898 ] 2X 9.400 [0.3701 ] 2X 7.50 [0.295 ] 2X 0.00 [0.000 ] 3.30 [0.130 ] 7 67.70 [2.665 ] 58.000 [2.2835 ] 47.15 [1.856 ] 32.85 [1.293 ] 19.17 [0.755 ] BALL 1 4 22.000 [0.8661 ] 9.60 [0.378 ] 12.30 [0.484 ] 6 AS VIEWED FROM PRIMARY SIDE OF THE MOTHERBOARD (DETAILS) 2X 72.50 [2.
Intel® Xeon® Processor 5500 Series Datasheet, Volume 1 A B C D 8 7 6 5 8 (90.00 ) [3.543] 8X 7 6.00 [0.236 ] (72.20 ) [2.843] DESKTOP BACKPLATE KEEPIN SHOWN FOR REFERENCE ONLY 70.50 [2.776 ] 6 9.50 [0.374 ] 47.15 [1.856 ] 5 AS VIEWED FROM SECONDARY SIDE OF THE MOTHERBOARD (DETAILS) (90.00 ) [3.543] (47.00 ) [1.850] 32.85 [1.293 ] 85.00 [3.346 ] 4 4 0.00 [0.000 ] 85.00 [3.346 ] 75.00 [2.953 ] 62.83 [2.474 ] 49.40 [1.945 ] 30.60 [1.205 ] 17.17 [0.676 ] 5.00 [0.197 ] 0.
7 6 5 8 7 6 5 4 DEPARTMENT R MOVED REVISION HISTORY TABLE TO SHEET 4 CORRECTED SOCKET SOLDERBALL ARRAY & POS 41.66 --> 40.64 (ARRAY SIZE) 44.85 --> 44.70 (ARRAY SIZE) 62.43 --> 62.39 (ARRAY POSITION) 19.17 --> 19.67 (ARRAY POSITION) ADDED TOPSIDE CU PAD CALLOUT FOR ILM HOLES SEE DETAIL A, SHEET 2 REVERTED SOCKET SOLDERBALL ARRAY X DIRECTION SIZE AND POSITION TO REV G. 40.64 --> 41.66 (ARRAY WIDTH) 19.67 --> 19.
Boxed Processor Specifications Figure 8-9.
Boxed Processor Specifications Figure 8-10.
Boxed Processor Specifications Figure 8-11.
Boxed Processor Specifications Figure 8-12.
Boxed Processor Specifications 8.2.2 Boxed Processor Retention Mechanism and Heat Sink Support (URS) Baseboards designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor. Refer to Figure 8-5 for mounting hole dimensions. Figure 8-13 illustrates the Unified Retention System (URS) and the Unified Backplate Assembly.
Boxed Processor Specifications Figure 8-13. Thermal Solution Installation 8.3 Fan Power Supply (“Combo” and “Active” Solution) The 4-pin PWM controlled thermal solution is being offered to help provide better control over pedestal chassis acoustics. This is achieved though more accurate measurement of processor die temperature through the processor’s Digital Thermal Sensors.
Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power header identification and location must be documented in the suppliers platform documentation, or on the baseboard itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket. Table 8-1. Table 8-2.
Boxed Processor Specifications 8.3.1.1 2U Passive / Active Combination Heat Sink Solution Active Configuration: The active configuration of the combination solution is designed to help pedestal chassis users to meet the thermal processor requirements without the use of chassis ducting. It may be still be necessary to implement some form of chassis air guide or air duct to meet the TLA temperature of 40°C depending on the pedestal chassis layout.
Boxed Processor Specifications 8.4 Boxed Processor Contents The Boxed Processor and Boxed Thermal Solution contents are outlined below.
Boxed Processor Specifications 154 Intel® Xeon® Processor 5500 Series Datasheet, Volume 1
