Dual-Core Intel® Xeon® Processor 5200 Series Datasheet August 2008 318590-005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ..................................................................................................... 10 1.2 State of Data .................................................................................................... 13 1.3 References .......................................................................................................
6.3 6.2.1 Intel® Thermal Monitor Features...............................................................85 6.2.2 On-Demand Mode ...................................................................................87 6.2.3 PROCHOT# Signal ..................................................................................88 6.2.4 FORCEPR# Signal ...................................................................................88 6.2.5 THERMTRIP# Signal ..........................................................
Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 3-1 3-2 3-3 3-4 3-5 3-6 3-7 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 7-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 Input Device Hysteresis ..................................................................................... 25 Dual-Core Intel® Xeon® Processor E5200 Series Load Current versus Time.............. 30 Dual-Core Intel® Xeon® Processor X5200 Series Load Current versus Time .............
Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 3-1 3-2 3-3 4-1 4-2 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 7-1 7-2 8-1 8-2 8-3 6 Dual-Core Intel® Xeon® Processor 5200 Series ....................................................10 Core Frequency to FSB Multiplier Configuration ......................................................17 BSEL[2:0] Frequency Table .................................................................................
Revision History Revision Description Date 001 Initial release 002 Added product information for Dual-Core Intel® Xeon® Processor L5238. November 2007 March 2008 003 Added product information for Dual-Core Intel® Xeon® Processor L5200 Series.
Dual-Core Intel® Xeon® Processor 5200 Series Datasheet
1 Introduction The Dual-Core Intel® Xeon® Processor 5200 Series is a server/workstation processor utilizing two 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. The processor is manufactured on Intel’s 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The Dual-Core Intel® Xeon® Processor 5200 Series maintains the tradition of compatibility with IA-32 software.
Monitor software enabling multiple, independent software environments inside a single platform. Further details on Intel Virtualization Technology can be found at http://developer.intel.com/technology/platform-technology/virtualization/index.htm. The Dual-Core Intel® Xeon® Processor 5200 Series is intended for high performance server and workstation systems.
Commonly used terms are explained here for clarification: • Dual-Core Intel® Xeon® Processor 5200 Series - Intel 64-bit microprocessor intended for dual processor servers and workstations based on Intel’s 45 nanometer process, in the PC-LGA 771 package with two processor cores. For this document “processors” is used as the generic term for the “Dual-Core Intel® Xeon® Processor 5200 Series processor”.
mounted on a pinless substrate with 771 lands, and includes an integrated heat spreader (IHS). • LGA771 socket – The Dual-Core Intel® Xeon® Processor 5200 Series interfaces to the baseboard through this surface mount, 771 Land socket. See the LGA771 Socket Design Guidelines for details regarding this socket. • Processor core – Processor core with integrated L1 cache. L2 cache and system bus interface are shared between the two cores on the die.
communicates readings from the processor’s digital thermometer. PECI replaces the thermal diode available in previous processors. • Intel® Virtualization Technology – Processor virtualization, which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform.
§ 14
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications 2 Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications 2.1 Front Side Bus and GTLREF Most Dual-Core Intel® Xeon® Processor 5200 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Twenty two lands are specified as VTT, which provide termination for the FSB and provides power to the I/O buffers. The platform must implement a separate supply for these lands which meets the VTT specifications outlined in Table 2-12. 2.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous processor generations, the Dual-Core Intel® Xeon® Processor 5200 Series core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during manufacturing. The default setting is for the maximum speed of the processor.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-2. 2.4.2 BSEL[2:0] Frequency Table BSEL2 BSEL1 BSEL0 Bus Clock Frequency 0 0 0 266.66 MHz 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 333.33 MHz 1 0 1 Reserved 1 1 0 400 MHz 1 1 1 Reserved PLL Power Supply An on-die PLL filter solution is implemented on the Dual-Core Intel® Xeon® Processor 5200 Series.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications The Dual-Core Intel® Xeon® Processor 5200 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-3. Voltage Identification Definition HEX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX HEX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 7A 1 1 1 1 0 1 0.8500 3C 0 1 1 1 1 0 1.2375 78 1 1 1 1 0 0 0.8625 3A 0 1 1 1 0 1 1.2500 76 1 1 1 0 1 1 0.8750 38 0 1 1 1 0 0 1.2625 74 1 1 1 0 1 0 0.8875 36 0 1 1 0 1 1 1.2750 72 1 1 1 0 0 1 0.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-4. Loadline Selection Truth Table for LL_ID[1:0] LL_ID1 LL_ID0 0 0 Reserved 0 1 Dual-Core Intel® Xeon® Processor 5100 series, Dual-Core Intel® Xeon® Processor 5200 Series, and Quad-Core Intel® Xeon® Processor 5400 Series 1 0 Reserved 1 1 Quad-Core Intel® Xeon® processor 5300 series Note: Table 2-5. The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications The TESTHI signals must use individual pull-up resistors as detailed below. A matched resistor must be used for each signal: • TESTHI8 - cannot be grouped with other TESTHI signals • TESTHI9 - cannot be grouped with other TESTHI signals • TESTHI10 – cannot be grouped with other TESTHI signals • TESTHI11 – cannot be grouped with other TESTHI signals • TESTHI12 - cannot be grouped with other TESTHI signals 2.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-6.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#, and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-10. PECI DC Electrical Limits Notes1 Symbol Definition and Conditions Min Max Units Vin Input Voltage Range -0.150 VTT V Vhysteresis Hysteresis 0.1 * VTT N/A V Vn Negative-edge threshold voltage 0.275 * VTT 0.500 * VTT V Vp Positive-edge threshold voltage 0.550 * VTT 0.725 * VTT V Isource High level output source (VOH = 0.75 * VTT) -6.0 N/A mA Isink Low level output sink (VOL = 0.25 * VTT) 0.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications 2.11 Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency, core frequency, power segments, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel. Combining processors from different power segments is also not supported.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-11. Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit V VCC Core voltage with respect to VSS -0.30 1.35 VTT FSB termination voltage with respect to VSS -0.30 1.45 V TCASE Processor case temperature See Chapter 6 See Chapter 6 °C TSTORAGE Storage temperature -40 85 °C Notes1, 2 3, 4, 5 Notes: 1.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-12. Voltage and Current Specifications (Sheet 1 of 2) Symbol 28 Parameter Min VID VID range VCC VCC for processor core Launch - FMB Vcc_boot Default VCC Voltage for initial power up VVID_STEP VID step size during a transition VVID_SHIFT Total allowable DC load line shift from VID steps VTT FSB termination voltage (DC + AC specification) 1.045 VCCPLL PLL supply voltage (DC + AC specification) 1.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-12.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications . Figure 2-2. 10. This specification refers to the total reduction of the load line due to VID transitions below the specified VID. 11. Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings. 12. This specification applies to the VCCPLL land. 13. Baseboard bandwidth is limited to 20 MHz. 14.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Figure 2-4. Dual-Core Intel® Xeon® Processor L5200 Series Load Current versus Time Sustained Current (A) 60 55 50 45 40 35 30 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s) Notes: 1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Table 2-13.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications 3. The loadlines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 11.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Figure 2-6. Dual-Core Intel® Xeon® Processor X5200 Series VCC Static and Transient Tolerance Load Lines Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 VID - 0.000 VID - 0.020 VCC Maximum VID - 0.040 Vcc [V] VID - 0.060 VID - 0.080 VID - 0.100 VCC Typical VID - 0.120 VCC Minimum VID - 0.140 VID - 0.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.13.2 for VCC overshoot specifications. 2. Refer to Table 2-12 for processor VID information. 3. Refer to Table 2-13 for VCCStatic and Transient Tolerance 4. The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Measured at 0.2*VTT. 3. VOH is determined by value of the external pullup resistor to VTT. Refer to platform design guide for details. 4. For VIN between 0 V and VOH. 2.13.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications 2.14 AGTL+ FSB Specifications Routing topologies are dependent on the processors supported and the chipset used in the design. Please refer to the appropriate platform design guidelines for specific implementation details. In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 2-8 for details on which signals do not include on-die termination.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-19. FSB Differential BCLK Specifications (Sheet 2 of 2) Symbol Parameter VOS Overshoot VUS Undershoot VRBM VTR ILI ERRefclk-diffRrise ERRefclk-diff-Fall Min Typ Max Unit Figure Notes1 N/A N/A 1.150 V 2-10 4 -0.300 N/A N/A V 2-10 5 Ringback Margin 0.200 N/A N/A V 2-10 6 Threshold Region VCROSS 0.100 N/A VCROSS + 0.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Figure 2-10. Differential Clock Waveform Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tp Tp = T1: BCLK[1:0] period Figure 2-11. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 250 + 0.
Mechanical Specifications 3 Mechanical Specifications The Dual-Core Intel® Xeon® Processor 5200 Series is packaged in a Flip Chip Land Grid Array (FC-LGA) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771 lands. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink.
Mechanical Specifications Figure 3-2. Note: 40 Dual-Core Intel® Xeon® Processor 5200 Series Package Drawing (Sheet 1 of 3) Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal/Mechanical Design Guidelines.
Mechanical Specifications Figure 3-3.
Mechanical Specifications Figure 3-4.
Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. Decoupling capacitors are typically mounted to either the topside or landside of the package substrate. See Figure 3-4 for keepout zones. 3.3 Package Loading Specifications Table 3-1 provides dynamic and static load specifications for the processor package.
Mechanical Specifications 3.4 Package Handling Guidelines Table 3-2 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 3-2. Package Handling Guidelines Parameter Maximum Recommended Units Notes Shear 311 70 N lbf 1,4,5 Tensile 111 25 N lbf 2,4,5 Torque 3.95 35 N-m LBF-in 3,4,5 Notes: 1.
Mechanical Specifications Figure 3-5. Processor Top-side Markings (Example) GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 Legend: Mark Text (Production Mark): GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 3400DP/6M/1600 Intel ® Xeon ® Proc# SXXX COO i (M) © ‘06 FPO ATPO S/N Note: 3.9 2D matrix is required for engineering samples only (encoded with ATPO-S/N).
Mechanical Specifications Figure 3-7.
Land Listing 4 Land Listing 4.1 Dual-Core Intel® Xeon® Processor 5200 Series Pin Assignments This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number. 4.1.1 Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 1 of 20) Pin Name Pin No. Signal Buffer Type Direction Table 4-1.
Land Listing Table 4-1. Pin Name D01# Land Listing by Land Name (Sheet 3 of 20) Pin No. Signal Buffer Type Direction Table 4-1. Pin Name Land Listing by Land Name (Sheet 4 of 20) Pin No.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 5 of 20) Pin No. Signal Buffer Type Direction Table 4-1. Pin Name Land Listing by Land Name (Sheet 6 of 20) Pin No.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 7 of 20) Pin No. Signal Buffer Type RESERVED AM2 RESET# G23 Common Clk RS0# B3 Common Clk RS1# F5 Common Clk RS2# A3 Common Clk Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 8 of 20) Pin No.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 9 of 20) Pin No. Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 10 of 20) Pin No.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 11 of 20) Pin No. Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 12 of 20) Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 13 of 20) Pin Name Pin No. Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 14 of 20) Pin No.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 15 of 20) Pin No. Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 16 of 20) Pin No.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 17 of 20) Pin No. VSS B20 VSS VSS Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 18 of 20) Pin No.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 19 of 20) Pin No. VSS M1 VSS VSS Signal Buffer Type Table 4-1. Direction Land Listing by Land Name (Sheet 20 of 20) Pin Name Pin No.
Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 1 of 20) Pin No. A10 Pin Name D08# Signal Buffer Type Source Sync A11 D09# Source Sync A12 VSS Power/Other A13 RESERVED A14 D50# Source Sync A15 VSS Power/Other A16 DSTBN3# Source Sync Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 3 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 5 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. AJ9 Land Listing by Land Number (Sheet 7 of 20) Pin Name VCC Signal Buffer Type Direction Power/Other Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 9 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 11 of 20) Pin Name Signal Buffer Type C2 BNR# Common Clk C20 DBI3# C21 D58# C22 VSS Power/Other C23 RESERVED Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 13 of 20) Pin Name Signal Buffer Type Direction F10 VSS Power/Other F11 D23# Source Sync F12 D24# Source Sync F13 VSS Power/Other F14 D28# Source Sync Input/Output Input/Output Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 15 of 20) Pin Name Signal Buffer Type Direction H29 VSS Power/Other H3 VSS Power/Other H30 BSEL1 CMOS Async Output H4 RSP# Common Clk H5 BR1# Common Clk H6 VSS H7 VSS H8 H9 Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 17 of 20) Pin Name Signal Buffer Type Direction M3 STPCLK# CMOS Async Input M30 VCC Power/Other M4 A07# Source Sync Input/Output Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. U3 Land Listing by Land Number (Sheet 19 of 20) Pin Name AP1# Signal Buffer Type Common Clk Direction Input/Output Table 4-2. Pin No.
Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (Sheet 1 of 8) Name A[37:3]# Type Description Notes 238-byte I/O A[37:3]# (Address) define a physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins of all agents on the FSB. A[37:3]# are protected by parity signals AP[1:0]#.
Signal Definitions Table 5-1. Signal Definitions (Sheet 2 of 8) Name Type Description I The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
Signal Definitions Table 5-1. Signal Definitions (Sheet 3 of 8) Name D[63:0]# Type Description Notes I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period.
Signal Definitions Table 5-1. Signal Definitions (Sheet 4 of 8) Name Description Notes DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor FSB agents. 3 DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#.
Signal Definitions Table 5-1. Signal Definitions (Sheet 5 of 8) Name Type Description Notes IERR# O IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. This signal does not have on-die termination.
Signal Definitions Table 5-1. Signal Definitions (Sheet 6 of 8) Name 72 Type Description Notes MS_ID[1:0] O These signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying. These signals are not connected to the processor die. Both the bits 0 and 1 are logic 0 and pulled to ground on the Dual-Core Intel® Xeon® Processor 5200 Series package.
Signal Definitions Table 5-1. Signal Definitions (Sheet 7 of 8) Name Type Description STPCLK# I STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state.
Signal Definitions Table 5-1. Signal Definitions (Sheet 8 of 8) Name Type Description VID_SELECT O VID_SELECT is an output from the processor which selects the appropriate VID table for the Voltage Regulator. This signal is not connected to the processor die. This signal is a no-connect on the Dual-Core Intel® Xeon® Processor 5200 Series package. VSS_DIE_SENSE VSS_DIE_SENSE2 O VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated, low impedance connection to the processor core power and ground.
Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Dual-Core Intel® Xeon® Processor 5200 Series requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Thermal Specifications The Dual-Core Intel® Xeon® Processor E5200 Series and Dual-Core Intel® Xeon® Processor L5200 Series supports a single Thermal Profile (see Figure 6-1; Table 6-1Table 6-6).With this Thermal Profile, it is expected that the Thermal Control Circuit (TCC) would only be activated for very brief periods of time when running the most power-intensive applications.
Thermal Specifications Table 6-1. Dual-Core Intel® Xeon® Processor E5200 Series Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes 65 5 See Figure 6-1; Table 6-2; 1, 2, 3, 4, 5 Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC.
Thermal Specifications Table 6-2. Table 6-3. Dual-Core Intel® Xeon® Processor E5200 Series Thermal Profile Table Power (W) TCASE_MAX (°C) 0 43.0 5 44.8 10 46.5 15 48.3 20 50.1 25 51.9 30 53.6 35 55.4 40 57.2 45 58.9 50 60.7 55 62.5 60 64.2 65 66.
Thermal Specifications Figure 6-2. Dual-Core Intel® Xeon® Processor X5200 Series Thermal Profiles A and B TCASE_MAX is a thermal solution design point. In actuality, units will not significantly exceed TCASE_MAX_A due to TCC activation. 70 65 Tcase [C] 60 Thermal Profile B (1U) Y = 0.289*x +42.9 55 Thermal Profile A (2U) Y = 0.235*x +42.2 50 45 40 0 10 20 30 40 Power [W] 50 60 70 80 Notes: 1.
Thermal Specifications Table 6-4. Table 6-5. Table 6-6. Dual-Core Intel® Xeon® Processor X5200 Series Thermal A Profile Table (Sheet 2 of 2) Power (W) TCASE_MAX (°C) 50 54.0 55 55.1 60 56.3 65 57.5 70 58.7 75 59.8 80 61.0 Dual-Core Intel® Xeon® Processor X5200 Series Thermal B Profile Table Power (W) TCASE_MAX (°C) 0 42.9 5 44.3 10 45.8 15 47.2 20 48.7 25 50.1 30 51.6 35 53.0 40 54.5 45 55.9 50 57.4 55 58.8 60 60.2 65 61.7 70 63.1 75 64.6 80 66.
Thermal Specifications Figure 6-3. Dual-Core Intel® Xeon® Processor L5200 Series Thermal Profile 60 Tcase [C] 55 50 Thermal Profile Y = 0.354*x +41.8 45 40 0 10 20 30 40 Power [W] Notes: 1. Dual-Core Intel® Xeon® Processor L5200 Series Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-7 for discrete points that constitute the thermal profile. 2.
Thermal Specifications Table 6-8. Dual-Core Intel® Xeon® Processor L5238 Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes 35 5 See Figure 6-4; Table 6-8 1, 2, 3, 4, 5 Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC.
Thermal Specifications Table 6-9. Dual-Core Intel® Xeon® Processor L5238 Thermal Profile Table Power (W) Nominal TCASE_MAX (°C) Short-term TCASE_MAX (°C) 0 45 60 5 49 64 10 52 67 15 56 71 20 60 75 25 64 79 30 67 82 35 71 86 Table 6-10. Dual-Core Intel® Xeon® Processor L5215 Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes 20 5 See Figure 6-5; Table 6-11 1, 2, 3, 4, 5 Notes: 1.
Thermal Specifications 2. 3. 4. 5. 6. Implementation of the Dual-Core Intel® Xeon® Processor L5215 Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).
Thermal Specifications Figure 6-6. Case Temperature (TCASE) Measurement Location Note: Figure is not to scale and is for reference only. 6.2 Processor Thermal Features 6.2.1 Intel® Thermal Monitor Features Dual-Core Intel® Xeon® Processor 5200 Series provides two thermal monitor features, Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2. The Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2 must both be enabled in BIOS for the processor to be operating within specifications.
Thermal Specifications When the Intel® Thermal Monitor 1 is enabled, and a high temperature situation exists (that is, TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30 - 50%). Cycle times are processor speed dependent and will decrease as processor core frequencies increase.
Thermal Specifications service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency. Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps in order to support Intel® Thermal Monitor 2.
Thermal Specifications bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. 6.2.
Thermal Specifications 6.3 Platform Environment Control Interface (PECI) 6.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. Figure 6-8 shows an example of the PECI topology in a system with Dual-Core Intel® Xeon® Processor 5200 Series. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices.
Thermal Specifications Figure 6-9. Conceptual Fan Control Diagram of PECI-based Platforms T CONTROL Setting TCC Activation Temperature Max PECI = 0 Fan Speed (RPM ) PECI = -10 M in PECI = -20 Temperature (not intended to depict actual implementation) 6.3.1.2 Processor Thermal Data Sample Rate and Filtering The Digital Thermal Sensor (DTS) provides an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals.
Thermal Specifications 6.3.2.3 PECI Fault Handling Requirements PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and thus given operating conditions that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures.
Thermal Specifications 92
Features 7 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Dual-Core Intel® Xeon® Processor 5200 Series samples its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifics on these options, please refer to Table 7-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features 7.2.1 Normal State This is the normal operating state for the processor. 7.2.2 HALT or Extended HALT State The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state must be enabled for the processor to remain within its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. 7.2.2.1 HALT State HALT is a low power state entered when the processor have executed the HALT or MWAIT instruction.
Features Table 7-2. Extended HALT Maximum Power (Sheet 2 of 2) Max Unit Notes 1 PEXTENDED_HALT Dual-Core Intel® Xeon® Processor E5240 Symbol Extended HALT State Power Parameter Min Typ 8 W 2 PEXTENDED_HALT Dual-Core Intel® Xeon® Processor L5200 Series Extended HALT State Power 6 W 2 PEXTENDED_HALT Dual-Core Intel® Xeon® Processor L5238 Extended HALT State Power 6 W 3 Notes: 1.
Features 7.2.3 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no later than 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state. All processor cores will enter the Stop-Grant state once the STPCLK# pin is asserted.
Features 7.2.4.2 Extended HALT Snoop State The Extended HALT Snoop state is the default Snoop state when the Extended HALT state is enabled via the BIOS. The processor will remain in the lower bus to core frequency ratio and VID operating point of the Extended HALT state. While in the Extended HALT Snoop state, snoops and interrupt transactions are handled the same way as in the HALT Snoop state. After the snoop is serviced or the interrupt is latched, the processor will return to the Extended HALT state.
Features 98
Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Dual-Core Intel® Xeon® Processor 5200 Series will be offered as an Intel boxed processor.
Boxed Processor Specifications Figure 8-1. Boxed Dual-Core Intel® Xeon® Processor 5200 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan) Figure 8-2.
Boxed Processor Specifications Figure 8-3. 2U Passive Dual-Core Intel® Xeon® Processor 5200 Series Thermal Solution (Exploded View) Notes: 1. The heat sinks represented in these images are for reference only, and may not represent the final boxed processor heat sinks. 2. The screws, springs, and standoffs will be captive to the heat sink. This image shows all of the components in an exploded view. 3. It is intended that the CEK spring will ship with the base board and be pre-attached prior to shipping.
Boxed Processor Specifications Figure 8-4.
Boxed Processor Specifications Figure 8-5.
Boxed Processor Specifications Figure 8-6.
Boxed Processor Specifications Figure 8-7.
Boxed Processor Specifications Figure 8-8.
Boxed Processor Specifications Figure 8-9.
Boxed Processor Specifications Figure 8-10.
Boxed Processor Specifications 8.2.2 Boxed Processor Heat Sink Weight 8.2.2.1 Thermal Solution Weight The 1U passive/3U+ active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams. Note that this is per processor, a dual processor system will have up to 2010 grams total mass in the heat sinks. This large mass will require a minimum chassis stiffness to be met in order to withstand force during shock and vibration.
Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power header identification and location must be documented in the suppliers platform documentation, or on the baseboard itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket. Table 8-1. Table 8-2.
Boxed Processor Specifications around the heatsink. It is assumed that a 40°C TLA is met. This requires a superior chassis design to limit the TRISE at or below 5°C with an external ambient temperature of 35°C. These specifications apply to both copper and aluminum heatsink solutions. Following these guidelines allows the designer to meet Dual-Core Intel® Xeon® Processor 5200 Series Thermal Profile and conform to the thermal requirements of the processor. 8.3.2.
Boxed Processor Specifications § 112
Debug Tools Specifications 9 Debug Tools Specifications Please refer to the appropriate platform design guidelines for information regarding debug tool specifications. Section 1.3 provides collateral details. 9.1 Debug Port System Requirements The Dual-Core Intel® Xeon® Processor 5200 Series debug port is the command and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the processors for system debug.
Debug Tools Specifications 9.3.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI plugs into the socket, while the processor plugs into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor.
